Current sharing control circuit

Abstract

The utility model discloses a current sharing control circuit. The current sharing control circuit comprises a first power unit, a second power unit, a detection unit and a control unit, the first power unit comprises a first switch unit and a first output branch; the second power unit comprises a second switch unit and a second output branch; the detection unit is used for detecting a first current on the first output branch, a second current on the second output branch and a total current on the first output end; the control unit generates a first control signal based on the first adjustment signal and the second adjustment signal, and generates a second control signal based on the first adjustment signal and the third adjustment signal. According to the current-sharing control circuit of the utility model, the current dynamic balance of each switch unit is realized, and the output voltage balance and the output power balance of the first power unit and the second power unit which are connected in series are ensured, so that the temperature rise of each power module is consistent, and the reliability of the power supply is greatly improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to current control technical field, specifically about a current -sharing control circuit. BACKGROUND

[0002] In the battery test equipment, with the explosive growth of energy storage battery scale, the test equipment of high voltage and large current energy storage system is more and more, and the output voltage level is continuously improved from 1000V to 1500V, 1600V or even 2000V, and the output power is continuously improved from several hundred kilowatts to several megawatts, with the improvement of voltage and current level, multiple IGBT or Sic power modules are needed to be connected in parallel to improve the output current capacity, and the single power supply after parallel connection is connected in series to improve the output voltage capacity, and the traditional module parallel connection mode cannot guarantee the current sharing of the module, so as to reduce the use current of the module to ensure the reliability, which causes a certain waste.

[0003] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present utility model and should not be regarded as an acknowledgment or any form of suggestion that it forms prior art of this utility model. SUMMARY

[0004] The utility model aims at providing a current -sharing control circuit, which can realize current dynamic balance under the condition of outputting high voltage and large current.

[0005] In order to realize the above-mentioned purpose, the utility model provides the technical scheme as follows in a specific embodiment: a current -sharing control circuit, comprising: a first power unit, a second power unit, a detection unit and a control unit.

[0006] The first power unit comprises a plurality of first switch units and a plurality of first output branches, each first switch unit is connected between a first input end and a second input end, the first end of each first output branch is connected with the corresponding first switch unit, the second ends of each first output branch are connected to form a first output end, each first switch unit controls the connection between the first input end and the first output branch or controls the connection between the second input end and the first output branch based on a group of first control signals;

[0007] The second power unit comprises a plurality of second switch units and a plurality of second output branches, each second switch unit is connected between a third input end and a fourth input end, the third input end is connected with the second input end, the first end of each second output branch is connected with the corresponding second switch unit, the second ends of each second output branch are connected to form a second output end, each second switch unit controls the connection between the third input end and the second output branch or controls the connection between the fourth input end and the second output branch based on a group of second control signals.

[0008] The detection unit is configured to detect and obtain the first currents on each first output branch, the second currents on each second output branch, and the total current on the first output terminal or the second output terminal;

[0009] The control unit is configured to generate a first adjustment signal within a first clipping range based on a deviation between the total current and a total preset current, generate a second adjustment signal within a second clipping range based on a deviation between each first current and a corresponding first preset current, generate a third adjustment signal within the second clipping range based on a deviation between each second current and a corresponding second preset current, and generate a first control signal based on the first adjustment signal and each second adjustment signal, generate a second control signal based on the first adjustment signal and each third adjustment signal.

[0010] In one or more embodiments of the present application, the control unit comprises a first adjustment module, a plurality of second adjustment modules, a plurality of third adjustment modules, a plurality of first output modules, and a plurality of second output modules.

[0011] The first adjustment module generates a first adjustment signal within a first clipping range based on a deviation between the total current and a total preset current.

[0012] Each second adjustment module generates a corresponding second adjustment signal within a second clipping range based on a deviation between a corresponding first current and a corresponding first preset current, and each first output module generates a corresponding first control signal within the first clipping range based on the first adjustment signal and the corresponding second adjustment signal.

[0013] Each third adjustment module generates a corresponding third adjustment signal within the second clipping range based on a deviation between a corresponding second current and a corresponding second preset current, and each second output module generates a corresponding second control signal within the first clipping range based on the first adjustment signal and the corresponding third adjustment signal.

[0014] In one or more embodiments of the present application, the first adjustment module comprises a first PI regulator and a first saturation clipper, a first input terminal of the first PI regulator is configured to receive the total current, a second input terminal of the first PI regulator is configured to receive the total preset current, an input terminal of the first saturation clipper is connected to an output terminal of the first PI regulator, and an output terminal of the first saturation clipper is configured to output the first adjustment signal, the first saturation clipper is configured to clip the output signal of the first PI regulator within the first clipping range.

[0015] In one or more embodiments of the utility model, the second adjusting module includes first multiplier, second PI regulator and second saturation limiter, the first multiplier is used for obtaining first preset current based on total preset current, the first input end of second PI regulator is used for receiving first preset current, the second input end of second PI regulator is used for receiving first current, the output end of second PI regulator is connected with the input end of second saturation limiter, the output end of second saturation limiter is used for outputting second adjusting signal, second saturation limiter is used for limiting the output signal of second PI regulator in second amplitude range, and / or

[0016] The third adjusting module includes second multiplier, inverter, third PI regulator and fourth saturation limiter, the second multiplier is used for obtaining second preset current based on total preset current, the first input end of third PI regulator is used for receiving second preset current, the inverter is used for inverting second current, the second input end of third PI regulator is used for receiving inverted second current, the output end of third PI regulator is connected with the input end of fourth saturation limiter, the output end of fourth saturation limiter is used for outputting third adjusting signal, and the fourth saturation limiter is used for limiting the output signal of third PI regulator in second amplitude range.

[0017] In one or more embodiments of the utility model, the first output module includes first adder, third saturation limiter and first processing module, the first input end of first adder is connected with first adjusting module to receive first adjusting signal, the second input end of first adder is connected with second adjusting module to receive second adjusting signal, the output end of first adder is connected with third saturation limiter to limit the signal generated by the sum of first adjusting signal and second adjusting signal in first amplitude range, and the first processing module is connected with third saturation limiter to generate a group of first control signals by processing the signal output by third saturation limiter.

[0018] In one or more embodiments of the utility model, the second output module includes second adder, fifth saturation limiter and second processing module, the first input end of second adder is connected with first adjusting module to receive first adjusting signal, the second input end of second adder is connected with third adjusting module to receive third adjusting signal, the output end of second adder is connected with fifth saturation limiter to limit the signal generated by the sum of first adjusting signal and third adjusting signal in first amplitude range, and the second processing module is connected with fifth saturation limiter to generate a group of second control signals by processing the signal output by fifth saturation limiter.

[0019] In one or more embodiments of the utility model, the first output branch includes first inductance, first end of first inductance is the first end of first output branch, second end of first inductance is the second end of first output branch.

[0020] In one or more embodiments of the utility model, the second output branch includes second inductance, first end of second inductance is the first end of second output branch, second end of second inductance is the second end of second output branch.

[0021] In one or more embodiments of the utility model, the first switch unit includes first transistor and second transistor, second end of first transistor is connected with first input end, first end of first transistor is connected with second end of second transistor and first end of first output branch, first end of second transistor is connected with second input end, control end of first transistor and control end of second transistor are used to receive a group of first control signals, and a group of first control signals are used to control first transistor to open, second transistor to shut off or control second transistor to open, first transistor to shut off;And / or

[0022] The second switch unit includes third transistor and fourth transistor, second end of third transistor is connected with third input end, first end of third transistor is connected with second end of fourth transistor and first end of second output branch, first end of fourth transistor is connected with fourth input end, control end of third transistor and control end of fourth transistor are used to receive a group of second control signals, and a group of second control signals are used to control third transistor to open, fourth transistor to shut off or control fourth transistor to open, third transistor to shut off.

[0023] In one or more embodiments of the utility model, the first power unit further includes first capacitor and / or second capacitor, first end of first capacitor is connected with first input end, second end of first capacitor is connected with second input end, first end of second capacitor is connected with first output end, second end of second capacitor is connected with second input end;And / or

[0024] The second power unit further includes third capacitor and / or fourth capacitor, first end of third capacitor is connected with third input end, second end of third capacitor is connected with fourth input end, first end of fourth capacitor is connected with third input end, second end of fourth capacitor is connected with second output end.

[0025] Compared with the prior art, the current equalization control circuit of the utility model, connect multiple first switch units and first output branch parallelly, connect multiple second switch units and second output branch parallelly, then connect the first power unit and the second power unit in series, thereby generating the ability of outputting high voltage and large current, through the detection unit, the first current on each first output branch, the second current on each second output branch and the total current on the first output end or the second output end are detected and obtained, through the control unit, the control signal of the switch unit is generated based on the total current and the partial current on each output branch, through the output range of each signal is limited in the way that the first adjustment module is combined with the second adjustment module and the third adjustment module, thereby realizing the current dynamic balance of each switch unit, also ensuring the output voltage balance and the output power balance of the first power unit and the second power unit in series, making the temperature rise of each power module (transistor) consistent, greatly improving the reliability of the power supply and the utilization rate of each power module (transistor). BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments in the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creating labor.

[0027] Figure 1 It is the circuit schematic diagram of the first power unit, the second power unit and the detection unit of the current equalization control circuit in an embodiment of the utility model.

[0028] Figure 2 It is the partial circuit schematic diagram of the control unit of the current equalization control circuit in an embodiment of the utility model.

[0029] Figure 3 It is another partial circuit schematic diagram of the control unit of the current equalization control circuit in an embodiment of the utility model.

[0030] Figure 4 It is the waveform diagram of each first control signal and each first current when charging the battery unit in an embodiment of the utility model.

[0031] Figure 5 It is the waveform diagram of each second control signal and each second current when charging the battery unit in an embodiment of the utility model.

[0032] Figure 6For the embodiment of the utility model in the battery unit is charging, through adjusting the duty cycle of each first control signal to balance the first current and through adjusting the duty cycle of each second control signal to balance the second current waveform schematic diagram.

[0033] Figure 7 For the embodiment of the utility model in the battery unit is discharging, the waveform diagram of each first control signal and each first current.

[0034] Figure 8 For the embodiment of the utility model in the battery unit is discharging, the waveform diagram of each second control signal and each second current.

[0035] Figure 9 For the embodiment of the utility model in the battery unit is discharging, the waveform diagram of each second control signal and each second current.

[0036] Figure 10 For the embodiment of the utility model in the battery unit is discharging, through adjusting the duty cycle of each first control signal to balance the first current and through adjusting the duty cycle of each second control signal to balance the second current waveform schematic diagram.

[0037] Figure 11 For the embodiment of the utility model in the battery unit is discharging, the waveform diagram of each first control signal and each first current. DETAILED DESCRIPTION

[0038] In order to make the person skilled in the art better understand the technical scheme in the utility model, the technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the drawings in the embodiment of the utility model, obviously, the described embodiment is only a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by the person skilled in the art without making creative labor should belong to the protection scope of the utility model.

[0039] The "coupling" or "connection" or "connection" in the specification includes both direct connection and indirect connection. Indirect connection is the connection through intermediate medium, such as the connection through electrically conductive medium, which can have parasitic inductance or parasitic capacitance;Indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through switching, following circuit or other circuits or components. In addition, in the utility model, for example, the words such as "first", "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between the technical features.

[0040] In the detailed description of the application, reference is made to the accompanying drawings, which form a part thereof, in which like numerals refer to like parts throughout the several views and in which an exemplary embodiment is shown by way of example. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0041] Various operations can be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations can not be performed in the order of presentation. Operations described can be performed in a different order than the described embodiment. Various additional operations can be performed and / or described operations can be omitted in additional embodiments.

[0042] For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0043] Various components, devices, etc. can be referred to herein in singular form, or in the plural form, but this is merely for convenience and brevity, and in no way should be construed as limiting the scope of this disclosure to only a single item. For example, a component can include plurality of such components, and vice versa.

[0044] The specification describes using the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising", "including", "having" and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0045] As Figure 1 , Figure 2 and Figure 3 A current-sharing control circuit in one embodiment of the utility model, including: first power unit 10, second power unit 20, detection unit 30 and control unit.

[0046] First power unit 10 includes a plurality of first switch unit and a plurality of first output branch, each first switch unit is connected between first input end a1 and second input end a2, the first end of each first output branch is connected with corresponding first switch unit, the second end of each first output branch is connected to form first output end O1, each first switch unit controls first input end a1 and first output branch to be connected or controls second input end a2 and first output branch to be connected based on a group of first control signal.

[0047] The second power unit 20 comprises a plurality of second switch units and a plurality of second output branches, each second switch unit is connected between a third input end b1 and a fourth input end b2, the third input end b1 is connected with the second input end a2, a first end of each second output branch is connected with a corresponding second switch unit, second ends of the second output branches are connected to form a second output end O2, and each second switch unit controls the connection between the third input end b1 and the second output branch or controls the connection between the fourth input end b2 and the second output branch based on a group of second control signals.

[0048] The first input end a1 and the second input end a2 are simultaneously connected with the first power module AC-DC1, the third input end b1 and the fourth input end b2 are simultaneously connected with the second power module AC-DC2, and the first output end O1 and the second output end O2 are simultaneously connected with the battery unit BATTERY.

[0049] The detection unit 30 is configured to detect and obtain the first current on each first output branch, the second current on each second output branch, and the total current Isum on the first output end O1 or the second output end O2.

[0050] The control unit is configured to generate a first adjustment signal within a first clipping range based on a deviation between the total current Isum and a total preset current Iset, generate a second adjustment signal within a second clipping range based on a deviation between each first current and a corresponding first preset current, generate a third adjustment signal within the second clipping range based on a deviation between each second current and a corresponding second preset current, and generate a group of first control signals based on the first adjustment signal and each second adjustment signal, and generate a group of second control signals based on the first adjustment signal and each third adjustment signal.

[0051] The control unit comprises a first adjustment module, a plurality of second adjustment modules, a plurality of third adjustment modules, a plurality of first output modules, and a plurality of second output modules.

[0052] The first adjustment module generates a first adjustment signal within a first clipping range based on a deviation between the total current Isum and a total preset current Iset.

[0053] Each second adjustment module generates a corresponding second adjustment signal within a second clipping range based on a deviation between a corresponding first current and a corresponding first preset current, and each first output module generates a corresponding group of first control signals within the first clipping range based on the first adjustment signal and the corresponding second adjustment signal.

[0054] Each third adjusting module generates a corresponding third adjusting signal within a second clipping range based on a deviation between the corresponding second current and a corresponding second preset current, and each second output module generates a corresponding set of second control signals within a first clipping range based on the first adjusting signal and the corresponding third adjusting signal.

[0055] In different application scenarios, the number of the first switch units, the first output branches, the second switch units and the second output branches can be set as needed, such as Figure 1 As shown in the figure, in an embodiment, the number of the first switch units, the first output branches, the second switch units and the second output branches are all set to three, and the following will be described in detail taking three first switch units 11, 12, 13, three first output branches 14, 15, 16, three second switch units 21, 22, 23 and three second output branches 24, 25, 26 as examples.

[0056] Each first switch unit and second switch unit includes two transistors, and different labels are given to the transistors for easy identification.

[0057] As shown in the figure, the first switch unit 11 includes a first transistor Q1 and a second transistor Q2, the second end of the first transistor Q1 is connected with the first input end a1, the first end of the first transistor Q1 is connected with the second end of the second transistor Q2 and the first end of the first output branch 14, the first end of the second transistor Q2 is connected with the second input end a2, and the control end of the first transistor Q1 and the control end of the second transistor Q2 are used to receive a set of first control signals PWM1, PWM2, which are used to control the first transistor Q1 to be turned on and the second transistor Q2 to be turned off or control the second transistor Q2 to be turned on and the first transistor Q1 to be turned off. Figure 1 The first switch unit 12 includes a first transistor Q3 and a second transistor Q4, the second end of the first transistor Q3 is connected with the first input end a1, the first end of the first transistor Q3 is connected with the second end of the second transistor Q4 and the first end of the first output branch 15, the first end of the second transistor Q4 is connected with the second input end a2, and the control end of the first transistor Q3 and the control end of the second transistor Q4 are used to receive a set of first control signals PWM3, PWM4, which are used to control the first transistor Q3 to be turned on and the second transistor Q4 to be turned off or control the second transistor Q4 to be turned on and the first transistor Q3 to be turned off.

[0058] The first switch unit 12 includes a first transistor Q3 and a second transistor Q4, the second end of the first transistor Q3 is connected with the first input end a1, the first end of the first transistor Q3 is connected with the second end of the second transistor Q4 and the first end of the first output branch 15, the first end of the second transistor Q4 is connected with the second input end a2, and the control end of the first transistor Q3 and the control end of the second transistor Q4 are used to receive a set of first control signals PWM3, PWM4, which are used to control the first transistor Q3 to be turned on and the second transistor Q4 to be turned off or control the second transistor Q4 to be turned on and the first transistor Q3 to be turned off.

[0059] The first switch unit 13 comprises a first transistor Q5 and a second transistor Q6, the second end of the first transistor Q5 is connected with the first input end a1, the first end of the first transistor Q5 is connected with the second end of the second transistor Q6 and the first end of the first output branch 16, the first end of the second transistor Q6 is connected with the second input end a2, the control end of the first transistor Q5 and the control end of the second transistor Q6 are used for receiving a group of first control signals PWM5, PWM6, the group of first control signals PWM5, PWM6 are used for controlling the first transistor Q5 to be turned on and the second transistor Q6 to be turned off or controlling the second transistor Q6 to be turned on and the first transistor Q5 to be turned off.

[0060] The second switch unit 21 comprises a third transistor Q7 and a fourth transistor Q8, the second end of the third transistor Q7 is connected with the third input end b1, the first end of the third transistor Q7 is connected with the second end of the fourth transistor Q8 and the first end of the second output branch 24, the first end of the fourth transistor Q8 is connected with the fourth input end b2, the control end of the third transistor Q7 and the control end of the fourth transistor Q8 are used for receiving a group of second control signals PWM7, PWM8, the group of second control signals PWM7, PWM8 are used for controlling the third transistor Q7 to be turned on and the fourth transistor Q8 to be turned off or controlling the fourth transistor Q8 to be turned on and the third transistor Q7 to be turned off.

[0061] The second switch unit 22 comprises a third transistor Q9 and a fourth transistor Q10, the second end of the third transistor Q9 is connected with the third input end b1, the first end of the third transistor Q9 is connected with the second end of the fourth transistor Q10 and the first end of the second output branch 25, the first end of the fourth transistor Q10 is connected with the fourth input end b2, the control end of the third transistor Q9 and the control end of the fourth transistor Q10 are used for receiving a group of second control signals PWM9, PWM10, the group of second control signals PWM9, PWM10 are used for controlling the third transistor Q9 to be turned on and the fourth transistor Q10 to be turned off or controlling the fourth transistor Q10 to be turned on and the third transistor Q9 to be turned off.

[0062] The second switch unit 23 comprises a third transistor Q11 and a fourth transistor Q12, the second end of the third transistor Q11 is connected with the third input end b1, the first end of the third transistor Q11 is connected with the second end of the fourth transistor Q12 and the first end of the second output branch 26, the first end of the fourth transistor Q12 is connected with the fourth input end b2, the control end of the third transistor Q11 and the control end of the fourth transistor Q12 are used for receiving a group of second control signals PWM11, PWM12, the group of second control signals PWM11, PWM12 are used for controlling the third transistor Q11 to be turned on and the fourth transistor Q12 to be turned off or controlling the fourth transistor Q12 to be turned on and the third transistor Q11 to be turned off.

[0063] The first transistors Q1, Q3, Q5, the second transistors Q2, Q4, Q6, the third transistors Q7, Q9, Q11, and the fourth transistors Q8, Q10, Q12 are all N-channel MOSFETs. In this case, the first terminal of each transistor is the source, the second terminal is the drain, and the control terminal is the gate. In other embodiments, the first transistors Q1, Q3, Q5, the second transistors Q2, Q4, Q6, the third transistors Q7, Q9, Q11, and the fourth transistors Q8, Q10, Q12 are all insulated-gate bipolar transistors. In this case, the first terminal of each transistor is the emitter, the second terminal is the collector, and the control terminal is the gate. Alternatively, each transistor can also be a P-channel MOSFET.

[0064] In one embodiment, the first control signals PWM1 and PWM2 are a set of inverted signals with dead time, the first control signals PWM3 and PWM4 are a set of inverted signals with dead time, the first control signals PWM5 and PWM6 are a set of inverted signals with dead time, the second control signals PWM7 and PWM8 are a set of inverted signals with dead time, the second control signals PWM9 and PWM10 are also a set of inverted signals with dead time, and the second control signals PWM11 and PWM12 are also a set of inverted signals with dead time.

[0065] Each first output branch and second output branch includes an inductor, which are labeled differently for easy distinction.

[0066] like Figure 1 As shown, the first output branch 14 includes a first inductor L11, the first end of the first inductor L11 being the first end of the first output branch 14, and the second end of the first inductor L11 being the second end of the first output branch 14. The first end of the first inductor L11 is connected to the first end of the first transistor Q1 and the second end of the second transistor Q2.

[0067] The first output branch 15 includes a first inductor L12, the first terminal of the first inductor L12 being the first terminal of the first output branch 15, and the second terminal of the first inductor L12 being the second terminal of the first output branch 15. The first terminal of the first inductor L12 is connected to the first terminal of the first transistor Q3 and the second terminal of the second transistor Q4.

[0068] The first output branch 16 includes a first inductor L13, the first terminal of the first inductor L13 being the first terminal of the first output branch 16, and the second terminal of the first inductor L13 being the second terminal of the first output branch 16. The first terminal of the first inductor L13 is connected to the first terminal of the first transistor Q5 and the second terminal of the second transistor Q6.

[0069] The second end of the first inductor L11, the second end of the first inductor L12 and the second end of the first inductor L13 are connected to form a first output end O1.

[0070] The second output branch 24 comprises a second inductor L21, the first end of the second inductor L21 is the first end of the second output branch 24, and the second end of the second inductor L21 is the second end of the second output branch 24. The first end of the second inductor L21 is connected to the first end of the third transistor Q7 and the second end of the fourth transistor Q8.

[0071] The second output branch 25 comprises a second inductor L22, the first end of the second inductor L22 is the first end of the second output branch 25, and the second end of the second inductor L22 is the second end of the second output branch 25. The first end of the second inductor L22 is connected to the first end of the third transistor Q9 and the second end of the fourth transistor Q10.

[0072] The second output branch 26 comprises a second inductor L23, the first end of the second inductor L23 is the first end of the second output branch 26, and the second end of the second inductor L23 is the second end of the second output branch 26. The first end of the second inductor L23 is connected to the first end of the third transistor Q11 and the second end of the fourth transistor Q12.

[0073] The second end of the second inductor L21, the second end of the second inductor L22 and the second end of the second inductor L23 are connected to form a second output end O2.

[0074] The first power unit 10 further comprises a first capacitor C1 and a second capacitor C2, the first end of the first capacitor C1 is connected to the first input end a1, the second end of the first capacitor C1 is connected to the second input end a2, the first end of the second capacitor C2 is connected to the first output end O1, and the second end of the second capacitor C2 is connected to the second input end a2. In other embodiments, the first capacitor C1 or the second capacitor C2 can not be provided.

[0075] The second power unit 20 further comprises a third capacitor C3 and a fourth capacitor C4, the first end of the third capacitor C3 is connected to the third input end b1, the second end of the third capacitor C3 is connected to the fourth input end b2, the first end of the fourth capacitor C4 is connected to the third input end b1, and the second end of the fourth capacitor C4 is connected to the second output end O2. In other embodiments, the third capacitor C3 or the fourth capacitor C4 can not be provided.

[0076] As Figure 1As shown, the detection unit 30 is composed of 7 Hall elements or shunts, and the current detection by the 7 Hall elements obtains the first currents I11, I12, I13 on the first output branches 14, 15, 16, the second currents I21, I22, I23 on the second output branches 24, 25, 26, and the total current Isum at the first output end O1.

[0077] Since there are three first currents and three second currents, and each of the first currents and the second currents needs to be processed with the total current, the second adjusting module and the third adjusting module are also provided with three, and the corresponding first output module and the second output module are also provided with three.

[0078] Specifically, as shown, Figure 2 The first adjusting module 41 includes a first PI regulator PI_1 and a first saturation limiter Saturation1, the first input end of the first PI regulator PI_1 is used for receiving the total current Isum, the second input end of the first PI regulator PI_1 is used for receiving the total preset current Iset, the input end of the first saturation limiter Saturation1 is connected with the output end of the first PI regulator PI_1, the output end of the first saturation limiter Saturation1 is used for outputting the first adjusting signal Iout_1, and the first saturation limiter Saturation1 is used for limiting the output signal of the first PI regulator PI_1 in a first limiting range.

[0079] The second adjusting module 421 includes a first multiplier X11, a second PI regulator PI_21 and a second saturation limiter Saturation21, the first multiplier X11 is used for obtaining a first preset current Is11 based on the total preset current Iset, the first input end of the second PI regulator PI_21 is used for receiving the first preset current Is11, the second input end of the second PI regulator PI_21 is used for receiving the first current I11, the input end of the second saturation limiter Saturation21 is connected with the output end of the second PI regulator PI_21, the output end of the second saturation limiter Saturation21 is used for outputting the second adjusting signal Iout_21, and the second saturation limiter Saturation21 is used for limiting the output signal of the second PI regulator PI_21 in a second limiting range to obtain the second adjusting signal Iout_21.

[0080] The first output module 424 comprises a first adder A11, a third saturation limiter Saturation31 and a first processing module NV11, the first input terminal of the first adder A11 is connected with the first adjusting module 41 to receive the first adjusting signal Iout_1, the second input terminal of the first adder A11 is connected with the second adjusting module 421 to receive the second adjusting signal Iout_21, the third saturation limiter Saturation31 is connected with the output terminal of the first adder A11 to limit the signal generated by the sum of the first adjusting signal Iout_1 and the second adjusting signal Iout_21 within the first limiting range, and the first processing module NV11 is connected with the third saturation limiter Saturation31 to process the signal output by the third saturation limiter Saturation31 to generate a set of first control signals PWM1, PWM2.

[0081] The second adjusting module 422 comprises a first multiplier X12, a second PI regulator PI_22 and a second saturation limiter Saturation22, the first multiplier X12 is used to obtain a first preset current Is12 based on the total preset current Iset, the first input terminal of the second PI regulator PI_22 is used to receive the first preset current Is12, the second input terminal of the second PI regulator PI_22 is used to receive the first current I12, the input terminal of the second saturation limiter Saturation22 is connected with the output terminal of the second PI regulator PI_22, the output terminal of the second saturation limiter Saturation22 is used to output the second adjusting signal Iout_22, and the second saturation limiter Saturation22 is used to limit the output signal of the second PI regulator PI_22 within the second limiting range to obtain the second adjusting signal Iout_22.

[0082] The first output module 424 comprises a first adder A11, a third saturation limiter Saturation31 and a first processing module NV11, the first input terminal of the first adder A11 is connected with the first adjusting module 41 to receive the first adjusting signal Iout_1, the second input terminal of the first adder A11 is connected with the second adjusting module 421 to receive the second adjusting signal Iout_21, the third saturation limiter Saturation31 is connected with the output terminal of the first adder A11 to limit the signal generated by the sum of the first adjusting signal Iout_1 and the second adjusting signal Iout_21 within the first limiting range, and the first processing module NV11 is connected with the third saturation limiter Saturation31 to process the signal output by the third saturation limiter Saturation31 to generate a set of first control signals PWM1, PWM2.

[0083] The second adjustment module 423 includes a first multiplier X13, a second PI regulator PI_23, and a second saturation limiter Saturation23. The first multiplier X13 is used to obtain a first preset current Is13 based on the total preset current Iset. The first input terminal of the second PI regulator PI_23 is used to receive the first preset current Is13, and the second input terminal of the second PI regulator PI_23 is used to receive the first current I13. The input terminal of the second saturation limiter Saturation23 is connected to the output terminal of the second PI regulator PI_23, and the output terminal of the second saturation limiter Saturation23 is used to output a second adjustment signal Iout_23. The second saturation limiter Saturation23 is used to limit the output signal of the second PI regulator PI_23 to a second limiting range to obtain the second adjustment signal Iout_23.

[0084] The first output module 426 includes a first adder A13, a third saturation limiter Saturation33, and a first processing module NV13. The first input terminal of the first adder A13 is connected to the first adjustment module 41 to receive the first adjustment signal Iout_1. The second input terminal of the first adder A13 is connected to the second adjustment module 423 to receive the second adjustment signal Iout_23. The third saturation limiter Saturation33 is connected to the output terminal of the first adder A13 to limit the signal generated by the sum of the first adjustment signal Iout_1 and the second adjustment signal Iout_23 within a first limiting range. The first processing module NV13 is connected to the third saturation limiter Saturation33 to process the signal output by the third saturation limiter Saturation33 to generate a set of first control signals PWM5 and PWM6.

[0085] like Figure 3 As shown, the third adjustment module 431 includes a second multiplier X21, an inverter N1, a third PI regulator PI_31, and a fourth saturation limiter Saturation41. The second multiplier X21 is used to obtain a second preset current Is21 based on the total preset current Iset. The first input terminal of the third PI regulator PI_31 is used to receive the second preset current Is21. The inverter N1 is used to invert the second current I21. The second input terminal of the third PI regulator PI_31 is used to receive the inverted second current I21. The input terminal of the fourth saturation limiter Saturation41 is connected to the output terminal of the third PI regulator PI_31. The output terminal of the fourth saturation limiter Saturation41 is used to output a third adjustment signal Iout_31. The fourth saturation limiter Saturation41 is used to limit the output signal of the third PI regulator PI_31 to a second limiting range to obtain the third adjustment signal Iout_31.

[0086] The second output module 434 comprises a second adder A21, a fifth saturation limiter Saturation51 and a second processing module NV21, the first input terminal of the second adder A21 is connected with the first adjusting module 41 to receive the first adjusting signal Iout_1, the second input terminal of the second adder A21 is connected with the third adjusting module 431 to receive the third adjusting signal Iout_31, the fifth saturation limiter Saturation51 is connected with the output terminal of the second adder A21 to limit the signal generated by the sum of the first adjusting signal Iout_1 and the third adjusting signal Iout_31 within the first limiting range, and the second processing module NV21 is connected with the fifth saturation limiter Saturation51 to process the signal output by the fifth saturation limiter Saturation51 to generate a set of second control signals PWM7 and PWM8.

[0087] The third adjusting module 432 comprises a second multiplier X22, an inverter N2, a third PI adjusting module PI_32 and a fourth saturation limiter Saturation42, the second multiplier X22 is used to obtain a second preset current Is22 based on the total preset current Iset, the first input terminal of the third PI adjusting module PI_32 is used to receive the second preset current Is22, the inverter N2 is used to take the complement of the second current I22, the second input terminal of the third PI adjusting module PI_32 is used to receive the complemented second current I22, the input terminal of the fourth saturation limiter Saturation42 is connected with the output terminal of the third PI adjusting module PI_32, the output terminal of the fourth saturation limiter Saturation42 is used to output the third adjusting signal Iout_32, and the fourth saturation limiter Saturation42 is used to limit the output signal of the third PI adjusting module PI_32 within the second limiting range to obtain the third adjusting signal Iout_32.

[0088] The second output module 435 comprises a second adder A22, a fifth saturation limiter Saturation52 and a second processing module NV22, the first input terminal of the second adder A22 is connected with the first adjusting module 41 to receive the first adjusting signal Iout_1, the second input terminal of the second adder A21 is connected with the third adjusting module 432 to receive the third adjusting signal Iout_32, the fifth saturation limiter Saturation52 is connected with the output terminal of the second adder A22 to limit the signal generated by the sum of the first adjusting signal Iout_1 and the third adjusting signal Iout_32 within the first limiting range, and the second processing module NV22 is connected with the fifth saturation limiter Saturation52 to process the signal output by the fifth saturation limiter Saturation52 to generate a set of second control signals PWM9 and PWM10.

[0089] The third adjusting module 433 comprises a second multiplier X23, an inverter N3, a third PI regulator PI_33 and a fourth saturation limiter Saturation43, the second multiplier X23 is configured to obtain a second preset current Is23 based on the total preset current Iset, a first input terminal of the third PI regulator PI_33 is configured to receive the second preset current Is23, the inverter N3 is configured to take the complement of the second current I23, a second input terminal of the third PI regulator PI_33 is configured to receive the complemented second current I23, an input terminal of the fourth saturation limiter Saturation43 is connected with an output terminal of the third PI regulator PI_33, an output terminal of the fourth saturation limiter Saturation43 is configured to output a third adjusting signal Iout_33, and the fourth saturation limiter Saturation43 is configured to limit the output signal of the third PI regulator PI_33 in a second limiting range to obtain the third adjusting signal Iout_33.

[0090] The second output module 436 comprises a second adder A23, a fifth saturation limiter Saturation53 and a second processing module NV23, a first input terminal of the second adder A23 is connected with the first adjusting module 41 to receive the first adjusting signal Iout_1, a second input terminal of the second adder A23 is connected with the third adjusting module 433 to receive the third adjusting signal Iout_33, the fifth saturation limiter Saturation53 is connected with an output terminal of the second adder A23 to limit the signal generated by the sum of the first adjusting signal Iout_1 and the third adjusting signal Iout_33 in a first limiting range, and the second processing module NV23 is connected with the fifth saturation limiter Saturation53 to process the signal output by the fifth saturation limiter Saturation53 to generate a set of second control signals PWM11, PWM12.

[0091] The application also discloses a current sharing control method based on the current sharing control circuit as described above. Figure 1 、 Figure 2 and Figure 3 The current sharing control method comprises the following steps.

[0092] The detection unit 30 detects and obtains the first current on each first output branch, the second current on each second output branch and the total current Isum on the first output end O1 or the second output end O2.

[0093] The control unit generates the first adjusting signal Iout_1 in the first limiting range based on the deviation between the total current Isum and the total preset current Iset.

[0094] The control unit generates a second adjustment signal within a second clipping range based on a deviation between each first current and a corresponding first preset current, and generates a set of first control signals based on the first adjustment signal Iout_1 and each second adjustment signal, through which the action of each first switch unit is controlled.

[0095] The control unit generates a third adjustment signal within a second clipping range based on a deviation between each second current and a corresponding second preset current, and generates a set of second control signals based on the first adjustment signal Iout_1 and each third adjustment signal, through which the action of each second switch unit is controlled.

[0096] Further, the current sharing control method comprises: processing the total current Isum and the total preset current Iset by a first PI regulator PI_1 to generate a corresponding first control quantity, and limiting the first control quantity within a first clipping range by a first saturation clipper Saturation1 to output a first adjustment signal Iout_1.

[0097] The first preset currents Is11, Is12, Is13 are obtained based on the total preset current Iset by first multipliers X11, X12, X13, respectively, the first preset currents Is11, Is12, Is13 and the first currents I11, I12, I13 are processed by second PI regulators PI_21, PI_22, PI_23 to generate corresponding second control quantities, respectively, and the second control quantities are limited within a second clipping range by second saturation clippers Saturation21, Saturation22, Saturation23 to output second adjustment signals Iout_21, Iout_22, Iout_23.

[0098] The first adjustment signal Iout_1 and the second adjustment signals Iout_21, Iout_22, Iout_23 are summed by first adders A11, A12, A13, respectively, the signal generated by the sum of the first adjustment signal Iout_1 and the second adjustment signals Iout_21, Iout_22, Iout_23 is limited within a first clipping range by third saturation clippers Saturation31, Saturation32, Saturation33, respectively, and the signals output by the third saturation clippers Saturation31, Saturation32, Saturation33 are processed by first processing modules NV11, NV12, NV13 to generate a set of first control signals PWM1 and PWM2, PWM3 and PWM4, PWM5 and PWM6.

[0099] The second preset current Is21, Is22, Is23 is obtained based on the total preset current Iset through the second multiplier X21, X22, X23, the second preset current Is21, Is22, Is23 and the second current I21, I22, I23 are processed through the third PI regulator PI_31 to generate a corresponding third control quantity, and the third control quantity is limited in the second limiting range through the fourth saturation limiter Saturation41, Saturation42, Saturation43 to output a corresponding third regulating signal Iout_31, Iout_32, Iout_33.

[0100] The first regulating signal Iout_1 and the third regulating signal Iout_31, Iout_32, Iout_33 are summed through the second adder A21, A22, A23, respectively, the signal generated by the sum of the first regulating signal Iout_1 and the third regulating signal Iout_31, Iout_32, Iout_33 is limited in the first limiting range through the fifth saturation limiter Saturation51, Saturation52, Saturation53, and the signal output by the fifth saturation limiter Saturation51, Saturation52, Saturation53 is processed through the second processing module NV21, NV22, NV23 to generate each group of second control signals PWM7 and PWM8, PWM9 and PWM10, PWM11 and PWM12.

[0101] In combination with Figure 1 , Figure 2 and Figure 3 , the current control circuit topology in the utility model is that two groups of independent AC-DC power modules are connected at the input end, and two groups of power units (the first power unit 10 and the second power unit 20) are further connected, the power unit is in the form of DC-DC, the inputs of the two groups of power units are connected in series (namely, the input negative end of the first power unit 10 is connected with the input positive end of the second power unit 20 of the second group), and the output ends of the two groups of power units are connected with the battery unit BATTERY to charge and discharge the battery unit BATTERY.

[0102] Each power unit in each group can be composed of multiple switching units and output branches, each switching unit is composed of a half-bridge composed of two IGBTs (Insulated Gate Bipolar Transistor) or MOSFETs (Insulated Gate Field Effect Transistor) above and below, and each output branch is composed of a filter inductor connected to the midpoint of the half-bridge. The output current (i.e. the current on the output branch) of each half-bridge switching unit is sampled by a Hall, and the current signals I1-I6 output by each half-bridge switching unit are obtained. The total current Isum obtained after the output of three half-bridge switching units is parallel and then filtered by the second capacitor C2 and the fourth capacitor C4 is obtained. The total current Isum is also sampled by the Hall, and the voltage signal on the battery unit BATTERY is also sampled.

[0103] The control block diagram of the circuit constant current charging and discharging is shown in Figure 2 and Figure 3 Iset is the set total preset current, the total preset current Iset and the sampled total current Isum pass through the first PI regulator PI_1 to output the first pre-regulation amount I_preout1, and then pass through the first saturation limiter Saturation1 to output the first regulation signal Iout_1, wherein the first limiting range of the first saturation limiter Saturation1 is 0.02-0.98 (the dead time ratio is 0.02, and the first limiting range of all in an embodiment is 0.02-0.98).

[0104] In an embodiment, since each group of power units is composed of three output branches, each first preset current is preset to 1 / 3*Iset, i.e. the total preset current Iset is evenly divided into three parts corresponding to the three first preset currents. The first preset current Is11 and the first current I11 (actual current) of the first switching unit 11 pass through the second PI regulator PI_21 to output the second pre-regulation amount I_preout21, and then pass through the second saturation limiter Saturation21 to output the second regulation signal I_out21, wherein the second limiting range of the second saturation limiter Saturation21 is -0.01-0.01 (the second limiting range of all in an embodiment is -0.01-0.01), the second regulation signal I_out21 and the first regulation signal Iout_1 are added and then limited by the third saturation limiter Saturation31, and finally a group of first control signals PWM1, PWM2 are output by the first processing module NV11. The first limiting range of the third saturation limiter Saturation31 is 0.02-0.98 (the dead time ratio is 0.02).

[0105] Since the first saturation limiter Saturation1 has a larger first limiting range and the second saturation limiter Saturation21 has a smaller second limiting range, it is equivalent to realize the duty cycle coarse adjustment through the first adjustment signal Iout_1 and the duty cycle fine adjustment through the second adjustment signal I_out21, so as to obtain a set of first control signals PWM1, PWM2 with stable duty cycle. Similarly, the first output modules 424, 425, 426 and the second output modules 434, 435, 436 also output the first control signals PWM3 and PWM4 with stable duty cycle, the first control signals PWM5 and PWM6 with stable duty cycle, the second control signals PWM7 and PWM8 with stable duty cycle, the second control signals PWM9 and PWM10 with stable duty cycle, and the second control signals PWM11 and PWM12 with stable duty cycle, respectively, so as to realize the constant current charging and discharging.

[0106] Due to the range limitation of the second saturation limiters Saturation21, Saturation22, Saturation23 and the fourth saturation limiters Saturation41, Saturation42, Saturation43, the final difference between the first control signals PWM1, PWM3, PWM5 and the second control signals PWM8, PWM10, PWM12 is only 2%, that is, the voltage difference between the output voltage of the first power unit 10 and the output voltage of the second power unit 20 is only 2% of the input bus voltage. Since the output currents of the first power unit 10 and the second power unit 20 are the same, the output power of the first power unit 10 and the second power unit 20 only differs by 2% at most.

[0107] In an embodiment, when charging the battery unit BATTERY, the waveforms of the first control signals PWM1, PWM3, PWM5 of the first transistors Q1, Q3, Q5, the first control signals PWM2, PWM4, PWM6 of the second transistors Q2, Q4, Q6, the second control signals PWM7, PWM9, PWM11 of the third transistors Q7, Q9, Q11, the second control signals PWM8, PWM10, PWM12 of the fourth transistors Q8, Q10, Q12, and the first currents I11, I12, I13 and the second currents I21, I22, I23 are as follows: Figure 4 and Figure 5As shown, the duty cycle of the first control signal PWM1, PWM3, PWM5 corresponds to the on time of the first transistor Q1, Q3, Q5, for example, if the duty cycle of the first control signal PWM1, PWM3, PWM5 is 0.8, then the on time of the first transistor Q1, Q3, Q5 is 80%, and the duty cycle of the corresponding first control signal PWM2, PWM4, PWM6 is 0.2, and the on time of the second transistor Q2, Q4, Q6 is 20% (not including dead time); the duty cycle of the second control signal PWM8, PWM10, PWM12 corresponds to the on time of the fourth transistor Q8, Q10, Q12, for example, if the duty cycle of the second control signal PWM8, PWM10, PWM12 is 0.8, then the on time of the fourth transistor Q8, Q10, Q12 is 80%, and the duty cycle of the second control signal PWM7, PWM9, PWM11 is 0.2, and the on time of the third transistor Q7, Q9, Q11 is 20%.

[0108] When charging the battery unit BATTERY, when the first transistor Q1 is turned on, the current on the first inductor L11 rises in the forward direction (the current direction from left to right is positive), when the first transistor Q1 is turned off, the current on the first inductor L11 falls in the forward direction, and the first transistor Q3 and the first transistor Q5 are the same. When the fourth transistor Q8 is turned on, the current on the second inductor L21 rises in the reverse direction (the current direction from left to right is positive), and when the fourth transistor Q8 is turned off, the current on the second inductor L21 falls in the reverse direction, and the fourth transistor Q10, Q12 is the same.

[0109] In an embodiment, as shown in Figure 6 and Figure 7 When charging the battery unit BATTERY, current sharing is performed, and the total preset current Iset is set to 300A, before 0.15s, the duty cycle D11 of the first control signal PWM1, the duty cycle D12 of the first control signal PWM3, and the duty cycle D13 of the first control signal PWM5 have the same value, but due to the fact that the parameters of the components in the circuit are not completely consistent, the currents on the first inductors L11, L12, L13 have a large deviation, and long-term operation in this way will cause uneven heating of the three groups of transistors Q1-Q6 and the first inductors L11, L12, L13, affecting the temperature reliability of the equipment.

[0110] If the first current I11 on the first current I11 is less than 1 / 3*Iset (i.e. 100A), that is, the reference current in the second PI regulator PI_21 is greater than the actual first current I11, and after adjustment and calculation by the second PI regulator PI_21, the second adjustment signal Iout_21 is positive (for example Figure 7), the second regulating signal Iout_21 and the first regulating signal Iout_1 are added, and finally the duty cycle D11 of the first control signal PWM1 is increased, the opening time of the first transistor Q1 is increased, and the first current I11 flowing through the first inductor L11 is continuously increased, and finally reaches the set 1 / 3*Iset.

[0111] If the first current I12 on the first inductor L12 is greater than 1 / 3*Iset, at this time the reference current in the second PI regulator PI_22 is less than the actual first current I12, and after the calculation of the second PI regulator PI_22, the second regulating signal Iout_22 is output as negative (such as Figure 7 ), the second regulating signal Iout_22 and the first regulating signal Iout_1 are added, and finally the duty cycle D12 of the first control signal PWM3 is reduced, the opening time of the first transistor Q3 is reduced, and the first current I12 flowing through the first inductor L12 is continuously reduced, and finally reaches the set 1 / 3*Iset.

[0112] If the first current I13 on the first inductor L13 is substantially the same as 1 / 3*Iset, at this time the reference current in the second PI regulator PI_23 is equal to the actual first current I13, and after the calculation of the second PI regulator PI_23, the second regulating signal Iout_23 is output close to 0 (such as Figure 8 ), the second regulating signal Iout_23 and the first regulating signal Iout_1 are added, and finally the duty cycle D13 of the first control signal PWM5 is substantially maintained unchanged, and finally reaches the set 1 / 3*Iset. Finally, the first currents I11, I12, I13 on the first inductors L11, L12, L13 tend to be balanced.

[0113] The second currents I21, I22, I23 on the second inductors L21, L22, L23 are balanced in the same way. It should be noted that the second currents I21, I22, I23 on the second inductors L21, L22, L23 need to be inverted after sampling.

[0114] In an embodiment, when the battery unit BATTERY is discharged, the first control signals PWM1, PWM3, PWM5 of the first transistors Q1, Q3, Q5 and the first control signals PWM2, PWM4, PWM6 of the second transistors Q2, Q4, Q6, the second control signals PWM7, PWM9, PWM11 of the third transistors Q7, Q9, Q11 and the second control signals PWM8, PWM10, PWM12 of the fourth transistors Q8, Q10, Q12, and the waveforms of the first currents I11, I12, I13 and the second currents I21, I22, I23 are as follows Figure 9 and Figure 10As shown, the duty cycle of the first control signal PWM1, PWM3, PWM5 corresponds to the on time of the first transistor Q1, Q3, Q5, for example, if the duty cycle of the first control signal PWM1, PWM3, PWM5 is 0.8, then the on time of the first transistor Q1, Q3, Q5 is 80%, and the duty cycle of the corresponding first control signal PWM2, PWM4, PWM6 is 0.2, and the on time of the second transistor Q2, Q4, Q6 is 20% (not including dead time); the duty cycle of the second control signal PWM8, PWM10, PWM12 corresponds to the on time of the fourth transistor Q8, Q10, Q12, for example, if the duty cycle of the second control signal PWM8, PWM10, PWM12 is 0.8, then the on time of the fourth transistor Q8, Q10, Q12 is 80%, and the duty cycle of the second control signal PWM7, PWM9, PWM11 is 0.2, and the on time of the third transistor Q7, Q9, Q11 is 20%.

[0115] When the battery unit BATTERY discharges, when the first transistor Q1 is turned on, the first current I11 on the first inductor L11 reversely decreases (the current direction from left to right is positive), when the first transistor Q1 is turned off, the first current I11 on the first inductor L11 reversely increases, and the first transistor Q3, the first transistor Q5 is the same. When the fourth transistor Q8 is turned on, the second current I21 on the second inductor L21 decreases in the positive direction (the current direction from left to right is positive), and when the fourth transistor Q8 is turned off, the second current I21 on the second inductor L21 increases in the positive direction, and the fourth transistor Q10, the fourth transistor Q12 is the same.

[0116] In an embodiment, as shown in Figure 11 and Figure 11 As shown, when the battery unit BATTERY discharges, the current sharing is carried out, and the total preset current Iset is set to -300A. Before 0.15s, the duty cycle D11 of the first control signal PWM1, the duty cycle D12 of the first control signal PWM3, and the duty cycle D13 of the first control signal PWM5 have the same value, but due to the fact that the parameters of the components in the circuit are not completely consistent, the currents on the first inductors L11, L12, L13 have a large deviation, and long-term operation in this way will cause uneven heating of the three groups of transistors Q1-Q6 and the first inductors L11, L12, L13, affecting the temperature reliability of the equipment.

[0117] If the first current I11 on the first current I11 is greater than 1 / 3*Iset (i.e. -100A), that is, the reference current in the second PI regulator PI_21 is less than the actual first current I11, and after the adjustment and calculation of the second PI regulator PI_21, the second adjustment signal Iout_21 is output as negative (for example Figure 11), the second regulating signal Iout_21 is added to the first regulating signal Iout_1, and finally the duty cycle D11 of the first control signal PWM1 is reduced, the on time of the first transistor Q1 is reduced, and the current flowing through the first inductor L11 is continuously reduced (negatively increased), and finally reaches the set 1 / 3*Iset.

[0118] If the first current I12 on the first inductor L12 is less than 1 / 3*Iset, the reference current in the second PI regulator PI_22 is greater than the actual first current I12 at this time, and after adjustment and calculation by the second PI regulator PI_22, the second regulating signal Iout_22 is output as positive (such as Figure 11 ), the second regulating signal Iout_22 is added to the first regulating signal Iout_1, and finally the duty cycle D12 of the first control signal PWM3 is increased, the on time of the first transistor Q3 is increased, and the first current I12 flowing through the first inductor L12 is continuously increased (negatively reduced), and finally reaches the set 1 / 3*Iset.

[0119] If the first current I13 on the first inductor L13 is less than 1 / 3*Iset, the reference current in the second PI regulator PI_23 is greater than the actual first current I13 at this time, and after adjustment and calculation by the second PI regulator PI_23, the second regulating signal Iout_23 is output as positive (such as ​ ), the second regulating signal Iout_23 is added to the first regulating signal Iout_1, and finally the duty cycle D13 of the first control signal PWM5 is increased, the on time of the first transistor Q5 is increased, and the first current I13 flowing through the first inductor L13 is continuously increased (negatively reduced), and finally reaches the set 1 / 3*Iset.

[0120] Finally, the first currents I11, I12, I13 on the first inductors L11, L12, L13 tend to be balanced. The second currents I21, I22, I23 on the second inductors L21, L22, L23 are balanced for the same reason. It should be noted that the second currents I21, I22, I23 on the second inductors L21, L22, L23 need to be inverted after sampling.

[0121] It is apparent for a person skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but that it can be implemented in other concrete forms without departing from the spirit or the essential characteristics of the present application. Therefore, the embodiments should be considered as exemplary and non-limiting, the scope of the present application being defined by the claims appended hereto rather than by the above description, and all the changes which fall within the meaning and the scope of the equivalent elements of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0122] Furthermore, it should be understood that although the present specification describes exemplary embodiments, not every embodiment contains only one independent technical solution, and the present specification is described in this way only for the sake of clarity, and a person skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that a person skilled in the art can understand.

Claims

1. A current sharing control circuit, characterized in that, include: The first power unit includes multiple first switching units and multiple first output branches. Each first switching unit is connected between a first input terminal and a second input terminal. The first terminal of each first output branch is connected to the corresponding first switching unit. The second terminals of each first output branch are connected to form a first output terminal. Each first switching unit controls the connection between the first input terminal and the first output branch or controls the connection between the second input terminal and the first output branch based on a set of first control signals. The second power unit includes multiple second switching units and multiple second output branches. Each second switching unit is connected between a third input terminal and a fourth input terminal. The third input terminal is connected to the second input terminal. The first terminal of each second output branch is connected to the corresponding second switching unit. The second terminals of each second output branch are connected to form a second output terminal. Each second switching unit controls the connection between the third input terminal and the second output branch or controls the connection between the fourth input terminal and the second output branch based on a set of second control signals. The detection unit is used to detect and obtain the first current on each first output branch, the second current on each second output branch, and the total current on the first output terminal or the second output terminal. The control unit is configured to generate a first adjustment signal within a first limit range based on the deviation between the total current and the total preset current, generate a second adjustment signal within a second limit range based on the deviation between each first current and the corresponding first preset current, generate a third adjustment signal within a second limit range based on the deviation between each second current and the corresponding second preset current, and generate a set of first control signals based on the first adjustment signals and each second adjustment signal, and generate a set of second control signals based on the first adjustment signals and each third adjustment signal.

2. The current sharing control circuit according to claim 1, characterized in that, The control unit includes: a first adjustment module, multiple second adjustment modules, multiple third adjustment modules, multiple first output modules, and multiple second output modules; The first adjustment module generates a first adjustment signal within a first limit range based on the deviation between the total current and the total preset current; Each of the second adjustment modules generates a corresponding second adjustment signal within the second limit range based on the deviation between the corresponding first current and the corresponding first preset current. Each of the first output modules generates a corresponding set of first control signals within the first limit range based on the first adjustment signal and the corresponding second adjustment signal. Each of the third adjustment modules generates a corresponding third adjustment signal within a second limiting range based on the deviation between the corresponding second current and the corresponding second preset current. Each of the second output modules generates a corresponding set of second control signals within a first limiting range based on the first adjustment signal and the corresponding third adjustment signal.

3. The current sharing control circuit according to claim 2, characterized in that, The first adjustment module includes a first PI regulator and a first saturation limiter. The first input terminal of the first PI regulator is used to receive the total current, and the second input terminal of the first PI regulator is used to receive the total preset current. The input terminal of the first saturation limiter is connected to the output terminal of the first PI regulator, and the output terminal of the first saturation limiter is used to output a first adjustment signal. The first saturation limiter is used to limit the output signal of the first PI regulator to a first limiting range.

4. The current sharing control circuit according to claim 2, characterized in that, The second adjustment module includes a first multiplier, a second PI regulator, and a second saturation limiter. The first multiplier is used to obtain a first preset current based on a total preset current. The first input terminal of the second PI regulator is used to receive the first preset current, and the second input terminal of the second PI regulator is used to receive the first current. The input terminal of the second saturation limiter is connected to the output terminal of the second PI regulator, and the output terminal of the second saturation limiter is used to output a second adjustment signal. The second saturation limiter is used to limit the output signal of the second PI regulator to a second limiting range; and / or The third adjustment module includes a second multiplier, an inverter, a third PI regulator, and a fourth saturation limiter. The second multiplier is used to obtain a second preset current based on the total preset current. The first input terminal of the third PI regulator is used to receive the second preset current. The inverter is used to invert the second current. The second input terminal of the third PI regulator is used to receive the inverted second current. The input terminal of the fourth saturation limiter is connected to the output terminal of the third PI regulator. The output terminal of the fourth saturation limiter is used to output a third adjustment signal. The fourth saturation limiter is used to limit the output signal of the third PI regulator to a second limiting range.

5. The current sharing control circuit according to claim 2, characterized in that, The first output module includes a first adder, a third saturation limiter, and a first processing module. The first input terminal of the first adder is connected to the first adjustment module to receive a first adjustment signal, and the second input terminal of the first adder is connected to the second adjustment module to receive a second adjustment signal. The third saturation limiter is connected to the output terminal of the first adder to limit the signal generated by the sum of the first adjustment signal and the second adjustment signal within a first limiting range. The first processing module is connected to the third saturation limiter to process the signal output by the third saturation limiter to generate a set of first control signals.

6. The current sharing control circuit according to claim 2, characterized in that, The second output module includes a second adder, a fifth saturation limiter, and a second processing module. The first input terminal of the second adder is connected to the first adjustment module to receive a first adjustment signal, and the second input terminal of the second adder is connected to the third adjustment module to receive a third adjustment signal. The fifth saturation limiter is connected to the output terminal of the second adder to limit the signal generated by the sum of the first adjustment signal and the third adjustment signal within a first limiting range. The second processing module is connected to the fifth saturation limiter to process the signal output by the fifth saturation limiter to generate a set of second control signals.

7. The current sharing control circuit according to claim 1, characterized in that, The first output branch includes a first inductor, the first end of the first inductor is the first end of the first output branch, and the second end of the first inductor is the second end of the first output branch.

8. The current sharing control circuit according to claim 1, characterized in that, The second output branch includes a second inductor, the first end of the second inductor being the first end of the second output branch, and the second end of the second inductor being the second end of the second output branch.

9. The current sharing control circuit according to claim 1, characterized in that, The first switching unit includes a first transistor and a second transistor. The second terminal of the first transistor is connected to the first input terminal. The first terminal of the first transistor is connected to the second terminal of the second transistor and the first terminal of the first output branch. The first terminal of the second transistor is connected to the second input terminal. The control terminal of the first transistor and the control terminal of the second transistor are used to receive a set of first control signals. The set of first control signals are used to control the first transistor to turn on and the second transistor to turn off, or to control the second transistor to turn on and the first transistor to turn off. and / or The second switching unit includes a third transistor and a fourth transistor. The second terminal of the third transistor is connected to the third input terminal. The first terminal of the third transistor is connected to the second terminal of the fourth transistor and the first terminal of the second output branch. The first terminal of the fourth transistor is connected to the fourth input terminal. The control terminals of the third transistor and the fourth transistor are used to receive a set of second control signals. The set of second control signals is used to control the third transistor to turn on and the fourth transistor to turn off, or to control the fourth transistor to turn on and the third transistor to turn off.

10. The current sharing control circuit according to claim 1, characterized in that, The first power unit further includes a first capacitor and / or a second capacitor, wherein a first terminal of the first capacitor is connected to a first input terminal, a second terminal of the first capacitor is connected to a second input terminal, a first terminal of the second capacitor is connected to a first output terminal, and a second terminal of the second capacitor is connected to a second input terminal; and / or The second power unit further includes a third capacitor and / or a fourth capacitor, wherein the first terminal of the third capacitor is connected to the third input terminal, the second terminal of the third capacitor is connected to the fourth input terminal, the first terminal of the fourth capacitor is connected to the third input terminal, and the second terminal of the fourth capacitor is connected to the second output terminal.

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