Circuit board with information identification and electronic equipment

Abstract

The utility model provides a circuit board with information identification and electronic equipment, and belongs to the technical field of electronic equipment. The circuit board comprises a substrate layer, a solder mask layer and a gold plating layer, the solder mask layer is located on the surface of the substrate layer, the solder mask layer is provided with a mark groove exposed out of the substrate layer, and the gold plating layer is located in the mark groove. The shapes of orthographic projections of the mark grooves on the surface of the substrate layer comprise character patterns, digital patterns and two-dimensional code patterns, and the color of the solder mask layer is different from the color of the surface, away from the substrate layer, of the gold plating layer. The wear resistance of the information mark of the circuit board can be improved, and the service life of the circuit board can be prolonged.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of electronic equipment, and in particular, to a circuit board with information identification and electronic equipment. BACKGROUND

[0002] As a carrier for carrying electronic components, a printed circuit board (PCB) is used to realize electrical connection between electronic components and is an important component of electronic equipment. The printed circuit board usually includes a high-density interconnector (HDI) circuit board and an integrated circuit (ICS) board.

[0003] In the related art, a circuit board usually includes a substrate layer and information marks on the surface of the substrate layer. The information marks can include product-related marks such as text, numbers, or two-dimensional code patterns. These information marks are usually printed on the substrate layer in a way of embossing or are attached to the substrate layer as stickers. A technician can track and trace the product through the information marks to realize quality monitoring of the product.

[0004] However, the information marks are prone to wear after long-term use of the circuit board, which reduces the recognition of the information marks and is not conducive to realizing quality monitoring of the product. UTILITY MODEL CONTENT

[0005] The present disclosure provides a circuit board with information identification and electronic equipment, which can improve the wear resistance of the information marks of the circuit board and prolong the service life of the circuit board. The technical solution is as follows:

[0006] The present disclosure provides a circuit board with information identification, which includes a substrate layer, a solder mask layer, and a gold plating layer. The solder mask layer is located on the surface of the substrate layer. The solder mask layer has a mark groove that exposes the substrate layer. The shape of the orthographic projection of the mark groove on the surface of the substrate layer includes at least one of a text pattern, a number pattern, and a two-dimensional code pattern. The gold plating layer is located in the mark groove. The color of the solder mask layer is different from the color of the surface of the gold plating layer away from the substrate layer.

[0007] In an implementation manner of the present disclosure, the gold plating layer includes a Ni layer, a Pd layer, and an Au layer stacked in the mark groove in sequence.

[0008] In another implementation manner of the present disclosure, the thickness of the Ni layer is 5 μm to 9 μm, the thickness of the Pd layer is 0.3 μm to 1 μm, and the thickness of the Au layer is 0.3 μm to 1 μm.

[0009] In another implementation manner of the embodiment of the present disclosure, the thickness of the gold plating layer is less than or equal to the depth of the mark groove.

[0010] In another implementation manner of the embodiment of the present disclosure, the depth of the mark groove is 10 μm to 40 μm.

[0011] In another implementation manner of the embodiment of the present disclosure, the substrate layer comprises an insulating plate and a conductive layer, the conductive layer is located on the plate surface of the insulating plate, and the solder mask layer is located on the surface of the conductive layer away from the insulating plate.

[0012] In another implementation manner of the embodiment of the present disclosure, the thickness of the conductive layer is 15 μm to 25 μm.

[0013] In another implementation manner of the embodiment of the present disclosure, the thickness of the insulating plate is 100 μm to 200 μm.

[0014] In another implementation manner of the embodiment of the present disclosure, the shape of the orthographic projection of the gold plating layer on the surface of the substrate layer comprises at least one of a character pattern, a number pattern and a two-dimensional code pattern.

[0015] The embodiment of the present disclosure provides an electronic device comprising the circuit board as described above.

[0016] The technical scheme provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0017] In the circuit board provided by the embodiment of the present disclosure, the solder mask layer is arranged on the surface of the substrate layer, and the mark groove exposing the substrate layer is arranged on the surface of the solder mask layer. The shape of the mark groove can be a character pattern, a number pattern or a two-dimensional code pattern, which is used to represent product information. In order to avoid damage of the mark groove due to wear after long-term use of the circuit board, the gold plating layer is filled in the mark groove, and the position of the mark groove is protected by the gold plating layer, which can prevent the position from being eroded by chemical substances and improve the service life. In addition, the gold plating layer can also prevent the position of the mark groove from being damaged due to frequent contact or physical wear, thereby improving the wear resistance and corrosion resistance of the position of the mark groove. At the same time, since the circuit board also works in a high-temperature environment due to heat generated by electronic devices, the gold plating layer can not only improve the high-temperature resistance, but also quickly dissipate the heat at the position of the mark groove to other positions through the good heat conduction of the metal, so as to avoid damage of the position of the mark groove due to local high temperature of the circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0019] Figure 1 is a structural schematic diagram of a circuit board provided by an embodiment of the present disclosure;

[0020] Figure 2 is a local level schematic diagram of a circuit board provided by an embodiment of the present disclosure;

[0021] Figure 3 is a preparation state diagram of a circuit board provided by an embodiment of the present disclosure;

[0022] Figure 4 is a preparation state diagram of a circuit board provided by an embodiment of the present disclosure;

[0023] Figure 5 is a preparation state diagram of a circuit board provided by an embodiment of the present disclosure.

[0024] The descriptions of the various marks in the drawings are as follows:

[0025] 10, substrate layer; 11, insulating plate; 12, conductive layer;

[0026] 20, solder resist layer; 21, marking groove;

[0027] 30, gold plating layer; 31, Ni layer; 32, Pd layer; 33, Au layer;

[0028] 40, circuit board; 41, effective area; 42, marking area. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0030] Unless otherwise defined, technical terms or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third", and the like, as used in the description and the claims of this disclosure do not have any specific meaning, and are merely used to distinguish one component from another. Similarly, the terms "one", "another", and the like, do not limit the quantity of the mentioned objects, and mean at least one. The terms "comprise", "comprising", and the like, mean that the elements or objects listed after the terms are encompassed by the "comprising" or "comprises" terms, and do not exclude other elements or objects. The terms "connected", "coupled", and the like, do not limit the manner of connection or coupling to physical or mechanical, but can include electrical connection or coupling, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom", and the like, are merely used to indicate relative positions, and can change when the absolute positions of the described objects change.

[0031] Figure 1 is a structural schematic diagram of a circuit board provided by an embodiment of the present disclosure. As shown in Figure 1 , the circuit board 40 includes an effective area 41 for connecting with electronic devices and a marking area 42 for marking product information.

[0032] The marking area has information markings such as text patterns, number patterns, or two-dimensional code patterns.

[0033] As shown in Figure 1 , the marking area 42 of the circuit board 40 has a two-dimensional code pattern. A technician can query product information and track and trace the product by scanning the two-dimensional code pattern, so as to realize quality monitoring of the product.

[0034] Figure 2 is a partial level schematic diagram of a circuit board provided by an embodiment of the present disclosure. Figure 2 The schematic is a level cross-sectional view corresponding to the marking area 42. As shown in Figure 1 , 2 , the circuit board includes a substrate layer 10, a solder resist layer 20, and a gold plating layer 30. The solder resist layer 20 is located on the surface of the substrate layer 10, the solder resist layer 20 has a marking groove 21 exposing the substrate layer 10, the shape of the normal projection of the marking groove 21 on the surface of the substrate layer 10 includes text patterns, number patterns, and two-dimensional code patterns, and the gold plating layer 30 is located in the marking groove 21.

[0035] The color of the solder resist layer 20 is different from the color of the surface of the gold plating layer 30 away from the substrate layer 10. Such arrangement of different colors can more easily show the corresponding marking information.

[0036] The circuit board provided by the embodiments of the present disclosure is provided with a solder resist layer 20 on the surface of the substrate layer 10, and the surface of the solder resist layer 20 is provided with a mark groove 21 exposing the substrate layer 10. The shape of the mark groove 21 can be a character pattern, a number pattern or a two-dimensional code pattern, which is used to represent product information. In order to avoid the mark groove 21 being damaged due to wear after long-term use of the circuit board, the mark groove 21 is filled with a gold plating layer 30, and the position where the mark groove 21 is located is protected by the gold plating layer 30, which can prevent the position from being eroded by chemicals and improve the service life. In addition, the gold plating layer 30 can also prevent the position where the mark groove 21 is located from being damaged due to frequent contact or physical wear, thereby improving the wear resistance and corrosion resistance of the area where the mark groove 21 is located. At the same time, since the circuit board will also work in a high-temperature environment due to the heat generated by electronic devices, the gold plating layer 30 can not only improve the high-temperature resistance, but also quickly dissipate the heat at the position where the mark groove 21 is located to other positions through the good heat conduction characteristics of the metal, so as to avoid local high temperature at the position where the mark groove 21 of the circuit board is located.

[0037] Optionally, as shown in Figure 2 The substrate layer 10 includes an insulating plate 11 and a conductive layer 12, the conductive layer 12 is located on the surface of the insulating plate 11, the solder resist layer 20 is located on the surface of the conductive layer 12 away from the insulating plate 11, and the mark groove 21 exposes the conductive layer 12.

[0038] Exemplarily, the preparation material of the insulating plate 11 can include glass fiber and epoxy resin. The glass fiber and the epoxy resin can provide mechanical support and insulation function.

[0039] Exemplarily, the conductive layer 12 can be a copper foil. The conductive layer 12 is patterned by an etching process to form a circuit pattern to realize the transmission of current and signal.

[0040] Exemplarily, the preparation material of the solder resist layer 20 includes polymer resin and pigment. The pigment mixed in the polymer resin makes the solder resist layer 20 have color, so as to facilitate the technician to observe whether the solder resist layer 20 covers the area of the substrate layer 10 that needs to be insulated.

[0041] The solder resist layer 20 can be uniformly coated on the surface of the conductive layer 12 by a process such as screen printing, spraying or light drawing to form a layer of solder resist layer 20 with insulation properties. The solder resist layer 20 can protect the copper foil of the circuit board from being oxidized and prevent short circuit.

[0042] Optionally, the depth of the mark groove 21 is 10-40 μm.

[0043] The depth of the marking groove 21 is set in the above range, which can avoid the depth of the marking groove 21 being too shallow to fill enough gold plating layer 30, affecting the protection effect of the gold plating layer 30, and also can avoid the depth of the marking groove 21 being too deep, and too much metal needs to be filled in the marking groove 21, effectively reducing the preparation cost of the gold plating layer 30.

[0044] Exemplarily, the depth of the marking groove 21 is 20 μm.

[0045] Optionally, the thickness of the conductive layer 12 is 15 μm to 25 μm.

[0046] By setting the thickness of the conductive layer 12 in the above range, the thickness of the conductive layer 12 meets the use requirements to ensure the safety of the circuit board current transmission.

[0047] Exemplarily, the thickness of the conductive layer 12 is 20 μm.

[0048] Optionally, the thickness of the insulating plate 11 is 100 μm to 200 μm.

[0049] By setting the thickness of the insulating plate 11 in the above range, the thickness of the insulating plate 11 is thick enough to play a good supporting and insulating role, and improve the safety of the circuit board.

[0050] Exemplarily, the thickness of the insulating plate 11 is 150 μm.

[0051] Optionally, as shown in Figure 2 The gold plating layer 30 includes a Ni layer 31, a Pd layer 32 and an Au layer 33 which are sequentially stacked in the marking groove 21.

[0052] Exemplarily, the Ni layer 31 is formed in the marking groove 21 first, and the adhesion of the Ni layer 31 and the conductive layer 12 is better, which can improve the connection reliability of the gold plating layer 30 and the conductive layer 12, and prevent the gold plating layer 30 from loosening from the marking groove 21.

[0053] As an example, the thickness of the Ni layer 31 is 5 μm to 9 μm. For example, the thickness of the Ni layer 31 can be 8 μm. Setting a thicker Ni layer 31 can improve the connection reliability of the gold plating layer 30 and the conductive layer 12.

[0054] Exemplarily, the Pd layer 32 is formed on the Ni layer 31, and the Pd layer 32 can play a role of protecting the Ni layer 31 to prevent the metal nickel from being easily corroded.

[0055] As an example, the thickness of the Pd layer 32 is 0.3 μm to 1 μm. For example, the thickness of the Pd layer 32 is 0.5 μm. Setting a thinner Pd layer 32 can play a role of covering the Ni layer 31 to meet the purpose of protecting the metal Ni.

[0056] Exemplarily, the Au layer 33 is formed on the Pd layer 32, and the Au layer 33 serves to protect the Ni layer 31 and the Pd layer 32, avoiding easy oxidation of the Ni layer 31 and the Pd layer 32.

[0057] For example, the thickness of the Au layer 33 is 0.3 μm to 1 μm. For example, the thickness of the Au layer 33 is 0.5 μm. The Au layer 33 is arranged to be thin enough to cover the Pd layer 32, and the preparation cost of the gold plating layer 30 is reduced.

[0058] Optionally, as shown in Figure 2 The thickness of the gold plating layer 30 is less than or equal to the depth of the mark groove 21. The thickness of the gold plating layer 30 is controlled to be not greater than the depth of the mark groove 21, so that the gold plating layer 30 does not protrude from the mark groove 21. In this way, the opening area of the mark groove 21 is physically abraded before the gold plating layer 30, and the gold plating layer 30 is physically abraded only when the mark groove 21 is abraded to the same thickness as the gold plating layer 30, which further improves the wear resistance of the position where the mark groove 21 is located.

[0059] Exemplarily, the thickness of the gold plating layer 30 is 1 μm to 30 μm less than the depth of the mark groove 21.

[0060] In the embodiment of the present disclosure, the thickness of the gold plating layer is 5.6 μm to 11 μm.

[0061] When the depth of the mark groove is 10 μm to 11 μm, the thickness of the gold plating layer can be less than or equal to the depth of the mark groove, that is, the gold plating layer can be flush with the opening of the mark groove or not protrude from the mark groove.

[0062] When the depth of the mark groove exceeds 11 μm, the thickness of the gold plating layer is less than the depth of the mark groove. At this time, after the gold plating layer is filled into the mark groove, it does not protrude from the mark groove.

[0063] Optionally, the shape of the orthographic projection of the gold plating layer 30 on the surface of the substrate layer 10 includes a character pattern, a number pattern, and a two-dimensional code pattern.

[0064] Exemplarily, as shown in Figure 2 The shape of the orthographic projection of the gold plating layer 30 on the surface of the substrate layer 10 is a two-dimensional code pattern.

[0065] In the embodiment of the present disclosure, the shape of the orthographic projection of the mark groove 21 on the substrate layer 10 is also a two-dimensional code pattern. In this way, when the gold plating layer 30 is formed, the gold plating layer 30 is deposited in the mark groove 21 by evaporation, which naturally makes the pattern of the gold plating layer 30 consistent with the two-dimensional code pattern, effectively reducing the preparation difficulty of the gold plating layer 30.

[0066] The preparation process of the circuit board provided in the embodiment of the present disclosure is as follows:

[0067] The first step is to prepare substrate layer 10.

[0068] like Figure 3 As shown, the substrate layer 10 includes an insulating plate 11 and a conductive layer 12 stacked on the insulating plate 11.

[0069] For example, the insulating board 11 can be at least one of fiberglass board and epoxy resin board. The depth of the insulating board 11 is 100 μm to 200 μm.

[0070] For example, the conductive layer 12 may be a copper foil. The thickness of the conductive layer 12 is 15 μm to 25 μm.

[0071] The second step is to form a solder resist layer 20 on the conductive layer 12.

[0072] like Figure 4 As shown, the solder resist layer 20 covers the conductive layer 12.

[0073] For example, the solder mask 20 may be a polymer resin layer mixed with pigments, so that the color of the solder mask 20 is different from that of the conductive layer 12.

[0074] The solder resist layer 20 can be uniformly coated on the surface of the conductive layer 12 through processes such as screen printing, spraying or photolithography.

[0075] For example, the thickness of the solder mask layer 20 is 10 μm to 40 μm.

[0076] The third step is to engrave marking grooves 21 on the surface of the solder mask layer 20.

[0077] The orthographic projection of the marking groove 21 onto the substrate layer 10 is a QR code pattern.

[0078] like Figure 5 As shown, a QR code pattern is formed by etching the surface of the solder resist layer 20 with a laser beam to expose the surface of the conductive layer 12.

[0079] The fourth step is to use plasma to clean the marking tank 21.

[0080] The ions and free radicals generated by high-density plasma can react with hydrocarbon contaminants on the surface of the marking tank 21 to be treated, generating volatile gases or tiny particles, thereby achieving the purpose of cleaning the marking tank 21, improving the activity and wettability of the marking tank 21, and removing foreign matter from the surface of the substrate layer 10.

[0081] The fifth step is to vapor deposit a gold plating layer 30 in the marking groove 21.

[0082] like Figure 2As shown, the gold plating layer 30 includes a Ni layer 31, a Pd layer 32 and an Au layer 33 which are sequentially stacked in the mark groove 21.

[0083] Exemplarily, the Ni layer 31 is formed in the mark groove 21 first, and the Ni layer 31 has better adhesion with the conductive layer 12. The thickness of the Ni layer 31 is 5 μm to 9 μm.

[0084] Exemplarily, the Pd layer 32 is formed on the Ni layer 31, and the Pd layer 32 can protect the Ni layer 31. The thickness of the Pd layer 32 is 0.3 μm to 1 μm.

[0085] Exemplarily, the Au layer 33 is formed on the Pd layer 32, and the Au layer 33 can avoid the Ni layer 31 and the Pd layer 32 from being easily oxidized. The thickness of the Au layer 33 is 0.3 μm to 1 μm.

[0086] The electronic device provided by the embodiments of the present disclosure includes the circuit board as described above.

[0087] Exemplarily, the electronic device can be any electronic device including a circuit board, such as a server, a mobile phone, a computer, a television, a game console, an electronic watch, etc.

[0088] The above is not intended to limit the present disclosure in any form, although the present disclosure has been disclosed as above through embodiments, however, is not intended to limit the present disclosure, any person skilled in the art, without departing from the technical solution of the present disclosure, can make some changes or modifications to the above disclosed technical content for equivalent embodiments, as long as it does not deviate from the technical solution of the present disclosure, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present disclosure, still belongs to the scope of the technical solution of the present disclosure.

Claims

1. A circuit board having an information mark, characterized by, The circuit board includes a substrate layer (10), a solder resist layer (20) and a gold plating layer (30), the solder resist layer (20) is located on the surface of the substrate layer (10), the solder resist layer (20) has a mark groove (21) exposing the substrate layer (10), the shape of the orthographic projection of the mark groove (21) on the surface of the substrate layer (10) includes at least one of a character pattern, a number pattern and a two-dimensional code pattern, the gold plating layer (30) is located in the mark groove (21), the color of the solder resist layer (20) is different from the color of the gold plating layer (30) away from the surface of the substrate layer (10).

2. The circuit board of claim 1, wherein The gold plating layer (30) includes a Ni layer (31), a Pd layer (32) and an Au layer (33) which are sequentially stacked in the mark groove (21).

3. The circuit board of claim 2, wherein, The thickness of the Ni layer (31) is 5-9 μm, the thickness of the Pd layer (32) is 0.3-1 μm, and the thickness of the Au layer (33) is 0.3-1 μm.

4. The circuit board according to any one of claims 1 to 3, characterized by The thickness of the gold plating layer (30) is less than or equal to the depth of the mark groove (21).

5. The circuit board of claim 4, wherein, The depth of the mark groove (21) is 10-40 μm.

6. The circuit board according to any one of claims 1 to 3, characterized by The substrate layer (10) includes an insulating plate (11) and a conductive layer (12), the conductive layer (12) is located on the plate surface of the insulating plate (11), and the solder resist layer (20) is located on the surface of the conductive layer (12) away from the insulating plate (11).

7. The circuit board of claim 6, wherein, The thickness of the conductive layer (12) is 15-25 μm.

8. The circuit board of claim 6, wherein, The thickness of the insulating plate (11) is 100-200 μm.

9. The circuit board according to any one of claims 1 to 3, characterized by The shape of the orthographic projection of the gold plating layer (30) on the surface of the substrate layer (10) includes at least one of a character pattern, a number pattern and a two-dimensional code pattern.

10. An electronic device, comprising: The electronic device includes the circuit board according to any one of claims 1-9.

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