Control circuit and active suspension system
By designing redundant control circuits, the active suspension system can safely enter a safe state when the control system fails, solving the problem of controller damage caused by the simultaneous closure of the high-voltage power supply switch and the damping resistor switch, thus improving the safety and reliability of the system.
Patent Information
- Application Number
- CN202520231970.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2035-02-13
AI Technical Summary
In an active suspension system, the simultaneous closure of the high-voltage power supply switch and the damping resistor switch causes the damping resistor to be directly connected to the positive and negative terminals of the high voltage, resulting in damage to the controller.
Design a control circuit in which the control logic of two switches is controlled by the other control system when one control system fails, and the switch state is specified when both systems fail simultaneously, so that the system enters a safe state.
This improves the safety performance of the active suspension controller and reduces the failure rate and malfunction rate.
Smart Images
Figure CN223735800U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of new energy vehicle technology, and in particular to a control circuit and an active suspension system. Background Technology
[0002] Active suspension systems can dynamically and adaptively adjust the suspension during vehicle operation, adjusting the vehicle height to improve passability while maintaining ride comfort and handling stability. They are widely used in various automotive applications.
[0003] One of the core components of an active suspension system is the active suspension controller. To better control the active suspension system, a malfunction in the active suspension controller will trigger a damping resistor state. The high-voltage power supply switch will first disconnect, followed by the damping resistor switch closing, entering a passive damping state. Simultaneous closing of both the high-voltage power supply switch and the damping resistor switch would cause the damping resistor to be directly connected to the positive and negative terminals of the high voltage, generating a large current that could damage the damping resistor or the switch, ultimately damaging the controller.
[0004] It should be noted that the statements herein provide background information in connection with this disclosure only and do not necessarily constitute prior art. Utility Model Content
[0005] In view of the above problems, a control circuit and active suspension system are proposed to overcome or at least partially solve the above problems.
[0006] The embodiments disclosed herein employ the following technical solutions:
[0007] In a first aspect, this disclosure provides a control circuit, which includes: a first system, a second system, a processing circuit, a first switch, and a second switch. The outputs of the first system and the second system are respectively connected to the input of the processing circuit, and the output of the processing circuit is respectively connected to the first switch and the second switch. When the first system and / or the second system malfunctions, the active suspension system enters a safe state by controlling the switching states of the first switch and the second switch.
[0008] Preferably, the first system includes a first system base chip and a first microcontroller chip, the output of the first system base chip is connected to the input of the first microcontroller chip, the first system outputs a first control signal, and the first microcontroller chip outputs a second control signal and a third control signal.
[0009] Preferably, the second system includes a second system base chip and a second microcontroller chip, the output of the second system base chip is connected to the input of the second microcontroller chip, the second system outputs a fourth control signal, and the second microcontroller chip outputs a fifth control signal and a sixth control signal.
[0010] Preferably, the first system is connected to the processing circuit via a first information channel, and the first microcontroller chip is connected to the processing circuit via a second information channel and a third information channel, respectively; the first control signal, the second control signal, and the third control signal are transmitted via the first information channel, the second information channel, and the third information channel, respectively.
[0011] Preferably, the second system is connected to the processing circuit via a fourth information channel, and the second microcontroller chip is connected to the processing circuit via a fifth information channel and a sixth information channel, respectively; the fourth control signal, the fifth control signal, and the sixth control signal are transmitted via the fourth information channel, the fifth information channel, and the sixth information channel, respectively.
[0012] Preferably, the second switch includes a high-voltage power supply switch, the first switch includes a damping resistor switch, the processing circuit outputs a seventh control signal and an eighth control signal, the seventh control signal is connected to the damping resistor switch through a seventh information channel, and the eighth control signal is connected to the high-voltage power supply switch through an eighth information channel.
[0013] Preferably, the processing circuit includes a delay circuit and a discharge circuit, and the delay circuit and the discharge circuit are connected.
[0014] In a second aspect, this disclosure also provides an active suspension system, including control circuitry as described in any of the first aspects.
[0015] The above-described at least one technical solution adopted in the exemplary embodiment can achieve the following beneficial effects:
[0016] An exemplary embodiment of this disclosure is based on two control systems jointly controlling two switches, each switch being jointly controlled by the two control systems; each control system outputs control signals for the two switches in conjunction with external commands. When the first system and / or the second system fails, the switching states of the first and second switches remain under control, enabling the active suspension system to enter a safe state, thereby improving the safety performance of the active suspension controller and reducing the failure rate and malfunction rate.
[0017] It should be understood that the utility model description section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0018] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of some embodiments thereof in the accompanying drawings, in which:
[0019] Figure 1 This is a schematic diagram of the control circuit in an embodiment of this disclosure. Detailed Implementation
[0020] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not impose any limitation on the scope of this disclosure. The disclosure described herein may be implemented in ways other than those described below.
[0021] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.
[0022] References to "an embodiment," "embodiment," "exemplary embodiment," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment needs to include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an exemplary embodiment, whether explicitly described or not, those skilled in the art will recognize that such a feature, structure, or characteristic affects its connection to other embodiments.
[0023] It should be understood that while the terms “first” and “second”, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” as used herein includes any and all combinations of one or more of the listed terms.
[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. The singular forms “a,” “an,” and “the” used herein also include the plural forms unless the context clearly indicates otherwise. The terms “a group of elements” or “a collection of elements” as used herein are intended to include one or more elements. It should also be understood that the terms “comprising,” “including,” “having,” “possessing,” “including,” and / or “comprising,” when used herein, specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.
[0025] What will be understood is that when a component is referred to as "connected to another component," it can be directly connected to another component, or there can be intermediate components. Conversely, when a component is referred to as "directly connected to another component," no intermediate components or layers exist.
[0026] As used in this disclosure, the term "circuit" may refer to one or more of the following:
[0027] (a) Implemented only in hardware circuitry (e.g., implemented only in analog and / or digital circuitry)
[0028] (b) A combination of hardware circuitry and software, such as (if applicable):
[0029] (i) a combination of analog and / or digital hardware circuitry with software / firmware; and
[0030] (ii) Any part of a hardware processor (including a digital signal processor), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions, and
[0031] (c) Hardware circuitry and / or processors, such as microprocessors or a portion thereof, which require software (e.g., firmware) to operate, but may be absent when the software is not required to operate.
[0032] The definition of "circuit" applies to all uses of the term in this disclosure, including in any claim. As another example, as used in this disclosure, the term "circuit" also includes implementations of hardware circuitry or a processor (or processors) or a portion thereof and its accompanying software and / or firmware. The term "circuit" also includes, for example, a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, cellular network device, or other computing network device, if applicable to a particular claim element.
[0033] The design concept of this application is as follows: In view of the current situation in related technologies, the simultaneous closing of the high-voltage power supply switch and the damping resistor switch will cause the damping resistor to be directly connected to the positive and negative terminals of the high voltage, resulting in damage to the controller. The application proposes a universal control circuit. When one of the control circuits fails, the control logic of the two switches is handed over to the other control system. When both control systems fail at the same time, the logic for closing the switch is specified. This improves the safety performance of the active suspension controller and reduces the failure rate and failure rate.
[0034] The technical solutions provided by the embodiments of this disclosure are described in detail below with reference to the accompanying drawings.
[0035] The disclosed embodiments provide a control circuit and an active suspension system. For example... Figure 1As shown, a schematic diagram of the control circuit in an embodiment of this disclosure is provided. The control circuit includes: a first system, a second system, a processing circuit, a first switch, and a second switch. The outputs of the first system and the second system are respectively connected to the input of the processing circuit, and the output of the processing circuit is respectively connected to the first switch and the second switch. When the first system and / or the second system malfunctions, the active suspension system enters a safe state by controlling the switching states of the first switch and the second switch.
[0036] In one example, combined Figure 1 The first control system is Figure 1 System 1 in the middle, the second control system is Figure 1 In system 2, the first switch is Figure 1 SW1, which is the damping resistor switch, is the second switch. Figure 1 SW2 in this context refers to the high-voltage power supply switch.
[0037] In some embodiments, the first system includes a first system base chip and a first microcontroller chip. The output of the first system base chip is connected to the input of the first microcontroller chip. The first system outputs a first control signal, and the first microcontroller chip outputs a second control signal and a third control signal. The first system is connected to the processing circuit through a first information channel, and the first microcontroller chip is connected to the processing circuit through a second information channel and a third information channel, respectively. The first control signal, the second control signal, and the third control signal are transmitted through the first information channel, the second information channel, and the third information channel, respectively.
[0038] In one example, refer to Figure 1 The first system's basic chip is Figure 1 The SBC1 in the middle, the first microcontroller chip is Figure 1 MCU1 in the middle; the first control signal is Figure 1 In SS1, the second control signal is Figure 1 In MCU1_SW1_EN, the third control signal is Figure 1 The MCU1_SW2_EN in System 1. Different control signals in System 1 are sent to the (hardware logic) processing circuit through different information channels. After processing by the processing circuit, relevant control signals are further generated and sent to the switching circuit. Among them, the first information channel, the second information channel, and the third information channel include transmission channels for carrying enable signals. Multiple enable signals can be transmitted through a single transmission channel, or different enable signals can be transmitted through different transmission channels.
[0039] The second system includes a second system base chip and a second microcontroller chip. The output of the second system base chip is connected to the input of the second microcontroller chip. The second system outputs a fourth control signal, and the second microcontroller chip outputs a fifth control signal and a sixth control signal. The second system is connected to the processing circuit through a fourth information channel, and the second microcontroller chip is connected to the processing circuit through the fifth and sixth information channels, respectively. The fourth, fifth, and sixth control signals are transmitted through the fourth, fifth, and sixth information channels, respectively.
[0040] In one example, refer to Figure 1 The second system's basic chip is Figure 1 The SBC2 in the middle, the second microcontroller chip is Figure 1 MCU2 in the middle; the fourth control signal is Figure 1 In SS2, the fifth control signal is Figure 1 In MCU2_SW1_EN, the sixth control signal is Figure 1 The MCU2_SW2_EN in System 2. Different control signals in System 2 are sent to the (hardware logic) processing circuit through different information channels. After processing by the processing circuit, relevant control signals are further generated and sent to the switching circuit. Among them, the fourth, fifth and sixth information channels include transmission channels for carrying enable signals. Multiple enable signals can be transmitted through a single transmission channel, or different enable signals can be transmitted through different transmission channels.
[0041] In some embodiments, the second switch includes a high-voltage power supply switch, the first switch includes a damping resistor switch, the processing circuit outputs a seventh control signal and an eighth control signal, the seventh control signal is connected to the damping resistor switch through a seventh information channel, and the eighth control signal is connected to the high-voltage power supply switch through an eighth information channel.
[0042] In one example, refer to Figure 1 The high-voltage power supply switch is Figure 1 SW2 in the middle is the damping resistor switch. Figure 1 In the context of SW1, the seventh control signal is... Figure 1 In SW1_EN, the eighth control signal is Figure 1 In the SW2_EN (hardware logic) processing circuit, different control signals are sent to the damping resistor switch or high-voltage power supply switch through different information channels to control the switch state. Among them, the seventh and eighth information channels include transmission channels for carrying enable signals. Multiple enable signals can be transmitted through a single transmission channel, or different enable signals can be transmitted through different transmission channels.
[0043] In one example, the processing circuit includes a delay circuit and a discharge circuit. To prevent one switch from closing before the other is fully open, an RC delay circuit and a diode fast discharge circuit are added to the processing circuit.
[0044] It is understood that this disclosure processes the SW1 and SW2 control signals and fault flag signals output by the MCU to achieve redundant control and error correction design, ensuring that the two switch control states can enter a safe state regardless of whether there is a software failure or a hardware failure.
[0045] To better illustrate the control logic of the control circuit in this disclosure, the following explanation is provided:
[0046] MCU1 outputs signals MCU1_SW1_EN and MCU1_SW2_EN; MCU2 outputs signals MCU2_SW1_EN and MCU2_SW2_EN. The SBC and MCU form a minimum system. When the system (SBC1 and MCU1, SBC2 and MCU2) is normal, SS1 / SS2 outputs 1; when the system (including SBC1 and MCU1, SBC2 and MCU2) malfunctions, SS1 / SS2 outputs 0. After processing by the hardware logic circuit, these signals output SW1_EN and SW2_EN signals to control the SW1 and SW2 switches.
[0047] When both System 1 and System 2 are functioning normally, the switching states of SW1 and SW2 are controlled by commands issued by MCU1 and MCU2: when the commands from MCU1 and MCU2 to control SW1 and SW2 are consistent, the corresponding SW1 or SW2 closes; when the commands from MCU1 and MCU2 are inconsistent, both SW1 and SW2 open. The specific processing logic is as follows:
[0048] SS1 SS2 MCU1_SW2_EN MCU1_SW1_EN MCU2_SW2_EN MCU2_SW1_EN SW2_EN SW1_EN SW2 SW1 1 1 1 0 1 0 1 0 closure disconnect 1 1 0 1 0 1 0 1 disconnect closure 1 1 1 0 0 1 0 0 disconnect disconnect 1 1 0 1 1 0 0 0 disconnect disconnect
[0049] When system 1 malfunctions, the switching states of SW1 and SW2 are controlled by instructions issued by MCU2, and the processing logic is as follows:
[0050] SS1 SS2 MCU1_SW2_EN MCU1_SW1_EN MCU2_SW2_EN MCU2_SW1_EN SW2_EN SW1_EN SW2 SW1 0 1 X X 1 0 1 0 closure disconnect 0 1 X X 0 1 0 1 disconnect closure
[0051] When system 2 malfunctions, the switching states of SW1 and SW2 are controlled by instructions issued by MCU1, and the processing logic is as follows:
[0052] SS1 SS2 MCU1_SW2_EN MCU1_SW1_EN MCU2_SW2_EN MCU2_SW1_EN SW2_EN SW1_EN SW2 SW1 1 0 1 0 X X 1 0 closure disconnect 1 0 0 1 X X 0 1 disconnect closure
[0053] When both System 1 and System 2 fail, SW1 closes and SW2 opens. The processing logic is as follows:
[0054] SS1 SS2 MCU1_SW2_EN MCU1_SW1_EN MCU2_SW2_EN MCU2_SW1_EN SW2_EN SW1_EN SW2 SW1 0 0 X X X X 0 1 disconnect closure
[0055] It is understood that in the exemplary embodiment, MCU1 and MCU2 do not distinguish between master and slave, and both MCUs jointly control SW1 and SW2. When the output instructions of MCU1 and MCU2 to control SW1 and SW2 are consistent, the corresponding SW1 or SW2 is closed; when the output instructions of MCU1 and MCU2 to control SW1 and SW2 are inconsistent, both SW1 and SW2 are open. In addition, this disclosure can prevent SW1 and SW2 from operating in unexpected states: when one system fails, the control of SW1 / SW2 is transferred to the other system; when both systems fail, a specific safe state is entered (SW1 closed, SW2 open).
Claims
1. A control circuit, characterized by The control circuit comprises a first system, a second system, a processing circuit, a first switch and a second switch, The output of the first system and the output of the second system are connected with the input of the processing circuit respectively, and the output of the processing circuit is connected with the first switch and the second switch respectively; When the first system and / or the second system fails, the active suspension system enters a safe state by controlling the switch state of the first switch and the second switch.
2. The control circuit of claim 1, wherein The first system comprises a first system base chip and a first micro control chip, the output of the first system base chip is connected with the input of the first micro control chip, the first system outputs a first control signal, and the first micro control chip outputs a second control signal and a third control signal.
3. The control circuit of claim 1, wherein The second system comprises a second system base chip and a second micro control chip, the output of the second system base chip is connected with the input of the second micro control chip, the second system outputs a fourth control signal, and the second micro control chip outputs a fifth control signal and a sixth control signal.
4. The control circuit of claim 2, wherein, The first system is connected with the processing circuit through a first information channel, and the first micro control chip is connected with the processing circuit through a second information channel and a third information channel respectively; The first control signal, the second control signal and the third control signal are transmitted by the first information channel, the second information channel and the third information channel respectively.
5. The control circuit of claim 3, wherein, The second system is connected with the processing circuit through a fourth information channel, and the second micro control chip is connected with the processing circuit through a fifth information channel and a sixth information channel respectively; The fourth control signal, the fifth control signal and the sixth control signal are transmitted by the fourth information channel, the fifth information channel and the sixth information channel respectively.
6. The control circuit of any one of claims 1 to 5, wherein, The second switch comprises a high-voltage power supply switch, the first switch comprises a damping resistance switch, the processing circuit outputs a seventh control signal and an eighth control signal, The seventh control signal is connected with the damping resistance switch through a seventh information channel, and the eighth control signal is connected with the high-voltage power supply switch through an eighth information channel.
7. The control circuit of claim 6, wherein The processing circuit comprises a delay circuit and a discharge circuit, and the delay circuit and the discharge circuit are connected.
8. An active suspension system characterized by, The control circuit comprises a first system, a second system, a processing circuit, a first switch and a second switch, The output of the first system and the output of the second system are connected with the input of the processing circuit respectively, and the output of the processing circuit is connected with the first switch and the second switch respectively; When the first system and / or the second system fails, the active suspension system enters a safe state by controlling the switch state of the first switch and the second switch. The first system comprises a first system base chip and a first micro control chip, the output of the first system base chip is connected with the input of the first micro control chip, the first system outputs a first control signal, and the first micro control chip outputs a second control signal and a third control signal. The second system comprises a second system base chip and a second micro control chip, the output of the second system base chip is connected with the input of the second micro control chip, the second system outputs a fourth control signal, and the second micro control chip outputs a fifth control signal and a sixth control signal. The first system is connected with the processing circuit through a first information channel, and the first micro control chip is connected with the processing circuit through a second information channel and a third information channel respectively; The first control signal, the second control signal and the third control signal are transmitted by the first information channel, the second information channel and the third information channel respectively. The second system is connected with the processing circuit through a fourth information channel, and the second micro control chip is connected with the processing circuit through a fifth information channel and a sixth information channel respectively; The fourth control signal, the fifth control signal and the sixth control signal are transmitted by the fourth information channel, the fifth information channel and the sixth information channel respectively. The second switch comprises a high-voltage power supply switch, the first switch comprises a damping resistance switch, the processing circuit outputs a seventh control signal and an eighth control signal, The seventh control signal is connected with the damping resistance switch through a seventh information channel, and the eighth control signal is connected with the high-voltage power supply switch through an eighth information channel. The processing circuit comprises a delay circuit and a discharge circuit, and the delay circuit and the discharge circuit are connected. The control circuit comprises a first system, a second system, a processing circuit, a first switch and a second switch, The output of the first system and the output of the second system are connected with the input of the processing circuit respectively, and the output of the processing circuit is connected with the first switch and the second switch respectively; When the first system and / or the second system fails, the active suspension system enters a safe state by controlling the switch state of the first switch and the second switch.