Identification circuit and Ethernet equipment

Abstract

The utility model discloses an identification circuit and Ethernet equipment, and belongs to the field of circuits. The identification circuit provided by the utility model comprises an SoC and an isolation transformer, the SoC is provided with at least one pair of signal pins matched with the isolation transformer, and the SoC is connected with the isolation transformer through the at least one pair of signal pins; under the condition that the isolation transformer is a first-class transformer, the at least one pair of signal pins are in a first state; under the condition that the isolation transformer is a second type transformer, the at least one pair of signal pins is in a second state; the first type of transformer is different from the second type of transformer, and the first state is different from the second state.

Description

Technical Field

[0001] This application belongs to the field of circuits, specifically relating to an identification circuit and an Ethernet device. Background Technology

[0002] Currently, to enable communication between Ethernet devices, Ethernet device 1 typically includes a System-on-Chip (SoC), an isolation transformer, and a connector. Ethernet device 1 communicates with the other end's Ethernet device 2 via the SoC, isolation transformer, and connector. When the SoC has a built-in Gigabit Ethernet PHY (Physical Layer) module, to improve the speed of establishing communication connections between Ethernet devices, the SoC needs to identify the type of the isolation transformer and determine whether to disable the SoC's Gigabit negotiation capability.

[0003] In related technologies, a GPIO (General Purpose Input Output) interface on the SoC is used to identify the type of transformer connected to the SoC. If the SoC is connected to a gigabit transformer, the hardware controls the GPIO interface to input a low-level signal to keep the gigabit negotiation capability enabled. If the SoC is connected to a 100 Mbps transformer, the hardware controls the GPIO interface to input a high-level signal to disable the gigabit negotiation capability, thereby improving the speed of establishing communication connections between Ethernet devices.

[0004] However, for a SoC, hardware resources such as GPIO are often very scarce. In related technologies, the SoC needs to identify the type of isolation transformer connected, which requires an additional GPIO interface on the SoC, resulting in a waste of SoC hardware resources. Utility Model Content

[0005] This application provides an identification circuit and Ethernet device that can solve the problem in related technologies where the SoC occupies an additional GPIO interface to identify the transformer type, thus wasting SoC hardware resources.

[0006] In a first aspect, embodiments of this application provide an identification circuit, including: a SoC and an isolation transformer; the SoC has at least one pair of signal pins adapted to the isolation transformer, and the SoC is connected to the isolation transformer through the at least one pair of signal pins;

[0007] When the isolation transformer is a first type of transformer, the at least one pair of signal pins is in a first state; when the isolation transformer is a second type of transformer, the at least one pair of signal pins is in a second state.

[0008] The first type of transformer is different from the second type of transformer, and the first state is different from the second state.

[0009] Secondly, embodiments of this application provide an Ethernet device, including: the identification circuit described in the first aspect.

[0010] In this embodiment, the identification circuit includes a System-on-a-Chip (SoC) and an isolation transformer. The SoC has at least one pair of signal pins adapted to the isolation transformer, and the SoC is connected to the isolation transformer through the at least one pair of signal pins. When the isolation transformer is a first type of transformer, the at least one pair of signal pins is in a first state; when the isolation transformer is a second type of transformer, the at least one pair of signal pins is in a second state. The first type of transformer is different from the second type of transformer, and the first state is different from the second state. In this way, the SoC can identify the type of isolation transformer using the state of the at least one pair of signal pins adapted to the isolation transformer. Compared with related technologies, this eliminates the need for additional GPIO interfaces to identify the transformer type, thus avoiding waste of SoC hardware resources. Attached Figure Description

[0011] Figure 1 A schematic diagram illustrating the establishment of a connection between network devices in a related technology;

[0012] Figure 2 This is a schematic diagram illustrating how a SoC within a network device identifies a gigabit transformer via a GPIO interface, as provided in related technologies.

[0013] Figure 3 This is a schematic diagram illustrating how a SoC within a network device identifies a 100Mbps transformer via a GPIO interface, as provided in related technologies.

[0014] Figure 4 A schematic structural diagram of an identification circuit provided in an embodiment of this application;

[0015] Figure 5-1 A schematic structural diagram of another identification circuit provided in an embodiment of this application;

[0016] Figure 5-2 A schematic structural diagram of another identification circuit provided in an embodiment of this application;

[0017] Figure 5-3 A schematic structural diagram of another identification circuit provided in an embodiment of this application;

[0018] Figure 5-4 A schematic structural diagram of another identification circuit provided in an embodiment of this application;

[0019] Figure 6-1A schematic structural diagram of a SoC connecting a gigabit transformer provided in an embodiment of this application;

[0020] Figure 6-2 A schematic structural diagram of a SoC connected to a 100Mbps transformer provided in an embodiment of this application;

[0021] Figure 7-1 A partial structural diagram of the identification circuit provided in the embodiments of this application;

[0022] Figure 7-2 A schematic structural diagram of another SoC connecting a gigabit transformer provided in an embodiment of this application;

[0023] Figure 7-3 A schematic structural diagram of another SoC connecting a 100Mbps transformer provided in an embodiment of this application;

[0024] Figure 8 This is a schematic structural diagram of an Ethernet device provided in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 10 - Identification circuit; 100 - SoC; 110 - Gigabit Ethernet physical layer PHY module; MDI - Signal pin; 200 - Isolation transformer; 210 - Type 1 transformer; 220 - Type 2 transformer; 300 - Pin status control unit; 310 - First pin status control unit; 320 - Second pin status control unit; RJ45 - Connector; MDIP - First signal pin; MDIN - Second signal pin; MDI0P / MDI0N / MDI1P / MDI1N - Data transmission pin; MDI2P / MDI2N / MDI3P / MDI3N - Pin for identifying transformer type; R1 - First adjustable resistor; R2 - Second adjustable resistor; R3 - Third adjustable resistor; R4 - Fourth adjustable resistor; R5 - Fifth adjustable resistor; R6 - Sixth adjustable resistor; 800 - Ethernet device. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0028] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0029] A System-on-a-Chip (SoC) is a dedicated integrated circuit that fully integrates multiple functions. Typically, for an SoC to utilize network functions, it needs to connect to an Ethernet PHY chip. With further advancements in process and design technologies, it's possible to integrate the Ethernet PHY chip directly into the SoC. However, this technology is often highly complex, and currently, most SoCs on the market integrate 100Mbps Ethernet PHY chips; SoCs integrating gigabit Ethernet PHY chips are relatively rare. Integrating a gigabit Ethernet PHY chip into the SoC not only reduces costs (saving PCB space by eliminating the need for direct PCB connections between the PHY module and the CPU) but also enhances the chip's competitiveness (offering wider application scenarios, suitability for products with varying network speeds, supporting up to gigabit speeds while backward compatible with 100Mbps and 10Mbps).

[0030] For example, such as Figure 1 As shown, in the prior art, Ethernet device 1 includes: a CPU, a MAC (Media Access Control) controller, a Gigabit Ethernet physical layer PHY module, an isolation transformer, and a connector (RJ45). One end of the RJ45 is connected to the PHY module integrated inside the SoC through the isolation transformer, and the other end is connected to Ethernet PHY chips with different capabilities. Different Ethernet devices generally use auto-negotiation technology to automatically determine the optimal connection speed and duplex mode.

[0031] Among them, isolation transformers are divided into gigabit transformers and 100-megabit transformers. Based on the maximum speed supported by the Ethernet PHY chip and the type of transformer connected, assuming that the physical connection is normal, the speed types that can be connected according to auto-negotiation technology are shown in Table 1 below.

[0032]

[0033] Table 1

[0034] Typically, Gigabit Ethernet PHY chips are connected to Gigabit transformers, and 100Mbps Ethernet PHY chips are connected to 100Mbps transformers. However, for a SoC with a built-in Gigabit Ethernet PHY chip, any type of transformer may be used, making the transformer type a black box for the SoC. As shown in Table 1 above, which illustrates the network connection establishment time under different Ethernet devices and transformer connections, different transformer types and the type of peer network device will affect the network connection establishment time. For some products with very sensitive establishment time, this is unacceptable.

[0035] Since the product's network functionality relies on establishing a network connection between two devices, if each connection establishment takes an extra 4 seconds or more, the user experience will be poor, thus reducing the product's competitiveness. Furthermore, the network plays another crucial role: customers use it to program and upgrade the product's factory application. For each SoC, only one programming and upgrade tool exists, compatible with different product forms. If establishing a network connection takes an extra 4 seconds when programming a product, this represents a significant increase in production time costs for products with tens of millions of units shipped. This is unacceptable to customers. Therefore, it is necessary to improve the connection establishment speed in this scenario and save connection time.

[0036] Normally, two network devices establish a connection using auto-negotiation technology. Auto-negotiation involves exchanging a special FLP (Fast Link Plus) frame with the peer, which contains the operating modes (speed / duplex) that the device supports. The peer then compares this frame with its own supported modes and selects the optimal one. When exchanging FLPs, both devices detect the best mode shared by both sides based on the following priorities from highest to lowest: 1000M full-duplex, 100M full-duplex, 100M half-duplex, 10M full-duplex, 10M half-duplex.

[0037] Therefore, the SoC can identify whether the hardware is connected to a 100 Mbps transformer or a gigabit transformer. If the SoC is connected to a 100 Mbps transformer, the gigabit negotiation capability supported by the Ethernet PHY chip itself is turned off. This prevents the FLP frames sent by the auto-negotiation technology from having gigabit capability frames and only sending 100 Mbps full-duplex frames. In this way, two Ethernet devices can establish a connection in about 2 seconds, which greatly saves time and improves efficiency.

[0038] In related technologies, existing solutions for enabling the SoC to identify the type of connected transformer use a hardware GPIO. If the gigabit Ethernet PHY chip is connected to a gigabit transformer, the hardware sets this GPIO to a low-level signal (GND) to not disable gigabit negotiation capability. Figure 2 If the gigabit Ethernet PHY chip is connected to a 100 Mbps transformer, the hardware should set this GPIO input to a high-level signal (VCC) to disable gigabit negotiation capability, such as... Figure 3 As can be seen, the existing solution is to pull up or pull down a GPIO on the SoC in hardware. Although this GPIO can be used to identify the transformer type, it cannot be used for other functions. For a SoC, GPIO resources are often very scarce, and it adds extra hardware circuitry.

[0039] Based on this, in the identification circuit provided in this application embodiment, the SoC can identify the type of isolation transformer by the state of at least one pair of signal pins MDI that are adapted to the isolation transformer. Compared with related technologies, there is no need to waste SoC hardware resources, which solves the problem that in related technologies, SoC must waste SoC hardware resources to identify the type of the connected isolation transformer.

[0040] The identification circuit and Ethernet device provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0041] Figure 4 This is a schematic structural diagram of an identification circuit provided in an embodiment of this application.

[0042] like Figure 4 As shown, the identification circuit 10 provided in this application embodiment may include: SoC 100 and isolation transformer 200; SoC 100 has at least one pair of signal pins MDI adapted to isolation transformer 200, and SoC 100 is connected to isolation transformer 200 through at least one pair of signal pins MDI.

[0043] In this embodiment, the state of at least one pair of signal pins MDI corresponds to the type of the isolation transformer 200.

[0044] When the isolation transformer 200 is a Class 1 transformer, at least one pair of signal pins MDI is in the first state;

[0045] When the isolation transformer 200 is a Class II transformer, at least one pair of signal pins MDI are in the second state;

[0046] Among them, the first type of transformer is different from the second type of transformer, and the first state is different from the second state.

[0047] For example, the first state can be the termination state, which can be understood as the state in which the signal pin MDI is connected to the isolation transformer.

[0048] For example, the second state can be an open circuit state or a short circuit state. In the open circuit state or the short circuit state, the signal pin MDI is not connected to the isolation transformer.

[0049] For example, the first type of transformer is one of a gigabit transformer and a 100-megabit transformer, and the second type of transformer is the other of a gigabit transformer and a 100-megabit transformer. Furthermore, the SoC can identify whether the isolation transformer is a gigabit transformer or a 100-megabit transformer by the state of at least one pair of signal pins that are adapted to the isolation transformer.

[0050] It should be noted that related technologies require an additional GPIO interface on the SoC to identify the type of isolation transformer connected to the SoC. In contrast, in this embodiment, the state of at least one pair of signal pins MDI corresponds to the type of isolation transformer 200. The SoC can identify the type of isolation transformer by the state of at least one pair of signal pins adapted to the isolation transformer. Compared with related technologies, this eliminates the need to waste SoC hardware resources, thus solving the problem that in related technologies, identifying the type of connected isolation transformer requires the waste of SoC hardware resources.

[0051] The identification circuit provided according to an embodiment of this application includes a System-on-a-Chip (SoC) and an isolation transformer. The SoC has at least one pair of signal pins adapted to the isolation transformer, and the SoC is connected to the isolation transformer through the at least one pair of signal pins. The state of the at least one pair of signal pins corresponds to the type of the isolation transformer. When the isolation transformer is a first type of transformer, the at least one pair of signal pins is in a first state; when the isolation transformer is a second type of transformer, the at least one pair of signal pins is in a second state. The first type of transformer is different from the second type of transformer, and the first state is different from the second state. In this way, the SoC can identify the type of the isolation transformer using the state of the at least one pair of signal pins adapted to the isolation transformer. Compared with related technologies, this eliminates the need for additional GPIO interfaces to identify the transformer type, thus avoiding waste of SoC hardware resources.

[0052] To reduce the operating power consumption of the SoC and avoid the SoC continuously monitoring the state of at least one pair of signal pins, embodiments of this application can employ a pin state control unit to accurately control the state of at least one pair of signal pins I. For example, in a specific embodiment, such as... Figure 4 As shown, the identification circuit 10 provided in this application embodiment may further include: a pin state control unit 300, and at least one pair of signal pins MDI connected to the pin state control unit 300.

[0053] At least one pair of signal pins MDI can have different pin states, such as terminated, short-circuited, or open-circuited. Correspondingly, the pin state control unit 300 can control at least one pair of signal pins to be in different pin states.

[0054] For example, when the isolation transformer is a Class I transformer, the pin state control unit can put at least one pair of signal pins in the first state;

[0055] For example, when the isolation transformer is a type II transformer, the pin state control unit can put at least one pair of signal pins in the second state.

[0056] In this way, according to the type of isolation transformer, a pin state control unit is used to control at least one pair of signal pins MDI to be in a state corresponding to the type of isolation transformer. This allows the SoC to accurately identify the type of isolation transformer by detecting the state of at least one pair of signal pins MDI, and avoids the SoC from continuously detecting the state of the above at least one pair of signal pins, thereby reducing the operating power consumption of the SoC.

[0057] For example, in one specific embodiment, in order to achieve control of at least one pair of signal pins MDI, such as Figure 5-1 As shown, in the identification circuit 10 provided in this application embodiment, at least one pair of signal pins may include a first signal pin MDIP and a second signal pin MDIN;

[0058] The pin status control unit may include a first adjustable resistor R1, a second adjustable resistor R2, and a third adjustable resistor R3;

[0059] The first signal pin MDIP is connected to the second signal pin MDIN through the first adjustable resistor R1, the first signal pin MDIP is connected in series with the second adjustable resistor R2, and the second signal pin MDIN is connected in series with the third adjustable resistor R3.

[0060] By adjusting the resistance value of the first adjustable resistor R1, the first signal pin MDIP and the second signal pin MDIN can be controlled to be in a short-circuit state.

[0061] By adjusting the value of the second adjustable resistor R2, the first signal pin MDIP can be controlled to be in a terminated state or an open-circuit state.

[0062] By adjusting the value of the third adjustable resistor R3, the second signal pin MDIN can be controlled to be in a terminated state or an open circuit state.

[0063] Specifically, such as Figure 5-2The first state can be the termination state; when the isolation transformer 200 is a first-class transformer 210, the resistance of the first adjustable resistor R1 is infinite, the resistance of the second adjustable resistor R2 and the third adjustable resistor R3 are both zero, and the first signal pin MDIP and the second signal pin MDIN are in the termination state.

[0064] The first adjustable resistor R1 has an infinite resistance, which disconnects the first signal pin MDIN and the second signal pin MDIP. The second adjustable resistor R2 and the third adjustable resistor R3 both have zero resistance, which connects the first signal pin and the second signal pin to the isolation transformer.

[0065] In this way, the SoC can accurately identify the isolation transformer as a type 1 transformer by detecting that the first signal pin MDIN and the second signal pin MDIP are in a terminated state, without occupying additional hardware resources of the SoC.

[0066] In addition, such as Figure 5-3 The second state can be a short circuit state; when the isolation transformer 200 is a second type transformer 220, the resistance of the first adjustable resistor R1 is zero, the resistance of the second adjustable resistor R2 and the third adjustable resistor R3 are both infinite, and the first signal pin MDIP and the second signal pin MDIN are in a short circuit state.

[0067] The first adjustable resistor R1 has a resistance of zero, while the second adjustable resistor R2 and the third adjustable resistor R3 both have infinite resistances, thus connecting the first signal pin MDIP and the second signal pin MDIN together.

[0068] In this way, the SoC can accurately identify the isolation transformer as a second-type transformer by detecting that the first signal pin MDIP and the second signal pin MDIN are in a short-circuit state, without occupying additional hardware resources of the SoC.

[0069] Alternatively, in other embodiments, such as Figure 5-4 The second state can be an open circuit state; when the isolation transformer 200 is a second type transformer 220, the resistance values ​​of the first adjustable resistor R1, the second adjustable resistor R2 and the third adjustable resistor R3 are all infinite. At this time, the first signal pin MDIP and the second signal pin MDIN can be in an open circuit state (i.e., floating).

[0070] Among them, the resistance values ​​of the first adjustable resistor R1, the second adjustable resistor R2 and the third adjustable resistor R3 are all infinite, so that the first signal pin MDIN and the second signal pin MDIP are floating.

[0071] In this way, the SoC can accurately identify the isolation transformer as a second-type transformer by detecting that the first signal pin MDIN and the second signal pin MDIP are in an open-circuit state, without occupying additional hardware resources of the SoC.

[0072] In practical applications, in order to reduce costs and improve the competitiveness of the SoC, the SoC100 may include a Gigabit Ethernet physical layer PHY module 110, which is connected to the isolation transformer 200.

[0073] Among them, at least one pair of signal pins MDI are pins within the Gigabit Ethernet physical layer PHY module 110.

[0074] Thus, in this embodiment, the status of the first signal pin MDIN and the second signal pin MDIP is obtained through the Gigabit Ethernet physical layer PHY module inside the SoC, thereby correctly identifying the transformer type connected to the SoC. When the Gigabit Ethernet physical layer PHY module detects that the connected transformer is a 100 Mbps transformer, the Gigabit negotiation capability is turned off and the 100 Mbps negotiation capability is turned on. The maximum connection speed of the FLP frame sent by the network device is modified in an adaptive manner, thereby improving the network connection speed and saving the time of the network device to establish a connection.

[0075] Additionally, when the Gigabit Ethernet physical layer PHY module 110 is transmitting data, at least one pair of signal pins MDI is in an idle state.

[0076] In other words, the Gigabit Ethernet physical layer PHY module 110 uses other pins to transmit data, and at least one pair of signal pins used to identify the transformer type are not used for data transmission.

[0077] In this way, the type of isolation transformer 200 can be accurately identified by utilizing the status of idle pins within the Gigabit Ethernet physical layer PHY module 110, without affecting the original data transmission function of the Gigabit Ethernet physical layer PHY module 110.

[0078] The following explanation uses the SoC100's built-in Gigabit Ethernet physical layer PHY module, which has 8 pins, as an example.

[0079] The Gigabit Ethernet physical layer PHY module may include: MDI0P pin, MDI0N pin, MDI1P pin, MDI1N pin, MDI2P pin, MDI2N pin, MDI3P pin and MDI3N pin;

[0080] Among them, MDI0P pin, MDI0N pin, MDI1P pin and MDI1N pin are data transmission pins;

[0081] The at least one pair of signal pins used to identify the type of isolation transformer may include: MDI2P pin, MDI2N pin, MDI3P pin, and MDI3N pin.

[0082] The states of the MDI2P, MDI2N, MDI3P, and MDI3N pins can be controlled through the SoC's own software functions, or through a combination of the SoC and a pin state control unit. Examples are given below.

[0083] The SoC's built-in Gigabit Ethernet physical layer PHY module has eight pins: MDI0P, MDI0N, MDI1P, MDI1N, MDI2P, MDI2N, MDI3P, and MDI3N. When two network devices establish a 100 Mbps connection, only four pins—MDI0P, MDI0N, MDI1P, and MDI1N—are used to receive and transmit data. Therefore, the status of the other four pins can be used to identify this special application scenario.

[0084] The SoC's built-in Ethernet physical layer PHY module supports cable diagnostics, which identifies the status of eight pins. Pin status can be categorized into three types: terminated, open, and short. Specifically, when two Ethernet devices establish a connection, the status is terminated; if no Ethernet device connection is established and MDIP and MDIN are not connected, the status is open; if the P and N pins of one set of MDI pins are connected together, the status is short.

[0085] Depending on the type of transformer connected to the SoC, whether the RJ45 is plugged into a network cable, and whether it is connected to a network device (which must be working properly), enable the SoC's built-in Ethernet PHY cable diagnostic function. Without introducing additional hardware circuitry, the cable diagnostic status of the 4 pairs of MDI pins can be obtained, as shown in Table 2 below.

[0086]

[0087] Table 2

[0088] The SoC can distinguish the type of transformer connected to the Ethernet PHY based on the different states of these MDI pins. The specific determination method of the SoC is as follows:

[0089] Initialize the SoC's built-in Gigabit Ethernet physical layer PHY module;

[0090] Determine if the network cable is connected to the RJ45 connector;

[0091] When the network cable is connected to the RJ45 connector, enable the built-in Ethernet PHY cable diagnostic function of the SoC.

[0092] Determine the state of MDI0 / 1 / 2 / 3;

[0093] When MDI0 / 1 / 2 / 3 is in an open circuit state, continuously monitor the state of MDI0 / 1 / 2 / 3;

[0094] With MDI0 / 1 / 2 / 3 in the terminated state, it is confirmed that the isolation transformer connected to the SoC is a gigabit transformer (refer to...). Figure 6-1 ), SoC enables gigabit Ethernet PHY negotiation capability;

[0095] With MDI0 / 1 in the terminated state and MDI / 2 / 3 in the open (i.e., floating) state, it is determined that the isolation transformer connected to the SoC is a 100M transformer (refer to...). Figure 6-2 The SoC disables gigabit Ethernet PHY negotiation capability and enables 100 Mbps negotiation capability.

[0096] In this way, without introducing additional hardware resources into the SoC, the type of isolation transformer connected in the hardware can be determined by running software on the SoC. However, in this solution, the SoC continuously runs a detection program to monitor whether the RJ45 is plugged in the network cable. Only after the network cable is plugged in and the connected network device is working normally, can it determine that the MDI status is MDI0 / 1 terminated and MDI2 / 3 open, which matches the case of a 100Mbps transformer; when it determines that the MDI status is MDI0 / 1 / 2 / 3 all terminated, it matches the case of a gigabit transformer.

[0097] Based on the above solution, further optimizations are made to run the program only once during SoC initialization. If a 100Mbps transformer is used, the P and N pins of the MDI2 / 3 pins of the SoC's built-in Gigabit Ethernet physical layer PHY module are shorted, which does not occupy additional SoC hardware resources and avoids wasting SoC resources.

[0098] To reduce the power consumption of the SoC and avoid the SoC running detection programs continuously, in other embodiments, the SoC can combine a pin status control unit to determine the status of the MDI pin.

[0099] like Figure 7-1 As shown, the pin status control unit may include a first pin status control unit 310 and a second pin status control unit 320; the first pin status control unit 310 may include a first adjustable resistor R1, a second adjustable resistor R2 and a third adjustable resistor R3; the second pin status control unit 310 may include a fourth adjustable resistor R4, a fifth adjustable resistor R5 and a sixth adjustable resistor R6.

[0100] Adding a pin status control unit (R1 to R6) to the identification circuit can control the short circuit of MDI2 / 3 (this pin status control unit can also be called the MDI2 / 3 shorting circuit). Depending on the type of transformer connected to the SoC, whether the RJ45 is plugged into a network cable, and whether it is connected to a network device (which must be working properly), the built-in Ethernet PHY cable diagnostic function of the SoC is enabled. With the MDI2 / 3 shorting circuit introduced, the cable diagnostic status of the MDI2 / 3 pins is shown in Table 3 below.

[0101]

[0102] Table 3

[0103] The SoC can distinguish the type of transformer connected to the Ethernet PHY based on the different states of these MDI pins. The specific determination method of the SoC is as follows:

[0104] Initialize the SoC's built-in Gigabit Ethernet physical layer PHY module;

[0105] Enable the built-in Ethernet PHY cable diagnostic function of the SoC;

[0106] Determine whether MDI2 / 3 is in a short-circuit state;

[0107] If MDI2 / 3 is not in a short-circuit state, it is determined that the isolation transformer connected to the SoC is a gigabit transformer (reference). Figure 7-2 ), SoC enables gigabit Ethernet PHY negotiation capability;

[0108] With MDI2 / 3 in a short-circuit state, it is determined that the isolation transformer connected to the SoC is a 100M transformer (reference). Figure 7-3 The SoC disables gigabit Ethernet PHY negotiation capability and enables 100 Mbps negotiation capability.

[0109] For example, when the isolation transformer is a gigabit transformer, the MDI2P, MDI2N, MDI3P, and MDI3N pins are all in a terminated state; when the isolation transformer is a 100M transformer, the MDI2P, MDI2N, MDI3P, and MDI3N pins are all in a short-circuit state.

[0110] In this way, in scenarios where the MDI2 / 3 short-circuit circuit is introduced into the identification circuit, there is no need to determine whether the network cable is connected to the RJ45 connector. Instead, it is possible to directly determine whether the MDI2 / 3 state is short-circuited. If the MDI2 / 3 state is short-circuited, it is determined that the SoC is connected to a 100Mbps transformer. If the MDI2 / 3 state is not short-circuited (e.g., in a termination state), it is determined that the SoC is connected to a gigabit transformer. This saves the software resources consumed by the SoC in determining whether the network cable is inserted into the RJ45 connector.

[0111] It should be noted that the isolation transformer type connected to the SoC's built-in Gigabit Ethernet PHY chip is a black box to the SoC. Different transformer types and different network devices result in different network connection establishment times. In some product applications with strict requirements for network connection time, it is necessary to improve the network connection time. The network connection time is mainly affected by the transformer. Based on this, this embodiment proposes an identification circuit and identification scheme for identifying the transformer type connected to the SoC's built-in Ethernet PHY. Specifically, adjustable resistors R1~R6 are used to control the state of pins MDI2P / MDI2N / MDI3P / MDI3N of the SoC's built-in Gigabit Ethernet PHY chip.

[0112] If the SoC is connected to a gigabit transformer, the resistance of R2, R3, R5, and R6 is set to 0, while R1 and R4 are set to infinity (disconnected), which is no different from normal applications. If the SoC is connected to a 100-megabit transformer, the resistance of R1 and R4 is set to 0, while R2, R3, R5, and R6 are set to infinity (disconnected), creating a special hardware state (MDI2P / MDI2N / MDI3P / MDI3N short circuit). The SoC's own cable diagnostic function can correctly identify the state of MDI2P / MDI2N / MDI3P / MDI3N, thereby distinguishing the type of transformer connected to the SoC. This ensures stability and reliability without increasing additional hardware costs, and the original functions of the SoC are not affected.

[0113] It should be noted that the SoC's cable diagnostic function is generally only used for basic diagnostics, checking whether the network cable is physically intact. However, in this embodiment, the SoC's cable diagnostic function identifies the status of MDI2P / MDI2N / MDI3P / MDI3N, thereby correctly identifying the transformer type connected to the SoC. This allows for adaptive modification of the maximum connection speed of the FLP frames sent by the network device, improving network connection speed and saving connection time.

[0114] With this solution, there is no need to additionally determine whether the network cable is plugged in or whether the connected network device is working properly. The status of MDI2 / 3 can be directly determined, which can distinguish the type of isolation transformer. It does not affect the use of the SoC's 100 Mbps Ethernet function and also saves the software resources consumed by the SoC in determining whether the network cable is plugged into the RJ45 connector.

[0115] Based on the same technical concept as the identification circuit provided in the above embodiments, this application also provides an Ethernet device, including the identification circuit provided in any of the above embodiments.

[0116] Figure 8 This is a schematic diagram of an Ethernet device provided in an embodiment of this application.

[0117] like Figure 8 As shown, the Ethernet device 800 provided in this application embodiment includes the identification circuit 10 provided in any of the above embodiments.

[0118] The identification circuit 10 includes a SoC 100 and an isolation transformer 200; the Ethernet device 800 also includes a connector RJ45; the SoC 100 is connected to the isolation transformer 200 and the connector RJ45 in sequence.

[0119] The SoC100 has a Gigabit Ethernet physical layer PHY module, which has multiple pairs of MDI pins. The status of some of these MDI pins can be used to identify the type of the isolation transformer 200.

[0120] It should be noted that the Ethernet device provided in this application includes the identification circuit provided in any of the above embodiments, and can realize all the functions of the identification circuit provided in any of the above embodiments. To avoid repetition, it will not be described again here.

[0121] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0122] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. An identification circuit, characterized by Comprising: a system on chip (SoC) and an isolation transformer; the SoC has at least one pair of signal pins adapted to the isolation transformer, and the SoC is connected to the isolation transformer through the at least one pair of signal pins; in the case that the isolation transformer is a first type of transformer, the at least one pair of signal pins is in a first state; in the case that the isolation transformer is a second type of transformer, the at least one pair of signal pins is in a second state; wherein the first type of transformer is different from the second type of transformer, and the first state is different from the second state.

2. The identification circuit of claim 1, wherein The identification circuit further comprises a pin state control unit, and the at least one pair of signal pins is connected to the pin state control unit.

3. The identification circuit of claim 2, wherein: the at least one pair of signal pins comprises a first signal pin and a second signal pin; the pin state control unit comprises a first adjustable resistor, a second adjustable resistor, and a third adjustable resistor; wherein the first signal pin is connected to the second signal pin through the first adjustable resistor, the first signal pin is connected in series with the second adjustable resistor, and the second signal pin is connected in series with the third adjustable resistor.

4. The identification circuit of claim 3, wherein, the first state is a terminated state; in the case that the isolation transformer is a first type of transformer, the resistance value of the first adjustable resistor is infinite, the resistance values of the second adjustable resistor and the third adjustable resistor are both zero, and the first signal pin and the second signal pin are in a terminated state.

5. The identification circuit of claim 3, wherein, the second state is a short-circuit state; in the case that the isolation transformer is a second type of transformer, the resistance value of the first adjustable resistor is zero, the resistance values of the second adjustable resistor and the third adjustable resistor are both infinite, and the first signal pin and the second signal pin are in a short-circuit state.

6. The identification circuit of claim 3, wherein, the second state is an open-circuit state; in the case that the isolation transformer is a second type of transformer, the resistance values of the first adjustable resistor, the second adjustable resistor, and the third adjustable resistor are all infinite, and the first signal pin and the second signal pin are in an open-circuit state.

7. The identification circuit according to any one of claims 1 to 6, characterized in that, the first type of transformer is one of a gigabit transformer and a hundred-megabit transformer, and the second type of transformer is the other of the gigabit transformer and the hundred-megabit transformer.

8. The identification circuit according to any one of claims 1 to 6, characterized in that the SoC comprises a gigabit Ethernet physical layer (PHY) module, and the gigabit Ethernet PHY module is connected to the isolation transformer; wherein the at least one pair of signal pins are pins in the gigabit Ethernet PHY module; in the case that the gigabit Ethernet PHY module transmits data, the at least one pair of signal pins is in an idle state.

9. The identification circuit of claim 8, wherein: the gigabit Ethernet PHY module comprises an MDI0P pin, an MDI0N pin, an MDI1P pin, an MDI1N pin, an MDI2P pin, an MDI2N pin, an MDI3P pin, and an MDI3N pin. The MDI0P pin, the MDI0N pin, the MDI1P pin and the MDI1N pin are data transmission pins. The at least one pair of signal pins comprises an MDI2P pin, an MDI2N pin, an MDI3P pin and an MDI3N pin. In the case that the isolation transformer is a gigabit transformer, the MDI2P pin, the MDI2N pin, the MDI3P pin and the MDI3N pin are all in a termination state. In the case that the isolation transformer is a hundred-megabit transformer, the MDI2P pin, the MDI2N pin, the MDI3P pin and the MDI3N pin are all in a short-circuit state.

10. An Ethernet device, comprising: Comprise: The identification circuit of any one of claims 1-9. The identification circuit of any one of claims 1-9.

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