Edge computing system

Abstract

The utility model relates to the technical field of computing systems, in particular to an edge computing system and an edge computing system, the edge computing system comprises an information acquisition circuit, the information acquisition circuit comprises a signal amplification circuit, and the signal amplification circuit is used for amplifying signals received by the edge computing system; the crystal oscillator CO provides a stable clock signal for the information acquisition circuit, and ensures that each component in the information acquisition circuit can work synchronously; the input resistor R plays a role in limiting input current; the resistance of the balancing resistor R2 is equal to the resistance value of the balancing resistor R1 and the feedback resistor Rf which are connected in parallel, so that external resistors at the two input ends of the operational amplifier C are symmetrical, and the influence of input bias current and imbalance thereof is reduced; the operational amplifier C has the characteristics of high gain, high input impedance, low output impedance and the like, can amplify the input voltage signal, and improves the accuracy of information collection.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of computing system especially to an edge computing system. BACKGROUND

[0002] The offline part of edge computing usually refers to the ability of edge devices to perform data processing, storage, and analysis without internet connection. The background of offline processing technology usually involves the following key technical fields:

[0003] 1. Local data processing and computing

[0004] Data acquisition and preprocessing: Edge devices are usually equipped with sensors to collect data from the physical world. These data can be sensor data, video data, audio data, etc. In offline mode, these data are directly stored on the local device and preliminary processing and analysis are performed through embedded systems or microcontrollers.

[0005] Local analysis and decision-making: Some edge devices have certain computing capabilities and can perform local machine learning and artificial intelligence algorithms for data analysis and decision-making. For example, a smart camera may be able to recognize and analyze image content without transmitting video streams to the cloud for analysis.

[0006] Real-time requirements: The offline capabilities of edge computing platforms often need to handle high real-time requirement scenarios, such as real-time data analysis in automated production lines or real-time decision-making in autonomous driving systems.

[0007] 2. Embedded and edge computing devices

[0008] Hardware platform: The hardware of edge devices usually uses embedded processors, microcontrollers (MCU), single-board computers (such as Raspberry Pi, NVIDIA Jetson), or other edge computing dedicated devices (such as industrial PCs). The computing power of these devices is usually limited, but sufficient for local processing of certain tasks such as data preprocessing, lightweight machine learning inference, etc.

[0009] Low power consumption and real-time computing: Many edge devices require low power consumption in offline mode, especially in some energy-limited environments (such as remote sensors, drones, etc.). At the same time, edge computing needs to meet the requirements of low latency and high real-time, ensuring that the system can respond to various events or exceptions in a timely manner.

[0010] 3. Edge storage and data management

[0011] Local Storage: Edge computing devices often require some local storage capacity for caching and storing temporary data. For example, storage devices can be SD cards, solid-state drives (SSD), or specialized storage modules designed for edge applications such as flash memory. In offline mode, data can be stored locally until the device reconnects to the network or completes a predetermined local processing task.

[0012] Data Synchronization: The offline stored data of edge devices needs to be synchronized with cloud systems or other devices. In offline mode, edge devices usually upload local storage data or share processing results with other devices when network connectivity is restored.

[0013] Data Compression and Encryption: To reduce transmission bandwidth and ensure data security, edge devices may compress or encrypt offline processed data to ensure that data is not lost or leaked in offline state.

[0014] 4. Edge Artificial Intelligence and Machine Learning (AI / ML)

[0015] AI / ML models on edge devices: With the gradual improvement of the computing power of edge computing devices, many edge devices begin to embed or run machine learning models for intelligent analysis. These models are usually lightweight, such as compressed or optimized deep learning models, which can perform inference and decision-making on edge devices.

[0016] Offline inference: In the absence of network connection, edge devices can perform offline machine learning inference tasks. For example, sensors or camera devices may use trained AI models for image recognition, anomaly detection, predictive maintenance, etc., without the need to upload data to the cloud in real time.

[0017] Model update and transfer learning: Although edge devices can perform local inference in offline mode, in some cases, AI model updates need to rely on cloud training. Edge devices can periodically download and update new models offline, or use incremental learning techniques to perform partial learning and optimization locally.

[0018] 5. Data flow and message queue

[0019] Local message queue: In offline state, edge devices may accumulate a large amount of data, which will be stored in local message queue, waiting for subsequent synchronization or processing. In data flow systems, queues such as MQTT, Kafka are often used to ensure the order and reliability of data, especially in the case of network interruption.

[0020] Offline event triggers: Some systems may use offline event triggers for data processing, such as device state changes, sensor triggers, preset threshold exceedance, etc. Even without network connectivity, edge devices can still perform relevant operations based on local rule engines.

[0021] 6. Offline network protocols and standards

[0022] Low-Power Wide-Area Networks (LPWAN): Some edge computing devices may rely on low-power wide-area networks (such as LoRa, NB-IoT) for data transmission in offline states. These network protocols can help devices maintain some communication capabilities when the network is unstable, supporting remote data collection and transmission.

[0023] Device interconnection and local area network protocols: Some edge devices can communicate with other devices through local area networks (such as Wi-Fi, Bluetooth, Zigbee). This communication is usually a way of cooperation between devices in offline mode and does not depend on wide-area network connections.

[0024] 7. Fault tolerance and recovery mechanisms

[0025] Fault tolerance: Edge computing platforms need to have fault tolerance capabilities. Even if a device fails or has a fault during offline, the system should be able to automatically recover or switch to a backup mode to avoid data loss or system interruption.

[0026] Network outage recovery: When an edge device reconnects to the network, the system should be able to automatically resume operations, including data synchronization, device state updates, and communication with the cloud.

[0027] Most edge computing systems are prone to inaccurate data collection due to low voltage in the data collection circuit when collecting data. Utility model content

[0028] The main purpose of the utility model is to provide an edge computing system to solve the problem of low voltage in the data collection circuit affecting data collection accuracy in related technologies.

[0029] To achieve the above purpose, according to one aspect of the utility model, an edge computing system is provided, which comprises: an information collection circuit, the information collection circuit comprising a signal amplification circuit, the signal amplification circuit being used to amplify the signal received by the edge computing system.

[0030] Further, the information collection circuit further comprises a power supply component, a capacitor component, a resistor component, a crystal oscillator component, an operational amplifier component and a chip FP, the power supply component comprises a power supply, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, the capacitor component comprises a capacitor C5 and a capacitor C6, the resistor component comprises a resistor R1, a resistor R2, a resistor R3 and a resistor R4, the crystal oscillator component comprises a crystal oscillator CO, a capacitor C7 and a capacitor C8, and the operational amplifier component comprises an operational amplifier A and an operational amplifier B.

[0031] Further, the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 are connected in parallel, one end of the capacitor C1 and the capacitor C2 is connected to the positive pole of the power supply, and the other end is grounded, one end of the capacitor C3 and the capacitor C4 is connected to the negative pole of the power supply, and the other end is grounded, and the capacitor C5 and the capacitor C6 are connected in parallel, one end of the capacitor C5 and the capacitor C6 is connected to the pin DV of the chip FP, and the other end is grounded.

[0032] Further, the positive power supply pin V+ of the operational amplifier A is connected to the positive pole of the power supply, and the negative power supply pin V- is connected to the negative pole of the power supply, the non-inverting input pin +IN of the operational amplifier A is connected to the resistor R2 and the resistor R3, the inverting input pin -IN is connected to the pin REF of the chip FP, the offset null pin ON of the operational amplifier A is connected to the pin AGN of the chip FP, the non-inverting input pin +IN of the operational amplifier B is connected to the resistor R1 and the resistor R2, the inverting input pin -IN is connected to the pin AVdd of the chip FP, the offset null pin ON of the operational amplifier B is connected to the pin IFP of the chip FP, the resistor R1 is connected to the positive pole of the power supply, and the resistor R4 is connected in series with the resistor R3 and connected to the negative pole of the power supply.

[0033] Further, the fixed pin of the capacitor C7 and the capacitor C8 is connected in series with the crystal oscillator CO, and the moving pin is grounded, the input pin of the crystal oscillator CO is connected to the pin MCI of the chip FP, and the output pin is connected to the pin MCO of the chip FP.

[0034] Further, the signal amplification circuit comprises an operational amplifier C, an input resistor R, a feedback resistor Rf, a balance resistor R1 and a balance resistor R2, an input signal UL is connected to the non-inverting input terminal U+ of the operational amplifier C through the input resistor R, the feedback resistor Rf is connected between the output terminal U0 and the inverting input terminal U- of the operational amplifier C, one end of the balance resistor R1 is connected to the inverting input terminal U- of the operational amplifier C, and the other end is grounded, and one end of the balance resistor R2 is connected to the non-inverting input terminal U+ of the operational amplifier C, and the other end is grounded.

[0035] Compared with the prior art, the utility model has following beneficial effect: the partial pressure circuit that resistance R1 and resistance R2 constitute provides bias voltage for operational amplifier B, the partial pressure circuit that resistance R3 and resistance R4 constitute sets up amplification multiple for operational amplifier A;Capacitor C1, capacitor C2, capacitor C3 and capacitor C4 are used to filter and stabilize power supply voltage, reduce the interference of power supply noise to information acquisition circuit;Crystal oscillator CO provides stable clock signal for information acquisition circuit, ensures that each partial component of information acquisition circuit can work synchronously;Input resistance R plays the role of limiting input current;The resistance size of balance resistance R2 is equal to the resistance value of balance resistance R1 and feedback resistance Rf in parallel, makes the external resistance of two input ends of operational amplifier C symmetry, to reduce the influence of input bias current and its unbalance;Operational amplifier C has high gain, high input impedance and low output impedance etc. BRIEF DESCRIPTION OF DRAWINGS

[0036] Fig. 1 It is information acquisition circuit diagram for the utility model;

[0037] Fig. 2 It is signal amplification circuit diagram for the utility model. DETAILED DESCRIPTION

[0038] For further illustrating the technical means and effects that the utility model takes to realize the predetermined utility model purposes, the following combines the drawings and the preferred embodiments, and the specific implementation, structure, features and effects according to the utility model are described in detail as follows.

[0039] Please refer to Figs. 1-2 The embodiment provides an edge computing system, which comprises an information acquisition circuit, and the information acquisition circuit comprises a signal amplification circuit, and the signal amplification circuit is used for amplifying signals received by the edge computing system.

[0040] The information acquisition circuit further comprises a power supply component, a capacitor component, a resistance component, a crystal oscillator component, an operational amplifier component and a chip FP, the power supply component comprises a power supply, capacitor C1, capacitor C2, capacitor C3 and capacitor C4, the capacitor component comprises capacitor C5 and capacitor C6, the resistance component comprises resistance R1, resistance R2, resistance R3 and resistance R4, the crystal oscillator component comprises a crystal oscillator CO, capacitor C7 and capacitor C8, and the operational amplifier component comprises an operational amplifier A and an operational amplifier B.

[0041] The resistance R1, the resistance R2, the resistance R3 and the resistance R4 are used in cooperation with the operational amplifier A and the operational amplifier B to set the gain and other parameters of the operational amplifier A and the operational amplifier B, the voltage dividing circuit composed of the resistance R1 and the resistance R2 provides a bias voltage for the operational amplifier B, the voltage dividing circuit composed of the resistance R3 and the resistance R4 sets the amplification multiple of the operational amplifier A, the operational amplifier A amplifies the voltage signal of the chip FP analog output end AGN, and the operational amplifier B amplifies the voltage signal of the chip FP analog output end I FP.

[0042] The capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 are all in parallel, one end of the capacitor C1 and the capacitor C2 is connected with the positive electrode of the power supply, and the other end is grounded, one end of the capacitor C3 and the capacitor C4 is connected with the negative electrode of the power supply, and the other end is grounded, the capacitor C5 and the capacitor C6 are in parallel, one end of the capacitor C5 and the capacitor C6 is connected with the pin DV of the chip FP, and the other end is grounded, and the capacitor C5 and the capacitor C6 are used for filtering or stabilizing the voltage in the information acquisition circuit.

[0043] The voltage of the power supply is 5V, which provides working voltage for the information acquisition circuit and ensures that each component works in the normal voltage range.

[0044] The capacitance of the capacitor C1 and the capacitor C3 is 10uF, and the capacitance of the capacitor C2 and the capacitor C4 is 104 (i.e. 0.1uF), the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 are used for filtering and stabilizing the power supply voltage, reducing the interference of power supply noise on the information acquisition circuit.

[0045] The positive power supply pin V+ of the operational amplifier A is connected with the positive electrode of the power supply, and the negative power supply pin V- is connected with the negative electrode of the power supply, the non-inverting input pin +IN of the operational amplifier A is connected with the resistance R2 and the resistance R3, and the inverting input pin -IN is connected with the pin REF of the chip FP, the offset null pin ON of the operational amplifier A is connected with the pin AGN of the chip FP, the non-inverting input pin +IN of the operational amplifier B is connected with the resistance R1 and the resistance R2, and the inverting input pin -IN is connected with the pin AVdd of the chip FP, the offset null pin ON of the operational amplifier B is connected with the pin I FP of the chip FP, the resistance R1 is connected with the positive electrode of the power supply, and the resistance R4 is connected in series with the resistance R3 and connected with the negative electrode of the power supply.

[0046] The fixed pin of the capacitor C7 and the capacitor C8 is connected in series with the crystal oscillator CO, and the moving pin is grounded, the input pin of the crystal oscillator CO is connected with the pin MCI of the chip FP, and the output pin is connected with the pin MCO of the chip FP.

[0047] Capacitor C7 and capacitor C8 filter and stabilize the crystal oscillator CO, so that the crystal oscillator CO can work at its nominal frequency stably, and the crystal oscillator CO provides a stable clock signal for the information acquisition circuit, and ensures that each part of the information acquisition circuit can work synchronously.

[0048] The signal amplification circuit comprises an operational amplifier C, an input resistor R, a feedback resistor Rf, a balance resistor R1 and a balance resistor R2, the input signal UL is connected with the non-inverting input terminal U+ of the operational amplifier C through the input resistor R, the feedback resistor Rf is connected between the output terminal U0 and the inverting input terminal U- of the operational amplifier C, one end of the balance resistor R1 is connected with the inverting input terminal U- of the operational amplifier C, and the other end is grounded, one end of the balance resistor R2 is connected with the non-inverting input terminal U+ of the operational amplifier C, and the other end is grounded.

[0049] The operational amplifier C has the characteristics of high gain, high input impedance and low output impedance, and can amplify the input signal; the input resistor R plays a role in limiting the input current; the resistance of the balance resistor R2 is equal to the resistance value of the balance resistor R1 and the feedback resistor Rf in parallel, so that the external resistors of the two input terminals of the operational amplifier C are symmetrical, so as to reduce the influence of the input bias current and its offset.

[0050] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical scheme of the present application. Any modification, equivalent change and modification of the above embodiments, which does not depart from the technical scheme of the present application, is still within the scope of the present application.

Claims

1. An edge computing system, characterized by, The information acquisition circuit comprises a signal amplification circuit for amplifying the signal received by the edge computing system. The signal amplification circuit comprises an operational amplifier C, an input resistor R, a feedback resistor Rf, a balance resistor R1 and a balance resistor R2, an input signal UL is connected to the non-inverting input terminal U+ of the operational amplifier C through the input resistor R, the feedback resistor Rf is connected between the output terminal U0 and the inverting input terminal U- of the operational amplifier C, one end of the balance resistor R1 is connected to the inverting input terminal U- of the operational amplifier C, and the other end is grounded, one end of the balance resistor R2 is connected to the non-inverting input terminal U+ of the operational amplifier C, and the other end is grounded. The information acquisition circuit further comprises a power supply component, a capacitor component, a resistor component, a crystal oscillator component, an operational amplifier component and a chip FP, the power supply component comprises a power supply, capacitors C1, C2, C3 and C4, the capacitor component comprises capacitors C5 and C6, the resistor component comprises resistors R1, R2, R3 and R4, the crystal oscillator component comprises a crystal oscillator CO, capacitors C7 and C8, and the operational amplifier component comprises operational amplifiers A and B.

2. The edge computing system of claim 1, wherein, The capacitors C1, C2, C3 and C4 are connected in parallel, one end of each of the capacitors C1 and C2 is connected to the positive electrode of the power supply, and the other end is grounded, one end of each of the capacitors C3 and C4 is connected to the negative electrode of the power supply, and the other end is grounded, the capacitors C5 and C6 are connected in parallel, one end of each of the capacitors C5 and C6 is connected to the pin DV of the chip FP, and the other end is grounded.

3. The edge computing system of claim 2, wherein, The positive power supply pin V+ of the operational amplifier A is connected to the positive electrode of the power supply, the negative power supply pin V- is connected to the negative electrode of the power supply, the non-inverting input pin +IN of the operational amplifier A is connected to the resistors R2 and R3, the inverting input pin -IN is connected to the pin REF of the chip FP, and the offset null pin ON is connected to the pin AGN of the chip FP.

4. The edge computing system of claim 3, wherein, The non-inverting input pin +IN of the operational amplifier B is connected to the resistors R1 and R2, the inverting input pin -IN is connected to the pin AVdd of the chip FP, the offset null pin ON is connected to the pin I FP of the chip FP, the resistor R1 is connected to the positive electrode of the power supply, and the resistor R4 is connected in series with the resistor R3 and connected to the negative electrode of the power supply.

5. The edge computing system of claim 4, wherein, The fixed pin of the capacitors C7 and C8 is connected in series with the crystal oscillator CO, and the moving pin is grounded, the input pin of the crystal oscillator CO is connected to the pin MCI of the chip FP, and the output pin is connected to the pin MCO of the chip FP.

6. The edge computing system of claim 5, wherein, ​

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