Symmetrical double-base-island packaging frame

Abstract

The utility model relates to the technical field of integrated circuit packaging, and discloses a symmetrical double-base-island packaging frame, which comprises a first base island and a second base island, two first bonding pads are arranged on a first side part of the first base island, a second bonding pad and a third bonding pad are arranged on a second side part of the first base island, and the second bonding pad and the third bonding pad are arranged on a second side part of the second base island. The size of the third bonding pad is larger than that of the second bonding pad. The first side portion of the second base island is provided with two fourth bonding pads, the second side portion of the second base island is provided with a fifth bonding pad and a sixth bonding pad, and the size of the sixth bonding pad is larger than that of the fifth bonding pad. Compared with the prior art, the improvement enhances the visual features (size features) of the symbolic pads (the third pad and the sixth pad), so that a visual inspection device can better identify obviously different pads in a seal printing process, the condition of identification errors is reduced, the risk of direction indication errors is avoided, and the printing quality of the seal is improved. And therefore, the condition that the printing position of the seal is staggered due to wrong indication is reduced.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit packaging technology, and in particular relates to a symmetrical dual-base island packaging framework. Background Technology

[0002] With the increasing demand for digital electronic products and the advancement of chip processing technology, integrated circuit production has entered a mass production stage, and the pursuit of smaller size, higher stability, and higher quality has become the focus. An integrated circuit consists of a wireframe, a chip, and a molding compound. Commonly used SOP (Small Out-Line Package) frames are mostly single-island structures, supporting only one or two chips of the same polarity. If multiple chips of different polarities need to be packaged, the base island needs to be enlarged, additional packaging devices and external interconnects required. This not only increases costs but also makes the integrated circuit board structure more complex, making it difficult to meet the demands for high integration and high stability.

[0003] In the prior art, there is an SOP8 dual-base island package frame. Although this frame overcomes the defects of the single-base island frame, the eight pads in the frame are exactly the same, and the visual features are not obvious. This makes it easy for pin identification (usually identified by visual inspection equipment) errors to occur in the stamp printing process after the package is formed, resulting in incorrect orientation indication. This indication error will cause the stamp printing position to be misaligned, which in turn misleads the subsequent quality inspection process. Utility Model Content

[0004] This invention provides a symmetrical dual-base island packaging frame to solve the problem of pin identification errors that easily occur in the stamp printing process after packaging in the prior art.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A symmetrical dual-base island package frame includes a first base island and a second base island. The first base island has two first pads on its first side and a second pad and a third pad on its second side, with the third pad being larger than the second pad. The second base island has two fourth pads on its first side and a fifth pad and a sixth pad on its second side, with the sixth pad being larger than the fifth pad.

[0007] Through the above technical solution, compared with the traditional uniform standard pad size design, the packaging frame of this utility model adjusts the size of the third and sixth pads, making the third pad significantly larger than the second pad, and the sixth pad significantly larger than the fifth pad. These improvements enhance the visual characteristics of the marker pads (the third and sixth pads), enabling visual inspection equipment in the stamp printing process to better identify distinctly different pads, reducing identification errors, avoiding the risk of directional indication errors, and thus reducing the potential for misaligned stamp printing due to incorrect indication.

[0008] Preferably, the first base island is rotationally symmetrical with respect to the second base island, with the geometric center of the symmetrical dual-base island packaging frame as the rotation center.

[0009] Through the above technical solution, the first and second base islands are rotationally symmetrical. This structural design also makes the third and sixth pads rotationally symmetrical, which helps to increase the spacing between the "large pads" and effectively avoids the risk of solder bridging caused by adjacent "large pads" during the chip soldering process. In addition, the rotationally symmetrical structural solution facilitates industrial reproduction and production, improving production efficiency.

[0010] Furthermore, the third pad is located on the opposite side of the sixth pad.

[0011] By using the above technical solution, placing the third pad on the opposite side of the sixth pad can also increase the spacing between the third and sixth pads, thereby reducing the possibility of solder bridging caused by the small spacing between the "large pads".

[0012] Furthermore, the third and sixth pads are located at the two diagonal ends of the symmetrical dual-base island package frame.

[0013] With the above technical solution, the third and sixth pads are located at the two opposite ends of the packaging frame of this utility model, which maximizes the spacing between the two "large pads" and avoids the possibility of solder bridging caused by the small spacing between the "large pads". On this basis, the two opposite ends are the outer periphery of the entire frame. After the chip is soldered and packaged, the two "large pads" will not be completely covered by the chip or pins themselves. This is beneficial for visual inspection equipment to better identify the pads and the pins on the pads, and reduces the occurrence of pin identification errors.

[0014] Preferably, the device further includes a first chip and a second chip, wherein the drain pin of the first chip is connected to a first pad, the gate pin of the first chip is connected to a second pad, and the source pin of the first chip is connected to a third pad; the drain pin of the second chip is connected to a fourth pad, the gate pin of the second chip is connected to a fifth pad, and the source pin of the second chip is connected to a sixth pad.

[0015] With the above technical solution, if the packaging framework of this utility model is applied to the chip spot welding process, the first base island will spot weld the first chip through the above connection method, and the second base island will spot weld the second chip through the above connection method. Utilizing the characteristics of enlarged pads (the third and sixth pads) and the above connection structure, a certain degree of lateral offset during chip spot welding on the base island is allowed. This can relax the visual offset recognition standard while ensuring product quality, reduce the false detection rate of quality control visual inspection, and improve the efficiency of the quality control process.

[0016] Preferably, the packaging structure of the first chip and the second chip is any one of SOP3, SOP4 or SOP8.

[0017] SOP stands for Small Out-Line Package, and the packaging structure of this utility model has strong versatility. Specifically, the chip types that can be spot-welded with two base islands are mainly SOP3, SOP4, or SOP8, which are basically applicable to the soldering of most packaged chips on the market.

[0018] Preferably, if the first chip and the second chip are SOP8, the multiple sources of the first chip are connected to the third pad, and the multiple sources of the second chip are connected to the sixth pad.

[0019] With the above technical solution, when the first chip and the second chip are SOP8, the source is generally used to connect to the same signal source or power supply. These two chips usually have multiple sources. By taking advantage of the size of the "large pad", it is possible to connect multiple sources on the same side of the chip to the same pad. This makes the source solder joints connected to the same pad have the same impedance and the same current, which greatly improves the stability of the SOP8 chip power supply.

[0020] Preferably, the first chip and the second chip are any one of N-channel MOSFET, P-channel MOSFET, enhancement-mode MOSFET, depletion-mode MOSFET, and dual-enhancement MOSFET.

[0021] Through the above technical solution, the packaging framework of this utility model is applicable to the packaging of almost all MOSFET chips and has strong universality.

[0022] The beneficial effects of this utility model are:

[0023] 1. Compared to existing technologies, the packaging frame of this utility model adjusts the dimensions of the third and sixth pads, making the third pad significantly larger than the second pad, and the sixth pad significantly larger than the fifth pad. These improvements enhance the visual characteristics of the identifying pads (the third and sixth pads), enabling visual inspection equipment in the stamp printing process to better identify distinctly different pads and the pins connecting them, reducing pin identification errors and mitigating the risk of incorrect orientation indication.

[0024] 2. Compared with the prior art, the present invention rotates the first base island and the second base island in a symmetrical manner. This structural design makes the third pad and the sixth pad rotate in a symmetrical manner, which is beneficial to increase the spacing between the "large pads" and effectively avoids the risk of solder bridging caused by the proximity of the "large pads" in the chip soldering process.

[0025] 3. Compared with existing technologies, the size advantage of the "large pad" makes it possible to connect multiple sources on the same side of the chip to the same pad, thereby making the source solder joints connected to the same pad have the same impedance and the same current, which greatly improves the stability of the power supply of the SOP8 chip. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the symmetrical dual-base island packaging frame in Embodiment 1 of this utility model;

[0027] Figure 2 This is a schematic diagram of the connection after spot welding SOP8 chips to the symmetrical dual-base island packaging frame in Embodiment 2 of this utility model;

[0028] Figure 3 This is a schematic diagram of the connection after spot welding the SOP3 chip to the symmetrical dual-base island packaging frame in Embodiment 3 of this utility model;

[0029] Figure 4 This is a schematic diagram of the connection after spot welding SOP4 chips to the symmetrical dual-base island packaging frame in Embodiment 4 of this utility model.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1. First base island; 11. First pad; 12. Second pad; 13. Third pad;

[0032] 2. Second base island; 21. Fourth pad; 22. Fifth pad; 23. Sixth pad;

[0033] 4. First chip;

[0034] 5. Second chip. Detailed Implementation

[0035] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0036] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0037] This embodiment discloses a symmetrical dual-base island packaging frame to solve the problem of pin identification errors that easily occur in the stamp printing process after packaging in the prior art.

[0038] Example 1

[0039] like Figure 1 As shown, this embodiment discloses a symmetrical dual-base island package frame, including a first base island 1 and a second base island 2. The first base island 1 has two first pads 11 on its first side, and a second pad 12 and a third pad 13 on its second side, with the third pad 13 being larger than the second pad 12. The second base island 2 has two fourth pads 21 on its first side, and a fifth pad 22 and a sixth pad 23 on its second side, with the sixth pad 23 being larger than the fifth pad 22.

[0040] Through the above structural design, the package frame of this embodiment adjusts the dimensions of the third pad 13 and the sixth pad 23, making the third pad 13 significantly larger than the second pad 12, and the sixth pad 23 significantly larger than the fifth pad 22. Compared with the prior art, the above improvement enhances the visual characteristics of the landmark pads, namely the third pad 13 and the sixth pad 23, enabling the visual inspection equipment in the stamp printing process to better identify the pads and the pins on the pads, reducing the occurrence of pad and pin identification errors, avoiding the risk of directional indication errors, and thus reducing the possibility of stamp printing position misalignment due to indication errors.

[0041] More specifically, the two first pads 11 are pad P7 and pad P8, which are spaced apart and have the same polarity. The second pad 12 is pad P2, and the third pad 13 is pad P3, which are spaced apart and have different polarities. The two fourth pads 21 are pad P3 and pad P4, which are spaced apart and have the same polarity. The fifth pad 22 is pad P6, and the sixth pad 23 is pad P5, which are spaced apart and have different polarities. The above structural distribution defines the packaging frame of this utility model to facilitate the differentiation of the pads.

[0042] In this embodiment, the planar projections of the third pad 13 and the sixth pad 23 are rectangular to facilitate circuit board printing and frame space planning. In other embodiments, the planar projections of the third pad 13 and the sixth pad 23 can be circular, fan-shaped, rhomboid, or other shapes to suit different application scenarios.

[0043] In this embodiment, the third pad 13 and the sixth pad 23 are the same size. The third pad 13 is the same width as the second pad 12, but its length is 3-4 times that of the second pad 12. In other embodiments, the size of the pads can be adjusted according to actual conditions to suit different application environments.

[0044] It should be explained that "large pads" require more solder when spot welding and have higher requirements for welding temperature compared to small pads. If two "large pads" are placed next to each other and welded using the same process parameters as small pads, solder bridging will occur, meaning the solder on the two "large pads" will connect. This can lead to short circuits in subsequent testing processes and damage to the packaged chip.

[0045] In order to overcome the above-mentioned technical difficulties, in this embodiment, the third pad 13 and the sixth pad 23 are arranged opposite to each other, that is, the third pad 13 is located on the opposite side of the sixth pad 23.

[0046] The above structural design increases the spacing between the third pad 13 and the sixth pad 23, reducing the possibility of solder bridging caused by the small spacing between the two "large pads".

[0047] Furthermore, the first base island 1 is rotationally symmetrical with respect to the geometric center of the encapsulation frame in this embodiment and the second base island 2.

[0048] Preferably, the rotational symmetry angle is 180°.

[0049] Through the above structural design, the first base island 1 and the second base island 2 are rotationally symmetrical, which in turn makes the third pad 13 and the sixth pad 23 rotationally symmetrical. This facilitates further increasing the spacing between the "large pads" and effectively avoids the risk of solder bridging caused by the adjacency of the "large pads". In addition, this standardized structural design is more conducive to mass production.

[0050] Furthermore, to maximize the spacing between the two "large pads" and minimize the possibility of solder bridging caused by insufficient spacing, the third pad 13 and the sixth pad 23 in this embodiment are located at opposite corners of the symmetrical dual-base island package frame. Besides avoiding solder bridging, placing the two "large pads" on the periphery of the frame means that even after the base islands have completed the spot welding and packaging of the corresponding chips, a small section of the third pad 13 and the sixth pad 23 will still be exposed. This allows visual inspection equipment to better identify the pads and the pins on them, reducing the likelihood of pin identification errors.

[0051] The working principle of this utility model embodiment is as follows:

[0052] By increasing the size of the third pad 13 and the sixth pad 23, and combining the 180° rotational symmetry structure design of the dual-base island, the visual characteristics of these two pads are enhanced, enabling the visual inspection equipment in the stamp printing process to better identify the pads and the pins on the pads, reducing the occurrence of pin identification errors, avoiding the risk of incorrect direction indication, and thus reducing the possibility of misaligned stamp printing positions due to incorrect indication.

[0053] Example 2

[0054] like Figure 1 and Figure 2 As shown, based on Embodiment 1, the symmetrical dual-base island packaging framework of this embodiment also includes a first chip 4 and a second chip 5.

[0055] Specifically, the drain pin of the first chip 4 is connected to the first pad 11, the gate pin of the first chip 4 is connected to the second pad 12, and the source pin of the first chip 4 is connected to the third pad 13. The drain pin of the second chip 5 is connected to the fourth pad 21, the gate pin of the second chip 5 is connected to the fifth pad 22, and the source pin of the second chip 5 is connected to the sixth pad 23.

[0056] With the above structural design, if the packaging framework of this utility model is applied to the chip spot welding process, the first base island 1 will spot weld the first chip 4 through the above connection method, and the second base island 2 will spot weld the second chip 5 through the above connection method. Utilizing the characteristics of the "large solder pad" and the above connection structure, a certain degree of lateral offset during chip spot welding on the base island is allowed without affecting the product quality after spot welding. This provides structural support for relaxing visual offset recognition standards, which is beneficial for reducing the false detection rate of visual inspection and improving the efficiency of the quality control process.

[0057] In this embodiment, the first chip 4 and the second chip 5 can be any one of an N-channel MOSFET, a P-channel MOSFET, an enhancement-mode MOSFET, a depletion-mode MOSFET, or a dual-enhancement MOSFET. The symmetrical dual-base island package frame of this embodiment is a universal frame that can be applied to the spot welding and packaging of almost all MOSFET chips.

[0058] In this embodiment, Figure 2 Both the first chip 4 and the second chip 5 provided are SOP8 packages, each with 8 pins. The three sources of the first chip 4 are connected to the third pad 13, while the three sources of the second chip 5 are connected to the sixth pad 23.

[0059] It should be explained that SOP stands for Small Out-Line Package. In SOP8 packaged chips, the source pins are generally used to connect to the same signal source or power supply, and the three source pins of two SOP8 chips are located on the same side.

[0060] Through the above structural design, this embodiment utilizes the size advantage of the "large pad" to make it possible to connect multiple source electrodes on the same side of the chip to the same pad. This results in the source solder joints connected to the same pad having the same impedance and the same current, which greatly improves the stability of the SOP8 chip power supply.

[0061] Example 3

[0062] like Figure 1 and Figure 3 As shown, unlike Embodiment 2, the packaging structure of the first chip 4 and the second chip 5 in this embodiment is SOP3, that is, each chip has three pins.

[0063] In this configuration, the drain pin of the first chip 4 is connected to any one of the first pads 11, the gate pin of the first chip 4 is connected to the second pad 12, and the source pin of the first chip 4 is connected to the third pad 13. The drain pin of the second chip 5 is connected to any one of the fourth pads 21, the gate pin of the second chip 5 is connected to the fifth pad 22, and the source pin of the second chip 5 is connected to the sixth pad 23.

[0064] When the package structure of the first chip 4 and the second chip 5 is SOP3, it also has a gate, drain and source. Unlike the SOP8 package structure, although SOP3 is smaller in size (not shown in the figure), it utilizes the characteristics of "large pads", that is, it allows a certain degree of left and right offset of the soldering, so that the chip of the SOP3 package structure can also be spot soldered in the symmetrical dual-base island package frame provided in this embodiment.

[0065] Example 4

[0066] like Figure 1 and Figure 4 As shown, unlike Embodiment 2, the packaging structure of the first chip 4 and the second chip 5 in this embodiment is SOP4, that is, each chip has four pins.

[0067] In this configuration, the two drain pins of the first chip 4 are located on the same side and connected to the corresponding first pad 11, the gate pin of the first chip 4 is connected to the second pad 12, and the source pin of the first chip 4 is connected to the third pad 13. Similarly, the two drain pins of the second chip 5 are located on the same side and connected to the corresponding fourth pad 21, the gate pin of the second chip 5 is connected to the fifth pad 22, and the source pin of the second chip 5 is connected to the sixth pad 23.

[0068] When the package structure of the first chip 4 and the second chip 5 is SOP4, it also has a gate, drain and source. The SOP4 chip can be directly spot-welded onto the corresponding pads to realize the spot welding of the SOP4 chip.

[0069] In other embodiments, the chip packages disposed on the first base island 1 and the second base island 2 may be different to adapt to different application environments.

[0070] The above are all preferred embodiments of this utility model, and are not intended to limit the scope of protection of this utility model. Therefore, all equivalent changes made to the structure, shape and principle of this utility model should be covered within the scope of protection of this utility model.

Claims

1. A symmetric dual-die island package frame, comprising: The package structure comprises a first base island (1) and a second base island (2), the first side of the first base island (1) is provided with two first pads (11), the second side of the first base island (1) is provided with one second pad (12) and one third pad (13), the size of the third pad (13) is larger than that of the second pad (12); the first side of the second base island (2) is provided with two fourth pads (21), the second side of the second base island (2) is provided with one fifth pad (22) and one sixth pad (23), the size of the sixth pad (23) is larger than that of the fifth pad (22).

2. The symmetric dual-die island package frame of claim 1, wherein, The first base island (1) is rotationally symmetrical with the second base island (2) with the geometric center of the symmetrical double-base island package frame as the rotation center.

3. The symmetric dual-die island package frame of claim 1, wherein, The third pad (13) is located on the opposite side of the sixth pad (23).

4. The symmetric dual-die island package frame of claim 1, wherein, The third pad (13) and the sixth pad (23) are located at two opposite corners of the symmetrical double-base island package frame, respectively.

5. The symmetric dual-die island package frame of claim 1, wherein, The package structure further comprises a first chip (4) and a second chip (5), the drain pin of the first chip (4) is connected to the first pad (11), the gate pin of the first chip (4) is connected to the second pad (12), and the source pin of the first chip (4) is connected to the third pad (13); the drain pin of the second chip (5) is connected to the fourth pad (21), the gate pin of the second chip (5) is connected to the fifth pad (22), and the source pin of the second chip (5) is connected to the sixth pad (23).

6. The symmetric dual-die island package frame of claim 5, wherein, The package structure of the first chip (4) and the second chip (5) is any one of SOP3, SOP4 or SOP8.

7. The symmetric dual-die island package frame of claim 5, wherein, If the first chip (4) and the second chip (5) are SOP8, the multiple source pins of the first chip (4) are connected to the third pad (13), and the multiple source pins of the second chip (5) are connected to the sixth pad (23).

8. The symmetric dual-die island package frame of claim 5, wherein, The first chip (4) and the second chip (5) are any one of N-channel MOSFET, P-channel MOSFET, enhancement mode MOSFET, depletion mode MOSFET and double enhancement mode MOSFET.

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