Open-loop and closed-loop mode selection circuit for capacitive negative-voltage charge pump

Abstract

The utility model discloses an open-loop and closed-loop mode selection circuit for a capacitive negative voltage charge pump, which comprises a soft start and reference voltage signal generation circuit, a mode control circuit, a differential operational amplifier circuit and a driving voltage adjustable driving circuit, an enable signal end of the soft start and reference voltage generation circuit is externally connected with an excitation signal of an external drive, a signal output end of the soft start and reference voltage generation circuit is connected with the mode control circuit, and the mode control circuit generates a logic signal and feeds back the logic signal to the soft start and reference voltage generation circuit. Meanwhile, a soft start signal and a feedback signal are selected according to a system working mode and then are sequentially transmitted to the differential operational amplifier circuit and the driving voltage adjustable driving circuit, and the output end of the driving voltage adjustable driving circuit is in control connection with a grid electrode of a third switching power tube in the charge pump circuit. The charge pump circuit is simultaneously suitable for open-loop and closed-loop modes, and can be suitable for different working scenes. The utility model is suitable for the capacitive negative voltage charge pump circuit in any one of the open-loop mode and the closed-loop mode.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of integrated circuit, and relates to the start of chip power supply in integrated circuit, in particular to an open and closed loop mode selection circuit for capacitive negative voltage charge pump. BACKGROUND

[0002] In recent years, with the continuous development of integrated circuits, the application of TFT-LCD is also more and more extensive. In order to generate the required power supply voltage of TFT-LCD, the charge pump circuit is one of the keys. The output ripple, current capacity, adjustment precision and stability of the charge pump directly affect the picture quality of TFT-LCD. Therefore, the current domestic and foreign scholars are also in full swing for the research of charge pump. Based on the consideration of low power consumption, low cost and low EMI, the application of charge pump in integrated circuit is more and more extensive.

[0003] The charge pump is a DC / DC voltage conversion circuit, which is an important driving component in electronic circuits, and is widely used in power supply circuits of integrated circuits in various fields. The principle of charge pump is to use the charging and discharging of capacitor to realize the voltage rise. In practical application, the charge pump can output negative voltage from positive voltage, that is, positive to negative charge pump; or increase the size of input voltage even doubled. At present, the commonly used charge pump circuit in circuit design is positive to negative charge pump, and its circuit principle is shown in Figure 1 The core of the circuit is fast capacitor CFKY, input capacitor CIN, output capacitor COUT, and inverter U and first to fourth switches S1-S4, wherein the first to fourth switches S1-S4 are switch power tubes, and their off and on are controlled by the periodically changing square wave signal input in front of the charge pump and the inverter U. The switch state always appears in pairs, that is, the opening and closing of the first switch S1 and the second switch S2 are consistent, and the opening and closing of the third switch S3 and the fourth switch S4 are consistent. When the input in the current stage is high, the first switch S1 and the second switch S2 are closed, and the third switch S3 and the fourth switch S4 are opened. The input voltage charges the fast capacitor CFKY, and when the input in the current stage is low, the first switch S1 and the second switch S2 are opened, and the third switch S3 and the fourth switch S4 are closed. The fast capacitor CFKY discharges the output capacitor COUT, and so on.

[0004] At present, most of the negative voltage charge pump chips on the market work in an open loop system, that is, only the voltage VIN can be input, and the output voltage is -VIN, and the output voltage will change with the change of the load current. However, with the rapid development of large-scale integrated circuits, the requirement for power supply precision is higher and higher, and the requirement for the precision of negative voltage charge pump is also higher and higher. Such chips cannot meet the needs of applications requiring high-precision negative voltage, and the output voltage cannot be freely set, which is limited in many application scenarios and has poor versatility. In order to solve the problem of unadjustable output voltage, some charge pumps work in a closed loop system, and the output voltage of the charge pump can be adjusted through the feedback resistor. Although the design of such charge pumps can solve the problem of unadjustable output voltage, the application scenarios are relatively single, and cannot meet the use requirements of various application scenarios. Therefore, it is urgent to design a new circuit to meet the requirements of adjustable output voltage, output voltage not changing with load current, few peripheral devices, low ripple and easy integration. Content of the utility model

[0005] The utility model discloses a kind of open, closed loop mode selection circuit for capacitive negative voltage charge pump, to realize corresponding selection open loop mode or closed loop mode under different application scenarios.

[0006] In order to achieve the above purpose, the technical scheme adopted by the utility model is: an open, closed loop mode selection circuit for capacitive negative voltage charge pump, including the soft start and reference voltage signal generation circuit that provides soft start voltage from high to low, mode control circuit, differential operational amplifier circuit, drive voltage adjustable drive circuit, the enable signal end of the soft start and reference voltage generation circuit is connected with the excitation signal of external drive, the soft start signal and two reference voltage signals generated by it are connected mode control circuit respectively, the mode control circuit generates logic signal feedback to the soft start and reference voltage generation circuit by detecting the value of feedback signal, while mode control circuit sequentially sends soft start signal and feedback signal to differential operational amplifier circuit and drive voltage adjustable drive circuit according to system operation mode, and the output end of the drive voltage adjustable drive circuit is connected to the gate of the third switch power tube in charge pump circuit.

[0007] As the limitation of the soft start and reference voltage signal generation circuit in the utility model: the soft start and reference voltage signal generation circuit includes soft start voltage signal generation circuit and reference voltage signal generation circuit, wherein the soft start voltage signal generation circuit and the reference voltage signal generation circuit are connected in parallel, and the input end of the first inverter is used as the enable signal end of the open, closed loop mode selection circuit for capacitive negative voltage charge pump.

[0008] As the limitation of the soft start voltage signal generating circuit in the utility model: the soft start voltage signal generating circuit includes first N channel field effect tube, first P channel field effect tube, first Smith inverter, second inverter, the output end of the first inverter is connected with the grid of first N channel field effect tube, the drain of first N channel field effect tube is connected with the grid of first P channel field effect tube through first Smith inverter and second inverter, the drain of first P channel field effect tube is used as the feedback signal input end of the open and closed loop mode selection circuit for capacitive negative voltage charge pump, and the source thereof outputs soft start voltage;The source of first N channel field effect tube and first P channel field effect tube is grounded.

[0009] As the limitation of the reference voltage signal generating circuit in the utility model: the reference voltage signal generating circuit includes third inverter, second N channel field effect tube, second P channel field effect tube, third P channel field effect tube, resistance network formed by first resistance to fourth resistance, the signal output end of the first inverter is connected with the grid of second P channel field effect tube and third P channel field effect tube respectively, the source of second P channel field effect tube is connected with the series connection circuit of first resistance and second resistance, the source of third P channel field effect tube is connected with the series connection circuit of third resistance and fourth resistance, and the series connection circuit of first resistance and second resistance is connected with the series connection circuit of third resistance and fourth resistance in parallel.

[0010] The grid of second N channel field effect tube is connected with third inverter or or gate in turn, and the drain of second N channel field effect tube is connected with external feedback signal, and the source thereof is connected with the intermediate node of third resistance and fourth resistance series connection circuit;The intermediate node of first resistance and second resistance series connection circuit outputs first reference voltage, and the intermediate node of third resistance and fourth resistance series connection circuit outputs second reference voltage;The drain of first N channel field effect tube, second P channel field effect tube and third P channel field effect tube is connected with external input voltage respectively.

[0011] As the limitation of the resistance network in the utility model: the ratio of first resistance: second resistance: third resistance: fourth resistance in the resistance network is 20:21:18:21.

[0012] As the limitation of the utility model in the moment of silence is control circuit: the mode control circuit includes feedback voltage selection circuit, soft start voltage selection circuit, the feedback voltage selection circuit includes first comparator circuit, first two alternative circuit, the negative input end of first comparator circuit connects the first reference voltage output end of reference voltage signal generation circuit, the output end connects the first two alternative circuit, and the output end generates logic signal simultaneously and connects the second input end of or gate of reference voltage signal generation circuit, one static contact of the switch of the first two alternative circuit is connected with the second reference voltage output end of reference voltage signal generation circuit respectively, the other static contact is connected with external feedback signal, and the dynamic contact exports the feedback signal selected after mode control circuit;

[0013] The soft start voltage selection circuit includes second comparator circuit, second two alternative circuit, the positive input end of second comparator circuit is connected with the dynamic contact of the switch of the first two alternative circuit, the negative input end is as reference 0.26V voltage end, the output end is connected with the second two alternative circuit, one static contact of the switch of the second two alternative circuit is connected with the soft start voltage signal output end of soft start voltage signal generation circuit respectively, the other static contact is as reference 0.25V voltage end, and the dynamic contact exports the soft start voltage selected after.

[0014] As the limitation of the utility model in the differential operational amplifier circuit and the adjustable drive circuit of drive voltage:

[0015] The differential operational amplifier circuit is two-stage differential operational amplifier, the positive input end is inputted with the feedback signal selected after mode control circuit, and the negative input end is inputted with the soft start signal selected after mode control circuit;

[0016] The adjustable drive circuit of drive voltage includes two series-connected source followers, the input end of the series circuit of two source followers is connected with the output end of differential operational amplifier circuit, and the output end signal exports V-ADJ drive signal, and the clock signal end of adjustable drive circuit of drive voltage is controlled by square wave clock signal with duty ratio of 50%.

[0017] Compared with the prior art, the utility model has the following technical progress:

[0018] 1. The utility model provides a kind of open loop and closed loop mode selection circuit for capacitive negative voltage charge pump, and the output voltage of response is selected according to the working mode of charge pump ground Anu, both can satisfy the working mode of open loop charge pump circuit, and can satisfy the working mode of closed loop charge pump circuit, effectively solve the problem of poor versatility of chip;

[0019] 2. The reference voltage signal generating circuit designs a resistance network of the first resistance to the fourth resistance, can control the internal comparator to make corresponding selection to various reference voltages by judging whether there is a resistance feedback network outside, and achieves the purpose of controlling different working modes;

[0020] 3. The utility model discloses flexible selection working mode, and does not increase the peripheral device and PCB wire of charge pump circuit, covers all functions of two modes of similar chip at home and abroad, has great help to the urgent nationalization replacement at present, dual mode operation and controllable output voltage, greatly improve the versatility and convenience of user in chip selection and use.

[0021] In conclusion, the open and closed loop mode selection circuit for the capacitive negative voltage charge pump is suitable for the charge pump circuit of the open and closed loop mode, and can be suitable for different working scenes.

[0022] The utility model is suitable for the capacitive negative voltage charge pump circuit under any mode of open and closed loop.

[0023] The utility model discloses make further detailed description below combining with the drawings and specific embodiment.

[0024] Figure 1 It is the function principle diagram of the capacitive negative voltage charge pump of the utility model;

[0025] Figure 2 It is the circuit principle diagram of the embodiment of the utility model;

[0026] Figure 3 It is Figure 2 The circuit principle diagram of soft start and reference voltage signal generating circuit in it;

[0027] Figure 4 It is Figure 2 The circuit principle diagram of mode control circuit in it;

[0028] Figure 5 It is Figure 4 The circuit principle diagram of comparator circuit in it;

[0029] Figure 6 It is Figure 4 The circuit principle diagram of two-way switch circuit in it;

[0030] Figure 7 It is Figure 2 The circuit principle diagram of difference operational amplifier circuit in it;

[0031] Figure 8 It is Figure 2 The circuit principle diagram of drive voltage adjustable drive circuit in it;

[0032] Figure 9The application graph of the embodiment of the utility model for the application of the chip in open loop mode;

[0033] Figure 10 The starting curve when the embodiment of the utility model is used in open loop mode;

[0034] Figure 11 The signal change graph of the output drive voltage V-ADJ when the embodiment of the utility model is used in open loop mode;

[0035] Figure 12 The simulation result graph when the embodiment of the utility model is used in open loop mode;

[0036] Figure 13 The local period graph when the embodiment of the utility model is used in open loop mode, and the system normally works after starting ends;

[0037] Figure 14 The application graph of the embodiment of the utility model for the application of the chip in closed loop mode;

[0038] Figure 15 The starting curve when the embodiment of the utility model is used in closed loop mode;

[0039] Figure 16 The signal change graph of the output drive voltage V-ADJ when the embodiment of the utility model is used in closed loop mode;

[0040] Figure 17 The simulation result graph when the embodiment of the utility model is used in closed loop mode;

[0041] Figure 18 The local period graph when the embodiment of the utility model is used in closed loop mode, and the system normally works after starting ends. DETAILED DESCRIPTION

[0042] The utility model will be further explained in detail through specific embodiments. It should be understood that the described embodiments are only for explaining the utility model, and do not limit the utility model.

[0043] Embodiment Open and closed loop mode selection circuit for capacitive negative voltage charge pump

[0044] The embodiment is as shown in Figure 2 It comprises soft start and reference voltage signal generating circuit, mode control circuit, differential operational amplifier circuit, drive voltage adjustable drive circuit that are connected in turn. Wherein:

[0045] I. Soft start and reference voltage signal generating circuit can provide soft start voltage from high to low, and can provide two reference voltages for subsequent mode control circuit.

[0046] The soft start and reference voltage signal generating circuit in the embodiment is as shown in Figure 3As shown, the soft start voltage signal generating circuit and the reference voltage signal generating circuit are connected in parallel, and the output terminal of the first inverter INV1 is connected to the soft start voltage signal generating circuit and the reference voltage signal generating circuit respectively.

[0047] Specifically, 1. The soft start voltage signal generating circuit comprises a first N-channel field effect transistor MN1, a first P-channel field effect transistor MP1, a first Schmitt inverter SMINV1, and a second inverter INV2. The signal output terminal of the first inverter INV1 is connected to the gate of the first N-channel field effect transistor MN1. The drain of the first N-channel field effect transistor MN1 is connected to the gate of the first P-channel field effect transistor MP1 through the first Schmitt inverter SMINV1 and the second inverter INV2. The drain of the first P-channel field effect transistor MP1 is used as the feedback signal input terminal FB of the embodiment, and the source thereof outputs the soft start voltage TR-SS. The source of the first N-channel field effect transistor MN1 and the source of the first P-channel field effect transistor MP1 are both connected to the ground. In the embodiment, the source of the first N-channel field effect transistor MN1 is further connected to the ground through a first capacitor C1 in series, and the source of the first P-channel field effect transistor MP1 is further connected to the ground through a second capacitor C2 in series.

[0048] 2. The reference voltage signal generating circuit comprises a third inverter INV3, a second N-channel field effect transistor MN2, a second P-channel field effect transistor MP2, a third P-channel field effect transistor MP3, and a resistor network comprising a first resistor R1 to a fourth resistor R4. The signal output terminal of the first inverter INV1 is connected to the gate of the second P-channel field effect transistor MP2 and the gate of the third P-channel field effect transistor MP3 respectively. The source of the second P-channel field effect transistor MP2 is connected to the series circuit of the first resistor R1 and the second resistor R2. The source of the third P-channel field effect transistor MP3 is connected to the series circuit of the third resistor R3 and the fourth resistor R4. The series circuit of the first resistor R1 and the second resistor R2 is connected in parallel with the series circuit of the third resistor R3 and the fourth resistor R4.

[0049] Meanwhile, the gate of the first P-channel field effect transistor MP1 is connected to the gate of the second N-channel field effect transistor MN2 through a third inverter INV3 and an OR gate OR in series. The drain of the second N-channel field effect transistor MN2 is connected to the external feedback signal input terminal FB, and the source thereof is connected to the middle node of the series circuit of the third resistor R3 and the fourth resistor R4. The middle node of the series circuit of the first resistor R1 and the second resistor R2 outputs the first reference voltage VB1, and the middle node of the series circuit of the third resistor R3 and the fourth resistor R4 outputs the second reference voltage VB2. The drains of the first N-channel field effect transistor MN1, the second P-channel field effect transistor MP2, and the third P-channel field effect transistor MP3 are used as the input voltage terminal VIN of the embodiment.

[0050] II. Mode control circuit, which generates logic signal MODE-CTRL by detecting the value of external feedback signal FB

[0051] The reference voltage of the selected response is used to control the operation of the corresponding system mode. The mode control circuit, as shown in Figure 4 includes a feedback voltage selection circuit and a soft start voltage selection circuit. The feedback voltage selection circuit includes a first comparator circuit CMP1 and a first two-way switch 2S1-1. The positive input terminal of the first comparator circuit CMP1 is also connected to the external feedback signal FB as the feedback signal input terminal FB of the embodiment. The negative input terminal is connected to the first reference voltage output terminal VB1 of the reference voltage signal generation circuit. The output terminal is connected to the first two-way switch 2S1-1. The output terminal generates a logic signal MODE-CTRL which is connected to the second input terminal of the OR gate OR of the reference voltage signal generation circuit. The first stationary contact A1 of the switch of the first two-way switch 2S1-1 is connected to the second reference voltage output terminal VB2 of the reference voltage signal generation circuit. The second stationary contact B1 is connected to the external feedback signal FB. The moving contact C1 outputs the first feedback signal FB-1 of the mode control circuit.

[0052] The soft start voltage selection circuit includes a second comparator circuit CMP2 and a second two-way switch 2S1-2. The positive input terminal of the second comparator circuit CMP2 is connected to the moving contact C1 of the switch of the first two-way switch 2S1-1. The negative input terminal is the reference 0.26V voltage terminal of the embodiment. The output terminal is connected to the second two-way switch 2S1-2. The first stationary contact A2 of the switch of the second two-way switch 2S1-2 is connected to the soft start voltage signal TR-SS of the soft start voltage signal generation circuit. The second stationary contact B2 is the reference 0.25V voltage terminal of the embodiment. The moving contact C2 outputs the selected soft start voltage VREF-EA.

[0053] Further, the first comparator circuit and the second comparator circuit have the same structure, as shown in Figure 5 includes first to seventh field effect transistors Q1-Q7, a second Smithe inverter SMINV2, and a fourth inverter INV4. The gates of the second field effect transistor Q1 and the second field effect transistor Q2 are both connected to the signal VBP. The drains are both connected to the external input voltage VIN. The source of the first field effect transistor Q1 is connected in series with the bridge circuit of the third to sixth field effect transistors Q3-Q6 and then connected to ground. The source of the second field effect transistor Q2 is connected in series with the second Smithe inverter SMINV2 and the fourth inverter INV4 in turn and then connected to the output OUT of the comparator amplification circuit. The bridge circuit formed by the third to sixth field effect transistors Q3-Q6 is connected in series with the seventh field effect transistor Q7 and then forms a parallel circuit with the second field effect transistor Q2, which is also connected to the input terminal of the Smithe inverter SMINV2.

[0054] The first switch circuit 2S1-1 and the second switch circuit 2S1-2 are also the same structure, specifically as shown in Figure 6 As shown, the fifth inverter INV5, the fourth P-channel field effect transistor MP4, the fifth P-channel field effect transistor MP5, the third N-channel field effect transistor MN3, and the fourth N-channel field effect transistor MN4 are included, wherein the external excitation signal EN is connected to the gate of the fourth P-channel field effect transistor MP4 and the third N-channel field effect transistor MN3 after passing through the fifth inverter INV5, the drain of the fourth P-channel field effect transistor MP4 is connected to the drain of the third N-channel field effect transistor MN3 to serve as the first / second static contact A1 / A2 of the first / second switch circuit 2S1-1 / 2S1-2, the drain of the fifth P-channel field effect transistor MP5 is connected to the drain of the fourth N-channel field effect transistor MN4 to serve as the second static contact C1 / C2 of the first / second switch circuit 2S1-1 / 2S1-2, and the source of the fourth P-channel field effect transistor MP4, the third N-channel field effect transistor MN3, the fifth P-channel field effect transistor MP5, and the fourth N-channel field effect transistor MN4 are connected to serve as the movable contact B1 / B2 of the first / second switch circuit 2S1-1 / 2S1-2.

[0055] III. The differential operational amplifier circuit is a two-stage differential operational amplifier, the positive input end inputs the feedback signal selected by the mode control circuit, and the negative input end inputs the soft start signal selected by the mode control circuit. The specific circuit is as shown in Figure 7As shown, including the eighth field effect tube Q8 to the twelfth field effect tube Q16, resistance RC, capacitor CC, third capacitor C3, the eighth field effect tube Q8 to the eleventh field effect tube Q11 constitute a first bridge, the twelfth field effect tube Q12 to the fifteenth field effect tube Q15 constitute a second bridge, that is, the drain of the eighth field effect tube Q8 and the drain of the tenth field effect tube Q10 are connected, the drain of the ninth field effect tube Q9 and the drain of the eleventh field effect tube Q11 are connected, the source of the eighth field effect tube Q8 and the source of the ninth field effect tube Q9 are connected, the source of the tenth field effect tube Q10 and the source of the eleventh field effect tube Q11 are connected, the gate of the eighth field effect tube Q8 inputs the selected soft start voltage VREF-EA, the gate of the tenth field effect tube Q10 inputs the first feedback signal FB-1, the gates of the ninth field effect tube Q9 and the tenth field effect tube Q10 are connected to their own sources; In the second bridge, the gate of the twelfth field effect tube Q12 is connected to the gate of the fourteenth field effect tube Q14, the drain of the twelfth field effect tube Q12 is connected to the drain of the fourteenth field effect tube Q14, the source of the twelfth field effect tube Q12 is connected to the drain of the thirteenth field effect tube Q13, the source of the thirteenth field effect tube Q13 is connected to the source of the fifteenth field effect tube Q15 and grounded, the source of the fourteenth field effect tube Q14 is connected to the drain of the fifteenth field effect tube Q15, as the output terminal of the differential operational amplifier circuit, output signal VEA; The gate of the thirteenth field effect tube Q13 is connected to the intermediate node of the source of the eighth field effect tube Q8 and the ninth field effect tube Q9 in the first bridge, and the gate of the fifteenth field effect tube Q15 is connected to the intermediate node of the source of the tenth field effect tube Q10 and the eleventh field effect tube Q11 in the first bridge. The drain of the sixteenth field effect tube Q16 is connected to the intermediate node of the drain of the twelfth field effect tube Q12 and the drain of the fourteenth field effect tube Q14 in the second bridge, the drain of the sixteenth field effect tube Q16 is connected to the intermediate node of the drain of the eighth field effect tube Q8 and the tenth field effect tube Q10 in the first bridge, and the gate of the sixteenth field effect tube Q16 inputs the signal VBP. In addition, the resistance RC and the capacitor CC are connected in series and connected in parallel with the third capacitor C3, and the source of the fourteenth field effect tube Q14 and the drain of the fifteenth field effect tube Q15 are grounded.

[0056] When the charge pump circuit is detected as the open loop working mode, the embodiment has no feedback signal FB input, at this time, the input voltage difference between the two ends of the second differential operational amplifier is large, and it has no adjustment function, at this time, the error amplifier is equivalent to a comparator with a large capacitor connected to the output, and the output VEA is fixed as a large voltage value, and the third switch power tube NPOWER1 in the charge pump circuit works in the linear region in the working period, and the whole system runs in the open loop mode; when the charge pump circuit is detected as the closed loop working mode, the embodiment has the feedback signal FB input, and forms a negative feedback system, at this time, the voltage difference between the feedback signal FB and the reference signal is small, the circuit amplifies the voltage difference between the feedback signal and the reference signal, and the output VEA can adjust the size of the driving signal, and the third switch power tube NPOWER1 in the charge pump circuit works in the saturation region in the working period, and controls the VDS of the third switch power tube NPOWER1 in the charge pump circuit, so as to achieve the purpose of adjusting the output VOUT, and the whole system runs in the closed loop mode.

[0057] Four, the driving voltage adjustable driving circuit, the role of the driving voltage adjustable driving circuit in the embodiment is mainly to convert the VEA voltage into the gate voltage of the third switch power tube NPOWER1 of the charge pump circuit when the third switch power tube NPOWER1 is turned on through two source converters, and make the output signal V-ADJ have driving ability, at the same time, the clock signal end OSC is logically controlled by a square wave clock signal with a duty cycle of 50%, and does not affect the normal operation of the system.

[0058] The specific circuit is shown in Figure 8 The gate of the seventeenth field effect tube Q17 is connected with the gate of the eighteenth field effect tube Q18, the source of the seventeenth field effect tube Q17 is connected with the drain of the eighteenth field effect tube Q18, and then the drains of the fifth N-channel field effect tube MN5 and the sixth N-channel field effect tube MN6 are connected; the gate of the nineteenth field effect tube Q19 is connected with the gate of the twentieth field effect tube Q20, the source of the nineteenth field effect tube Q19 is connected with the gate of the nineteenth field effect tube Q19, and the drain of the nineteenth field effect tube Q19, the source of the twentieth field effect tube Q20, the source of the sixth P-channel field effect tube MP6, the source of the twenty-first field effect tube Q21, the source of the twenty-second field effect tube Q22, the source of the seventh P-channel field effect tube, and the source of the twenty-third field effect tube Q23 are connected.

[0059] The gate of the sixth P-channel field effect transistor MP6 is connected with the output signal VEA of the differential operational amplifier circuit, and the gate of the fifth N-channel field effect transistor MN5 is connected with the gate of the sixth P-channel field effect transistor MP6, and the drain of the sixth P-channel field effect transistor MP6 is connected with the source of the eighteenth field effect transistor Q18 and the gate of the sixth N-channel field effect transistor MN6; the source of the fifth N-channel field effect transistor MN5 is connected with the drain of the twenty-first field effect transistor Q21 and the gate of the seventh P-channel field effect transistor MP7, and the gate of the twenty-first field effect transistor Q21 is connected with the gate of the twentieth field effect transistor Q20; the input end of the sixth inverter INV6 is used as the clock signal end of the embodiment, and a square wave clock signal with a duty cycle of 50% is input, and the output end of the sixth inverter INV6 is connected with the gates of the twenty-second field effect transistor Q22 and the twenty-third field effect transistor Q23 respectively, and the drain of the seventh P-channel field effect transistor MP7, the source of the sixth N-channel field effect transistor and the drain of the twenty-third field effect transistor Q23 are connected with the signal V-ADJ of the third switch in the back output driving charge pump circuit, and the signal V-ADJ controls the gate of the third switch power transistor in the charge pump circuit.

[0060] The working principle of the embodiment is as follows: when the external excitation signal EN in the soft start and reference voltage signal generating circuit is high, the charge pump circuit works normally. When the external excitation signal EN changes from low to high, the signal ENN is low, the first N-channel field effect transistor MN1 is turned off, the constant current I1 continuously charges the first capacitor C1, and the voltage EN-1 on the first capacitor C1 rises linearly at a certain slope to high, so there is a delay time of tens of microseconds between the external excitation signal EN and the signal EN-1, and then the first Smith inverter SMINV1 and the second inverter INV2 prevent the logic jump of the signal at the critical value to obtain the EN-A signal. The signal makes the EN-A signal always have a low level of tens of microseconds at the system start, and the level makes the second P-channel field effect transistor MP2 keep conducting for tens of microseconds at the start, so that the external feedback signal FB voltage is equal to the soft start voltage TR-SS. After the delay time ends, the soft start voltage TR-SS slowly decreases at a fixed slope under the action of the constant current source I2 until it is zero. The function of the soft start voltage TR-SS signal is to prevent the overshoot current at the system start, and the overshoot current is too large to damage the circuit chip. It is worth noting that the soft start of the embodiment is different from the past, because the output voltage VOUT is from zero to negative, so the soft start voltage TR-SS must also be from high to low.

[0061] And the external excitation signal EN from low to high, ENN for low level makes the second P-channel field effect transistor MP2, the third P-channel field effect transistor MP3 conduction, the first resistance R1 to the fourth resistance R4 resistance network conduction. The second reference voltage VB2 in open loop mode when the value is defined as VB2open, and the second reference voltage VB2 value in closed loop work is defined as VB2loop. When the charge pump chip for open loop mode work, according to the resistance division law:

[0062] ,

[0063] As formula (4), the feedback signal FB is not affected by the second reference voltage VB2. In which the resistance bridge satisfies R1:R2:R3:R4=20:21:18:21, the circuit in this embodiment R1=2MΩ, R2=2.1MΩ, R3=1.8MΩ when the charge pump circuit for closed loop mode slice, the first reference voltage VB1 is unchanged, the value of the external feedback signal FB is divided into two stages, the second reference voltage VB2loop, the external feedback signal FB according to the resistance division law:

[0064] ,

[0065] (4) the second N-channel field effect transistor MN2 conduction stage, the external feedback signal FB is affected by VB2, according to formula (3) then FB=VB2loop; the second N-channel field effect transistor MN2 off stage, R4=2.1MΩ. Known charge pump closed loop work, VIN=3.3~5V, VOUT=-2.5~4.5, set RF1=100kΩ, must have RF2=58kΩ~100kΩ (RF1, RF2 for chip external feedback resistance). RF1, RF2 resistance value is much smaller than R3, R4 resistance value, so there is .

[0066] The above resistance value is to make the first reference voltage VB1, the second reference voltage VB2 for the positive voltage; take larger resistance value is to reduce the power consumption. Known charge pump output voltage signal VOUT for negative voltage, and the absolute value of the output voltage signal VOUT is less than the input voltage VIN, therefore according to the above formula, there is always VB2open>VB1>0, and VB2open>0.26V; charge pump circuit closed loop VB1>VB2loop>0, that is, VB1>FB>0.

[0067] Because of the prior art in the chip VIN under voltage protection circuit exists, therefore, whether the input voltage

[0068] VIN first power or external excitation signal EN first power, the chip will wait until the VIN signal end power before starting normal work. Because TR-SS=FB-VDSMP1 (VDSMP1 is Figure 2 The first P-channel field effect transistor MP1 conduction when the source-drain voltage, very small), so the charge pump circuit start TR-SS≈FB.

[0069] Charge pump circuit open loop use, the embodiment start FB=VIN·R4 / (R3+R4); closed loop use, the embodiment start FB=VIN·RF2 / (RF1+RF2). Whether open loop or closed loop work, the chip start TR-SS≈FB, and always greater than 1.2V.

[0070] And when the charge pump circuit open loop use, no external feedback signal FB, so the feedback signal input end FB in this embodiment as chip pin, will be floating. Start, EN-B signal constant have tens of microseconds for high, through the or gate OR makes the second N-channel field effect transistor MN2 conduction for a period of time, FB=VB2open, known VB2open>VB1, therefore FB>VB1, such as Figure 4 The CMP1 comparator output logic signal MODE-CTRL for high, further keep MN2 conduction constant FB=VB2open. At the same time Figure 4 The logic signal MODE-CTRL for high control first two alternative circuit 2S1-1 select FB-1=VB2open=FB, and FB-1>0.26V, therefore the output voltage of the second comparator circuit CMP2 CMP-OUT constant for high, make VREF-EA=TR-SS.

[0071] The soft start signal TR-SS and the external feedback FB signal are selected by two selection circuits and then transmitted to the two input terminals of the differential operational amplifier circuit as the voltage signal VREF-EA and the selected feedback voltage signal FB-1. As the chip starts to work, the soft start voltage TR-SS decreases at a fixed slope, and the feedback signal FB also decreases with the decrease of the output voltage signal VOUT, and the decrease slopes of the two signals are almost the same. At this time, the voltage difference between the soft start voltage VREF-EA and the selected feedback voltage FB-1 is small, and the output voltage VEA of the differential operational amplifier circuit slowly rises, avoiding the start overshoot current, until the voltage FB-1 decreases to VIN-(VIN-VOUT)·R4 / (R3+R4) and no longer decreases, and the soft start voltage VREF-EA decreases to 0V. At this time, the input terminal voltage difference of the differential operational amplifier circuit is getting larger and larger, and when the condition of virtual short cannot be met, the voltage VEA will be pulled to VIN, completing the soft start and normally running the chip. Therefore, when the charge pump circuit is used in open loop, the working curves of the soft start voltage VREF-EA, the voltage FB-1 and the output voltage VEA of the differential operational amplifier circuit in the open loop working of the charge pump in the embodiment are as shown in Figure 10 .

[0072] The output voltage VEA of the differential operational amplifier circuit is converted into the V-ADJ signal with driving capability by the driving voltage adjustable driving circuit, and the high level voltage of V-ADJ is VIN-VGSMN5+VGSMP7. Under the control of the input signal OSC signal in the front stage of the charge pump, V-ADJ will control the opening and closing of the third switch power tube NPOWER1 in the charge pump circuit with the square wave signal as shown in Figure 11 . At this time, in the period of the on-time of the third switch power tube NPOWER1 in the charge pump circuit, the V-ADJ signal makes the third switch power tube NPOWER1 in the charge pump circuit work in the linear region. The existence of the fifth resistance R5 makes VEA-1 not be pulled down to 0 when OSC=0, which helps to increase the on-time of NPOWER1 in the next period.

[0073] When used in open loop, the chip application diagram is as shown in Figure 9 , the input VIN of the positive and negative charge pump chip is 5V, Rload=500Ω, and the output is slightly greater than-5V. The simulation result diagram of the open loop use of the embodiment is as shown in Figure 12 . And the simulation result diagram of the open loop use of the embodiment is as shown in Figure 13It can be seen that when the external feedback signal FB floats, the system starts to work at 100uS (the external excitation EN level changes from low to high), and the logic signal MODE-CTRL is always high. FB-1 and the soft start voltage VREF-EA signal are input to the differential operational amplifier circuit, and first decrease at the same initial value and the same slope. During this period, the voltage difference between the two ends is small, and the output voltage VEA of the differential operational amplifier circuit slowly rises. Until about 220uS, FB-1 decreases to about 0.4V and no longer decreases, while the soft start signal VREF-EA decreases to 0V. At this time, the voltage difference is large, so that the output voltage VEA of the differential operational amplifier circuit is 5V. At this time, the high-level voltage of the driving voltage V-ADJ is VIN-VGSMN5+VGSMP7, so that the power tube NPOWER1 of the third switch in the charge pump circuit is turned on and works in the linear region. At this time, the value of VOUT is determined by the voltage drop caused by the conduction of switches S1, S2, S3 and S4 (the voltage drop is related to the conduction resistance of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 in the charge pump circuit and the load current).

[0074] When the charge pump circuit is used in a closed loop, the application diagram of the embodiment is as shown in Figure 14 The value of VOUT is set by the external feedback resistance network RF1 and RF2. At this time, the input voltage of the charge pump chip is 5V, RF1=100kΩ, RF2=74.74kΩ, Rload=33Ω, and the output is-3.3V. At this time, the simulation result of the embodiment is as shown in Figure 17 At this time, FB is used as a chip pin, and FB has a feedback signal input. When starting, EN-B is always high for tens of microseconds, and the OR gate makes the second N-channel field effect transistor MN2 conduct for a period of time, so that FB=VB2loop. Since VB1>VB2loop, as shown in Figure 4 the CMP1 comparator output MODE-CTRL is low, MN2 is disconnected, FB≠VB2loop, VB1>FB, and the MODE-CTRL signal is always low, which controls the 2-to-1 circuit (2S1) to always select FB-1=FB, and VB2loop is abandoned. When FB-1>0.26V, the output CMP-OUT of CMP2 is high, so that VREF-EA=TR-SS. When FB decreases to 0.26V or below with VOUT, the output CMP-OUT of CMP2 is low, so that VREF-EA=0.25V, and FB-1 is locked at 0.25V and no longer decreases under the action of negative feedback. VOUT is also locked at the set voltage value and no longer decreases.

[0075] TR-SS, 0.25V and FB signals are selected by two selectors and transmitted to the two input ends of the error amplifier, as shown inFigure 5 As the chip starts to work, the TR-SS voltage decreases with a fixed slope, and the FB voltage also decreases with the decrease of VOUT, and the decrease slopes of the two signals are almost the same. At this time, the voltage difference between VREF-EA and FB-1 is small, and the output VEA of the error amplifier slowly rises, avoiding the starting overshoot current, until FB-1 decreases to below 0.26V, the CMP2 output signal CMP-OUT is low, and VREF-EA will be switched to 0.25V reference voltage by TR-SS and no longer change. FB-1 is locked at about 0.25V under the action of the negative feedback system and no longer decreases, and the voltage difference between VREF-EA and FB-1 still remains small. The VEA voltage always maintains an intermediate value, completing the soft start and normally operating the chip, such as Figure 15 .

[0076] At this time, the output voltage VEA of the differential operational amplifier circuit is converted into the V-ADJ signal with driving ability by the adjustable drive voltage driving circuit, and the voltage is VEA+VGSMP6-VGSMN6 when V-ADJ is high. Under the control of the OSC signal, V-ADJ will control the on and off of the third switch power tube NPOWER1 in the charge pump circuit as shown in the square wave signal control. Figure 16 At this time, in the period of the on time of the third switch power tube NPOWER1 in the charge pump circuit, the V-ADJ signal makes NPOWER1 work in the saturation region. The existence of R5 makes VEA-1 not be pulled down to 0 when the front-stage input OSC=0, which helps to increase the on time of the third switch power tube NPOWER1 in the charge pump circuit in the next cycle.

[0077] By Figure 18It can be seen that when the FB port of the embodiment has the feedback signal provided by the external feedback resistor network RF1, RF2, the system starts to work at 100uS (the external excitation EN level changes from low to high), and the logic signal MODE-CTRL signal is always low. The FB-1 and soft start voltage VREF-EA signals are input terminals of the differential operational amplifier circuit, and first decrease at almost the same initial value and the same slope. During this period, the voltage difference between the two terminals is small, and the output voltage VEA of the differential operational amplifier circuit slowly rises. Until about 700uS, when the external feedback signal FB decreases to about 0.26V, the internal comparator will control VREF-EA=0.25V reference voltage, and the FB-1 voltage will be fixed at about 0.25V under the action of negative feedback. From the beginning to the end, the voltage difference between the two input terminals of the differential operational amplifier circuit is small, and the value of the output voltage VEA of the differential operational amplifier circuit is locked at an intermediate value. At this time, the high-level voltage of the driving voltage V-ADJ is VEA+VGSMP6-VGSMN6, so that the third switch power NPOWER1 in the charge pump circuit is turned on and works in the saturation region. At this time, the value of the output voltage VOUT is determined by the ratio of the feedback resistors RF1, RF2.

Claims

1. An open, closed loop mode selection circuit for a capacitive negative voltage charge pump, characterized by, The application relates to a soft start and reference voltage signal generating circuit, a mode control circuit, a differential operational amplifier circuit and a driving voltage adjustable driving circuit, wherein an enabling signal end of the soft start and reference voltage signal generating circuit is externally connected with an externally driven excitation signal, the soft start signal and two reference voltage signals generated by the soft start and reference voltage signal generating circuit are connected with the mode control circuit respectively, the mode control circuit generates a logic signal feedback to the soft start and reference voltage signal generating circuit by detecting the value of a feedback signal, the soft start signal and the feedback signal are selected according to the system working mode, and then the soft start signal is sequentially transmitted to the differential operational amplifier circuit and the driving voltage adjustable driving circuit, and the output end of the driving voltage adjustable driving circuit controls the gate of a third switch power tube in a charge pump circuit.

2. The open / closed loop mode selection circuit for a capacitive negative voltage charge pump of claim 1, wherein, The soft start and reference voltage signal generating circuit comprises a soft start voltage signal generating circuit and a reference voltage signal generating circuit, wherein the soft start voltage signal generating circuit and the reference voltage signal generating circuit are connected in parallel, and the input end of a first inverter is used as an enabling signal end of an open and closed loop mode selection circuit for the capacitive negative voltage charge pump.

3. The open / shorted loop mode selection circuit for a capacitive negative voltage charge pump of claim 2, wherein, The soft start voltage signal generating circuit comprises a first N-channel field effect tube, a first P-channel field effect tube, a first Schmitt inverter and a second inverter, the output end of the first inverter is connected with the gate of the first N-channel field effect tube, the drain of the first N-channel field effect tube is connected with the gate of the first P-channel field effect tube through the first Schmitt inverter and the second inverter, the drain of the first P-channel field effect tube is used as a feedback signal input end of the open and closed loop mode selection circuit for the capacitive negative voltage charge pump, the source of the first P-channel field effect tube outputs a soft start voltage, and the sources of the first N-channel field effect tube and the first P-channel field effect tube are grounded.

4. The open / shorted loop mode selection circuit for a capacitive negative voltage charge pump of claim 3, wherein, The reference voltage signal generating circuit comprises a third inverter, a second N-channel field effect tube, a second P-channel field effect tube and a third P-channel field effect tube, and a resistor network formed by a first resistor to a fourth resistor, the signal output end of the first inverter is connected with the gates of the second P-channel field effect tube and the third P-channel field effect tube respectively, the source of the second P-channel field effect tube is connected with a series circuit of the first resistor and the second resistor, the source of the third P-channel field effect tube is connected with a series circuit of the third resistor and the fourth resistor, and the series circuit of the first resistor and the second resistor and the series circuit of the third resistor and the fourth resistor are connected in parallel. The gate of the first P-channel field effect tube is connected with the gate of the second N-channel field effect tube in sequence after being connected with the third inverter and an OR gate, the drain of the second N-channel field effect tube is connected with an external feedback signal, and the source of the second N-channel field effect tube is connected with the middle node of the series circuit of the third resistor and the fourth resistor; the middle node of the series circuit of the first resistor and the second resistor outputs a first reference voltage, the middle node of the series circuit of the third resistor and the fourth resistor outputs a second reference voltage, and the drains of the first N-channel field effect tube, the second P-channel field effect tube and the third P-channel field effect tube are connected with external input voltages respectively.

5. The open / shorted loop mode selection circuit for a capacitive negative voltage charge pump of claim 4, wherein, In the resistor network, the first resistor: the second resistor: the third resistor: the fourth resistor=20:21:18:

21.

6. The open / closed loop mode selection circuit for a capacitive negative voltage charge pump of claim 4 or 5, wherein, The mode control circuit comprises a feedback voltage selection circuit and a soft start voltage selection circuit, the feedback voltage selection circuit comprises a first comparator circuit and a first two-way selection circuit, the negative input end of the first comparator circuit is connected with the first reference voltage output end of a reference voltage signal generation circuit, the output end is connected with the first two-way selection circuit, and the output end generates a logic signal connected with the second input end of an OR gate of the reference voltage signal generation circuit; one static contact of the switch of the first two-way selection circuit is connected with the second reference voltage output end of the reference voltage signal generation circuit, the other static contact is connected with an external feedback signal, and the dynamic contact outputs a feedback signal selected by the mode control circuit; the soft start voltage selection circuit comprises a second comparator circuit and a second two-way selection circuit, the positive input end of the second comparator circuit is connected with the dynamic contact of the switch of the first two-way selection circuit, the negative input end is a reference 0.26V voltage end, the output end is connected with the second two-way selection circuit, one static contact of the switch of the second two-way selection circuit is connected with the soft start voltage signal output end of a soft start voltage signal generation circuit, the other static contact is a reference 0.25V voltage end, and the dynamic contact outputs a selected soft start voltage.

7. The open / shorted loop mode selection circuit for a capacitive negative voltage charge pump of claim 6, wherein, The differential operational amplifier circuit is a two-stage differential operational amplifier, the positive input end of which inputs the feedback signal selected by the mode control circuit, and the negative input end inputs the soft start signal selected by the mode control circuit; The driving voltage adjustable driving circuit comprises two series-connected source followers, the input end of the series circuit of the two source followers is connected with the output end of the differential operational amplifier circuit, the output end signal of the driving voltage adjustable driving circuit outputs a V-ADJ driving signal, and the clock signal end source follower of the driving voltage adjustable driving circuit is controlled by a square wave clock signal with a duty cycle of 50%.

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