Semiconductor photonic device

Abstract

The embodiment of the utility model provides a semiconductor photonic device, which comprises a plurality of bus optical waveguide structures and one or more closed-loop optical waveguide structures which are arranged in a cascade photonic integrated circuit, such as a cascade resonator circuit. At least one closed-loop optical waveguide structure is fabricated to have a polygonal top-view shape, wherein the closed-loop optical waveguide structure includes a plurality of segments. This enables the intrinsic loss of the closed loop optical waveguide structure to be adjusted to achieve optical loss matching in a photonic integrated circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor photonic device. BACKGROUND

[0002] Semiconductor photonic devices can be configured for high-speed and secure data transmission with optical signals, which is performed between integrated circuits and / or semiconductor dies of the semiconductor photonic device. The optical signals can be transmitted through waveguides in the semiconductor photonic device. The waveguides enable confinement of the optical signals, which can reduce optical losses and increase the propagation efficiency of the optical signals. Light can be modulated into optical pulses by optical modulators to encode data into the optical signals. The optical pulses are then transmitted to the waveguides for propagation to other regions of the semiconductor photonic device. SUMMARY

[0003] Embodiments of the present application provide a semiconductor photonic device, comprising: a first optical waveguide structure; a second optical waveguide structure; and a third optical waveguide structure between the first optical waveguide structure and the second optical waveguide structure, the third optical waveguide structure comprising a top view shape having a plurality of segments.

[0004] In some embodiments, embodiments of the present application provide another semiconductor photonic device, comprising: a first optical waveguide structure comprising a first top view shape having a plurality of first segments; a second optical waveguide structure comprising a second top view shape having a plurality of second segments; and a third optical waveguide structure between the first optical waveguide structure and the second optical waveguide structure, the third optical waveguide structure comprising a third top view shape having a plurality of third segments.

[0005] In some embodiments, embodiments of the present application provide a method of forming a semiconductor photonic device, comprising: forming a first optical waveguide structure over a semiconductor substrate of the semiconductor photonic device, the first optical waveguide structure comprising a first top view shape; forming a second optical waveguide structure over the semiconductor substrate, the second optical waveguide structure comprising a second top view shape; and forming a third optical waveguide structure over the semiconductor substrate, wherein the third optical waveguide structure is between the first optical waveguide structure and the second optical waveguide structure, and wherein the third optical waveguide structure comprises a third top view shape having a plurality of segments. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of embodiments of the present application can be better understood with reference to the following detailed description when considered in connection with the accompanying drawings. Note that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] Figures 1A-1ESchematic diagram for an example embodiment of a semiconductor photonic device as described herein.

[0008] Figures 2A-2D Schematic diagram for an example embodiment of a semiconductor photonic device as described herein.

[0009] Figures 3A-3E Schematic diagram for an example embodiment of a semiconductor photonic device as described herein.

[0010] Figures 4A-4E Schematic diagram for an example embodiment of a semiconductor photonic device as described herein.

[0011] Figures 5A-5F Schematic diagram for an example embodiment of a semiconductor photonic device (or part thereof) as described herein.

[0012] Figures 6A-6F Schematic diagram for an example embodiment of a semiconductor photonic device (or part thereof) as described herein.

[0013] Figures 7A-7D Schematic diagram for an example embodiment of a semiconductor photonic device (or part thereof) as described herein.

[0014] Figures 8A-8D Schematic diagram for an example embodiment of a semiconductor photonic device (or part thereof) as described herein.

[0015] Figures 9A-9E Schematic diagram for an example embodiment of a semiconductor photonic device (or part thereof) as described herein.

[0016] Figures 10A-10D Schematic diagram for an example embodiment of a semiconductor photonic device (or part thereof) as described herein.

[0017] Figures 11A-11C Schematic diagram for an example embodiment of a cross-sectional profile of one or more waveguide structures as described herein.

[0018] Figure 12 Flow diagram for an example process relating to the formation of a semiconductor photonic device as described herein. DETAILED DESCRIPTION

[0019] The following detailed description includes various examples or aspects of the provided subject matter. The following description is not meant to be limiting as to the scope of the application. For example, in the following description, a first feature can be described as being on or over a second feature. This can include embodiments where the first and second features are in direct contact, as well as embodiments where one or more additional features can be present between the first and second features such that the first and second features do not directly contact one another. Furthermore, the use of the same reference symbols in different drawings does not necessarily indicate the same or similar parts.

[0020] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0021] In some cases, a photonic integrated circuit of a semiconductor photonic device can include one or more waveguide structures. For example, a generally straight input / output waveguide structure (which can be referred to as a bus optical waveguide) can couple an optical signal to a ring waveguide structure, which can be used to filter (e.g., wavelength filter) or modulate the optical signal. In some cases, optical signal loss can occur as the optical signal propagates around the ring waveguide structure, as well as when the optical signal is coupled to and / or from the ring waveguide structure. Optical signal loss in the ring waveguide structure (intrinsic loss) can affect the quality factor (Q-factor) of the ring waveguide structure. Optical signal loss from coupling (extrinsic coupling loss) also affects the power coupling coefficient (k-value) of the ring waveguide structure. The power coupling coefficient is an indicator of the efficiency of optical signal coupling between the ring waveguide structure and the bus optical waveguide. If the extrinsic coupling loss, which reduces the power coupling coefficient, and the intrinsic loss, which reduces the Q-factor, are not controlled, the ring waveguide structure can not function effectively and / or can not effectively filter with high selectivity.

[0022] For example, when the external coupling loss is greater than the intrinsic loss, the ring resonator structure and its associated input / output waveguide structures can become under-coupled, resulting in insufficient optical power transfer from the input / output waveguide structures to the ring resonator structure for modulation and / or filtering to occur. Conversely, when the intrinsic loss is greater than the external coupling loss, the ring resonator structure and its associated input / output waveguide structures can become over-coupled, resulting in interference in the ring resonator structure (which can lead to nonlinear effects and / or other modulation imperfections) and excessive power consumption in the ring resonator structure.

[0023] Some embodiments described herein provide techniques and apparatuses for semiconductor photonic devices that include a closed-loop optical waveguide structure that is configured to have a top-view size and / or shape to achieve a particular optical signal loss (intrinsic loss) for the closed-loop optical waveguide structure. The closed-loop optical waveguide structure can be fabricated to have a top-view shape that is polygonal (e.g., a top-view shape that is approximately octagonal or a top-view shape that is approximately hexagonal, among other examples), where the closed-loop optical waveguide structure includes a plurality of segments. The closed-loop optical waveguide structure can be fabricated to have a particular radius, to have a particular number of segments, and / or to have another property in order to achieve the particular optical signal loss for the closed-loop optical waveguide structure.

[0024] Fabricating the closed-loop optical waveguide structure to have the particular optical signal loss enables the Q-factor of the closed-loop optical waveguide structure to be balanced with the power coupling coefficient of the closed-loop optical waveguide structure. This enables the closed-loop optical waveguide structure to reach (or approach) a critical coupling, which is a condition in which the external coupling loss of the closed-loop optical waveguide structure is approximately equal to the optical signal loss of the closed-loop optical waveguide structure. At or near the critical coupling, the closed-loop optical waveguide structure can achieve efficient operation (e.g., modulation or filtering with minimal modulation imperfections and reduced power consumption) and high selectivity of optical filtering relative to over-coupling or under-coupling.

[0025] Furthermore, in some embodiments described herein, a semiconductor photonic device includes a plurality of bus optical waveguide structures and one or more closed-loop optical waveguide structures that are arranged in a cascaded photonic integrated circuit, such as a cascaded resonator circuit. At least one of the closed-loop optical waveguide structures is fabricated to have a polygonal top-view shape, where the closed-loop optical waveguide structure includes a plurality of segments. This enables the intrinsic loss of the closed-loop optical waveguide structure to be adjusted to achieve optical loss matching in the photonic integrated circuit.

[0026] Figures 1A-1E Schematic diagrams for example embodiments of example semiconductor photonic devices described herein. The semiconductor photonic devices include one or more photonic integrated circuits. Figures 1A-1EFIG. 1 illustrates a top view of an example embodiment of a semiconductor photonic device. The semiconductor photonic device can be configured to use optical signals for high-speed and secure data transmission between integrated circuits and / or semiconductor dies of the semiconductor photonic device.

[0027] As Figure 1A As shown in example embodiment 100 of FIG. 1, the semiconductor photonic device 102 can include a closed-loop optical waveguide structure 104 and a plurality of bus optical waveguide structures 106a and 106b. The closed-loop optical waveguide structure 104 is positioned between the bus optical waveguide structures 106a and 106b such that the bus optical waveguide structures 106a and 106b are positioned adjacent to opposite sides of the closed-loop optical waveguide structure 104. The closed-loop optical waveguide structure 104 and the bus optical waveguide structures 106a and 106b are arranged in a photonic integrated circuit, such as a resonator circuit or a modulator circuit, among other examples.

[0028] Optical signals can be transmitted through the bus optical waveguide structure 106a in the semiconductor photonic device 102. Opposite ends of the bus optical waveguide structure 106a correspond to an input port and a traverse port (or an output port) of the photonic integrated circuit. The bus optical waveguide structure 106a enables optical signals to be confined within, which can reduce optical loss and increase the propagation efficiency of the optical signals. In some embodiments, data can be encoded into optical signals by modulating light into optical pulses in the closed-loop optical waveguide structure 104. These optical pulses are then transferred to the bus optical waveguide structure 106 to propagate to other areas of the semiconductor photonic device 102. Alternatively, specific wavelengths of the optical signals can be filtered in the closed-loop optical waveguide structure 104 such that the filtered wavelengths (or unfiltered wavelengths) are transferred back to the bus optical waveguide structure 106 for signal propagation.

[0029] The bus optical waveguide structure 106b can be used to control or manipulate the optical resonance properties of the closed-loop optical waveguide structure 104. For example, opposite ends of the bus optical waveguide structure 106b can correspond to a drop port and an add port of the photonic integrated circuit. Specific wavelengths or frequencies of the optical signals in the closed-loop optical waveguide structure 104 can be coupled to the bus optical waveguide structure 106b and removed through the drop port for optical signal filtering of those wavelengths or frequencies of the optical signals. Conversely, the add port can be used to add specific wavelengths or frequencies of the optical signals into the closed-loop optical waveguide structure 104 by coupling the specific wavelengths or frequencies of the optical signals from the bus optical waveguide structure 106b into the closed-loop optical waveguide structure 104.

[0030] The closed-loop optical waveguide structure 104 and the bus optical waveguide structures 106a and 106b can be adjacent and / or side-by-side in the semiconductor photonic device 102 to achieve optical signal coupling between the closed-loop optical waveguide structure 104 and the bus optical waveguide structures 106a and 106b. For example, as Figure 1A As shown, the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a may be horizontally adjacent (or laterally adjacent) in the x-direction within the semiconductor photonic device 102, and the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106b may also be horizontally adjacent (or laterally adjacent) in the x-direction within the semiconductor photonic device 102. The bus optical waveguide structures 106a and 106b extend in the y-direction along opposite sides of the closed-loop optical waveguide structure 104. In some embodiments, the distance or spacing between the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a, and between the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106b, are approximately equal. In some embodiments, the distance or spacing between the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a, and between the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106b, are different distances.

[0031] The closed-loop optical waveguide structure 104 is "closed-loop" because its structure is a continuous waveguide structure that is interconnected and has no endpoints. This differs from other types of modulators and resonators (such as Mach-Zehnder modulators (MZMs)), which have endpoints corresponding to their inputs and outputs. Unlike the propagation of optical signals through the inputs and outputs of an MZM to couple optical signals into and out of it, optical signals are coupled into and out of the closed-loop optical waveguide structure 104 via evanescent coupling. When the evanescent field of an optical signal propagating through bus optical waveguide structure 106a (or from bus optical waveguide structure 106b) extends into a portion of the closed-loop optical waveguide structure 104 adjacent to bus optical waveguide structure 106a (or adjacent to bus optical waveguide structure 106b), evanescent coupling occurs from bus optical waveguide structure 106a (or from bus optical waveguide structure 106b) to closed-loop optical waveguide structure 104. Similarly, when the evanescent field of an optical signal propagating through closed-loop optical waveguide structure 104 extends into a portion of bus optical waveguide structure 106a (or extends into bus optical waveguide structure 106b), evanescent coupling occurs from closed-loop optical waveguide structure 104 to bus optical waveguide structure 106a (or to bus optical waveguide structure 106b).

[0032] Optical signal loss occurs within the closed-loop optical waveguide structure 104 as the optical signal propagates around it. This optical signal loss (inherent loss) can affect the Q-factor of the closed-loop optical waveguide structure 104. In some cases, the Q-factor can be expressed as a ratio λ. cen / λ FWHM , where λ cen λ is the center wavelength of the optical signal propagating around the closed-loop optical waveguide structure 104, while λ FWHM It is the full width at half maximum (FWHM) of the optical signal. The full width at half maximum is a function of the inherent loss and corresponds to the bandwidth of the optical signal in which the transmission (e.g., loss) in the closed-loop optical waveguide structure 104 is less than -3 dB.

[0033] Optical signal loss also occurs when optical signals couple between the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a, and / or when optical signals couple between the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106b. Optical signal loss due to coupling (external coupling loss) affects the power coupling coefficient (κ value) of the closed-loop optical waveguide structure 104. The power coupling coefficient is an indicator of the optical signal coupling efficiency between the closed-loop optical waveguide structure 104 and the bus optical waveguide structures 106a and / or 106b. In some cases, the power coupling coefficient can be expressed as κ = 1 - exp(-2πRα), where R is the radius of the closed-loop optical waveguide structure 104 (e.g., ...). Figure 1A The dimension D1 is shown, and α represents the external coupling loss in decibels per centimeter (dB / cm).

[0034] If external coupling loss α (which reduces the power coupling coefficient) and inherent loss (which affects λ) FWHM If the Q-factor is not controlled, the closed-loop optical waveguide structure 104 may not operate effectively and / or may not be able to filter with high selectivity. For example, when the external coupling loss is greater than the inherent loss, the closed-loop optical waveguide structure 104 and its associated bus optical waveguide structures 106a and / or 106b may become undercoupled, resulting in insufficient optical power transfer from the bus optical waveguide structures 106a and / or 106b to the closed-loop optical waveguide structure 104 for modulation and / or filtering. Conversely, when the inherent loss is greater than the external coupling loss, the closed-loop optical waveguide structure 104 and its associated bus optical waveguide structures 106a and / or 106b may become overcoupled, resulting in interference in the closed-loop optical waveguide structure 104 (which may cause nonlinear effects and / or other modulation defects) and excessive power consumption in the closed-loop optical waveguide structure 104.

[0035] In closed-loop optical waveguide structures, one of the main factors contributing to inherent losses is bending loss. Bending loss refers to the optical loss that occurs due to the closed-loop shape of the waveguide structure. Specifically, when an optical signal encounters a bend in the closed-loop waveguide structure, some of the signal is absorbed due to the interaction between the signal and the sidewalls of the waveguide at the bend, resulting in optical loss. Bending loss is generally inversely proportional to the radius of the closed-loop waveguide structure. The smaller the radius, the greater the bending loss (because the radius of curvature of the bend in the closed-loop waveguide structure is small), and the larger the radius, the smaller the bending loss. However, the resonant frequency of the closed-loop waveguide structure also depends on the radius. Therefore, it may be impossible to fabricate a closed-loop waveguide structure with a specific radius to achieve a specific inherent loss, as different radii may be needed to modulate and / or filter specific wavelengths of the optical signal being processed. Consequently, it may be impossible to achieve critical coupling for the closed-loop waveguide structure.

[0036] like Figure 1A As shown, the closed-loop optical waveguide structure 104 comprises a polygonal top-view shape having multiple segments 108 that are coupled to each other at connection points 110. Adjacent segments 108 are coupled at connection points 110 at their adjacent ends. Thus, each segment 108 is connected to two other segments 108 at its opposite ends. Figure 1A In the example, the first segment 108 and the connection point 110 at the opposite end of the first segment 108 are closest to the bus optical waveguide structure 106a, while the second segment 108 (opposite to the first segment 108) and the connection point 110 at the opposite end of the second segment 108 are closest to the bus optical waveguide structure 106b. In other embodiments, the connection point 110 is the portion of the closed-loop optical waveguide structure 104 closest to the bus optical waveguide structure 106a and / or the bus optical waveguide structure 106b.

[0037] The segment 108 of the closed-loop optical waveguide structure 104 introduces another type of loss, referred to as segment loss or segment-induced loss, which is attributed to the inherent loss of the closed-loop optical waveguide structure 104. While the radius of the closed-loop optical waveguide structure 104 may not be selectable to adjust its inherent loss (e.g., because the radius may be based on a specific resonant frequency for realizing the closed-loop optical waveguide structure 104), the size, shape, and / or number of segments 108 allow the closed-loop optical waveguide structure 104 to achieve a specific segment-induced loss. Therefore, the segment-induced loss allows the inherent loss of the closed-loop optical waveguide structure 104 to be adjusted without adjusting the radius of the closed-loop optical waveguide structure 104, enabling the achievement of a specific optical signal loss (inherent loss) in the closed-loop optical waveguide structure 104 to achieve critical coupling.

[0038] Figure 1AExamples of polygonal top view shapes of the closed loop optical waveguide structure 104 are schematically illustrated. In Figure 1A In examples, the closed loop optical waveguide structure 104 can have a top view shape that is approximately a dodecagon with twelve (12) interconnected segments 108. In other examples, the top view shape can be a hexagon with six (6) interconnected segments 108, an octagon with eight (8) interconnected segments 108, and / or other polygonal top view shapes. Other numbers of segments 108 and other top view shapes are within the scope of the present disclosure. The number of segments 108 can be an odd number of segments 108 (e.g., 5 segments, 17 segments) or can be an even number of segments 108 (e.g., 10 segments, 20 segments). In some embodiments, the closed loop optical waveguide structure 104 has a number of segments 108 and an arrangement of the segments such that the closed loop optical waveguide structure 104 is axisymmetric about one or more lines that pass through the center of the closed loop optical waveguide structure 104. In some embodiments, the closed loop optical waveguide structure 104 has a number of segments 108 and an arrangement of the segments such that the closed loop optical waveguide structure 104 is point symmetric, which means that the top view shape of the closed loop optical waveguide structure 104 has a number of points that are the same distance in opposite directions from a center point of the closed loop optical waveguide structure 104.

[0039] The closed loop optical waveguide structure 104 can be fabricated to have a radius (dimension Dl), to have a number of segments 108, to have a width (dimension D2) of each segment 108 as shown, Figure 1A to have a length (dimension D3) of each segment 108 as shown, Figure 1A to have an angle (dimension D4) between adjacent segments 108 as shown, Figure 1A and / or to have other characteristics to achieve a particular optical signal loss of the closed loop optical waveguide structure 104. In some embodiments, the number of segments 108, the width (dimension D2) of each segment 108, the length (dimension D3) of each segment 108, the angle (dimension D4) between adjacent segments 108, and / or another parameter of the closed loop optical waveguide structure 104 can be selected to achieve a particular radius (dimension Dl) of the closed loop optical waveguide structure 104. In some embodiments, the length (dimension D3) of each segment 108 and / or the angle (dimension D4) between adjacent segments 108 is based on the number of segments 108 included in the closed loop optical waveguide structure 104.

[0040] In addition, in Figure 1AIn the illustrated example, the widths (dimension D2) of the segments 108 are substantially equal, the lengths (dimension D3) of the segments 108 are substantially equal, and the angles (dimension D4) between adjacent segments 108 are substantially equal. In other examples, the widths (dimension D2) of two or more segments 108 of the closed-loop optical waveguide structure 104 are different widths, the lengths (dimension D3) of two or more segments 108 of the closed-loop optical waveguide structure 104 are different lengths, and / or the angles (dimension D4) between two or more sets of segments 108 of the closed-loop optical waveguide structure 104 are different angles.

[0041] As the optical signal transitions between the segments 108 of the closed-loop optical waveguide structure 104, segment-induced loss can occur at the junctions 110 between the segments 108. In particular, the change in direction of propagation that occurs at the junctions 110 between adjacent segments 108 can cause segment-induced loss in the optical signal. Segment-induced loss increases as the number of segments 108 decreases. In other words, for the same radius (dimension Dl), a smaller number of segments 108 results in greater segment-induced loss than a larger number of segments 108 because the angles (dimension D4) between adjacent segments 108 of the smaller number of segments 108 (resulting in a more drastic change in direction of the optical signal in the closed-loop optical waveguide structure 104) are smaller than the angles between adjacent segments 108 of the larger number of segments 108.

[0042] In some embodiments, a closed-loop optical waveguide structure 104 having a fixed number of segments 108 can have greater segment-induced loss if fabricated with a larger radius (dimension Dl) because the length (dimension D3) of each segment 108 increases as the radius (dimension Dl) increases. Thus, the number of segments 108 selected for a closed-loop optical waveguide structure 104 can be based on the radius (dimension Dl) of the closed-loop optical waveguide structure 104 and the intrinsic loss to be achieved for the closed-loop optical waveguide structure 104.

[0043] By controlling the parameters of the closed-loop optical waveguide structure 104 (e.g., the radius (dimension Dl), the number of segments 108, the widths (dimension D2) of the segments 108, the lengths (dimension D3) of the segments 108, and / or the angles (dimension D4) between the segments 108, among other parameters) to have an optical signal loss (e.g., an intrinsic loss) such that the closed-loop optical waveguide structure 104 reaches a critical coupling (or approaches a critical coupling), the extinction ratio (measured in dB) of the closed-loop optical waveguide structure 104 can be greater relative to an over-coupled condition or an under-coupled condition when the closed-loop optical waveguide structure 104 is at or near a critical coupling condition. The extinction ratio of the closed-loop optical waveguide structure 104 represents the ratio of the power of the optical signal in the on state to the power of the optical signal in the off state at λ centhe transmittance at the optical signal half maximum wavelength. In some cases, the extinction ratio can approach infinity when the closed-loop optical waveguide structure 104 is at or near the critical coupling condition.

[0044] Accordingly, the closed-loop optical waveguide structure 104 is fabricated to have a specific optical signal loss (e.g., intrinsic loss) that enables the Q-factor of the closed-loop optical waveguide structure 104 to be balanced with the power coupling coefficient of the closed-loop optical waveguide structure 104, which enables the closed-loop optical waveguide structure 104 to reach or approach the critical coupling. At the critical coupling or near critical coupling, the closed-loop optical waveguide structure 104 can achieve high efficient operation (e.g., modulation or filtering with minimal modulation imperfections and reduced power loss) and high selective optical filtering relative to over-coupling or under-coupling.

[0045] Figure 1A Further shown is the location of the cross-sectional view shown in other figures contained herein. For example, Figures 5A-5F , Figures 6A-6F , Figures 7A-7D , Figures 8A-8D , Figures 9A-9E and / or Figures 10A-10D and other examples, is a cross-sectional view taken along line A-A in the x-direction that spans the bus optical waveguide structures 106a and 106b and the closed-loop optical waveguide structure 104 between the bus optical waveguide structures 106a and 106b.

[0046] Figure 1B A top view of another example embodiment 112 of the semiconductor photonic device 102 is shown, in which a plurality of closed-loop optical waveguide structures 104a and 104b are included between the bus optical waveguide structures 106a and 106b. This configuration enables the implementation of a cascade modulator photonic integrated circuit or a cascade resonator photonic integrated circuit in the semiconductor photonic device 102. Figure 1BExample embodiment 112 of the semiconductor photonic device 102 is an example of a serial cascaded photonic integrated circuit, wherein the bus optical waveguide structure 106a, the closed-loop optical waveguide structure 104a, the closed-loop optical waveguide structure 104b, and the bus optical waveguide structure 106b are optically coupled in series. This means that the bus optical waveguide structure 106a is directly optically coupled to the closed-loop optical waveguide structure 104a only (e.g., by evanescent coupling), the bus optical waveguide structure 106b is directly optically coupled to the closed-loop optical waveguide structure 104b only (e.g., by evanescent coupling), and the closed-loop optical waveguide structures 104a and 104b are directly optically coupled to each other (e.g., by evanescent coupling).

[0047] Bus optical waveguide structure 106a is adjacent to (and extends along) a first side of closed-loop optical waveguide structure 104a. A first side of closed-loop optical waveguide structure 104b is adjacent to a second side of closed-loop optical waveguide structure 104a, and the second side of closed-loop optical waveguide structure 104a is opposite to its first side. Bus optical waveguide structure 106b is adjacent to ( and extends along) a second side of closed-loop optical waveguide structure 104b, and the second side of closed-loop optical waveguide structure 104b is opposite to its first side. Therefore, bus optical waveguide structure 106a, closed-loop optical waveguide structure 104a, closed-loop optical waveguide structure 104b, and bus optical waveguide structure 106b are arranged in the x-direction within semiconductor photonic device 102.

[0048] The semiconductor photonic device 102 includes multiple closed-loop optical waveguide structures 104a and 104b, which can perform various functions. For example, the closed-loop optical waveguide structures 104a and 104b can be fabricated with different resonant frequencies, which can be used to generate wavelength division multiplexed (WDM) optical signals in the semiconductor photonic device 102. Furthermore and / or alternatively, the closed-loop optical waveguide structures 104a and 104b can be fabricated with different resonant frequencies to filter multiple frequencies in the semiconductor photonic device 102.

[0049] like Figure 1B As further shown, closed-loop optical waveguide structures 104a and 104b each have a polygonal top-view shape and each includes multiple segments 108 interconnected at connection points 110. This allows the optical loss (e.g., inherent loss) in each of the closed-loop optical waveguide structures 104a and 104b to be adjusted independently.

[0050] In some embodiments, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b both have the same radius ( Figure 1A The dimensions D1 in the middle all have the same segment width. Figure 1A The dimensions D2 in the middle all have the same segment length. Figure 1A The dimensions D3) and / or all have the same segment angle ( Figure 1A (Dimension D4 in the text). In some embodiments, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b have different radii (different dimension D1 values), different segment widths (different dimension D2 values), different segment lengths (different dimension D3 values), and / or different segment angles (different dimension D4 values).

[0051] Furthermore and / or alternatively, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b can be manufactured with different top-view orientations. For example, the closed-loop optical waveguide structure 104a can be manufactured with an octagonal top-view shape, while the closed-loop optical waveguide structure 104b can be manufactured with an octagonal top-view shape, which is rotated relative to the octagonal top-view shape of the closed-loop optical waveguide structure 104a.

[0052] Figure 1C A top view of another example embodiment 114 of the semiconductor photonic device 102 is shown, which is similar to... Figure 1B The example embodiment 112 of the semiconductor photonic device 102 shown is similar. However, in Figure 1C In example embodiment 114 of the semiconductor photonic device 102, the semiconductor photonic device 102 includes more than two closed-loop optical waveguide structures 104a-104n, wherein the closed-loop optical waveguide structures 104a-104n are optically coupled in series. The number of closed-loop optical waveguide structures 104a-104n is selectable, enabling the filtering of a specific number of optical signal frequencies and / or the generation of WDMs of a specific number of optical signal frequencies.

[0053] Figure 1D A top view of another example embodiment 116 of the semiconductor photonic device 102 is shown, which is similar to... Figure 1B The example embodiment 112 of the semiconductor photonic device 102 shown is similar. However, in Figure 1D In example embodiment 116 of the semiconductor photonic device 102, the semiconductor photonic device 102 includes a closed-loop optical waveguide structure 104a having a polygonal top-view shape and an annular closed-loop optical waveguide structure 104b adjacent to the closed-loop optical waveguide structure 104a, wherein a plurality of segments 108 of the polygonal top-view shape are interconnected at connection points 110 at opposite ends of the segments 108. In other words, the closed-loop optical waveguide structure 104b has an annular top-view shape.

[0054] Figure 1E A top view of another example embodiment 118 of the semiconductor photonic device 102 is shown, which is similar to... Figure 1B The example embodiment 112 of the semiconductor photonic device 102 shown is similar. However, in Figure 1E In Example Embodiment 118 of the semiconductor photonic device 102, the semiconductor photonic device 102 includes closed-loop optical waveguide structures 104a and 104b with different polygonal top-view shapes. For example, closed-loop optical waveguide structure 104a may have a dodecagonal top-view shape (e.g., it may have twelve (12) segments 108), while closed-loop optical waveguide structure 104b may have a hexagonal top-view shape (e.g., it may have six (6) segments 108).

[0055] As shown above, Figures 1A-1E This is provided as an example. Other examples may be related to... Figures 1A-1E The descriptions are different.

[0056] Figures 2A-2D This is a schematic diagram of an example embodiment of the example semiconductor photonic device 102 described herein. Figures 2A-2D Each of these shows a top view of an example embodiment of the semiconductor photonics device 102.

[0057] like Figure 2A As shown in Example Embodiment 200, the semiconductor photonic device 102 includes multiple closed-loop optical waveguide structures 104a and 104b between bus optical waveguide structures 106a and 106b. This arrangement enables the implementation of cascade modulator photonic integrated circuits or cascade resonator photonic integrated circuits in the semiconductor photonic device 102. Example embodiment 200 of the semiconductor photonic device 102 in Figure 2 is an example of a parallel cascaded photonic integrated circuit, in which bus optical waveguide structures 106a and 106b are each directly optically coupled in parallel to closed-loop optical waveguide structures 104a and 104b. This means that bus optical waveguide structure 106a is directly optically coupled to both closed-loop optical waveguide structures 104a and 104b on a first side (e.g., through evanescent coupling), while bus optical waveguide structure 106b is directly optically coupled to both closed-loop optical waveguide structures 104a and 104b on a second side (e.g., through evanescent coupling), with the second side opposite to the first side. Closed-loop optical waveguide structures 104a and 104b are not directly optically coupled, but are indirectly coupled through bus optical waveguide structures 106a and 106b.

[0058] In the parallel-type cascaded photonic integrated circuit, the bus optical waveguide structure 106a continues to extend alongside both of the closed-loop optical waveguide structures 104a and 104b on a first side of the closed-loop optical waveguide structures 104a and 104b. The bus optical waveguide structure 106b continues to extend alongside both of the closed-loop optical waveguide structures 104a and 104b on a second side of the closed-loop optical waveguide structures 104a and 104b. The closed-loop optical waveguide structures 104a and 104b are adjacent to each other in an x-direction in the semiconductor photonic device 102, and are located between the bus optical waveguide structures 106a and 106b in a y-direction in the semiconductor photonic device 102.

[0059] As Figure 2A Further shown, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b each have a polygonal top view shape, and each include a plurality of segments 108 that are interconnected to each other at connection points 110. This enables optical loss (e.g., intrinsic loss) in each of the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b to be independently adjusted.

[0060] In some embodiments, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b each have the same radius (D1 in FIG. 1), each have the same segment width (D2 in FIG. 1), each have the same segment length (D3 in FIG. 1), and / or each have the same segment angle (D4 in FIG. 1). In some embodiments, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b have different radii (different values of D1), have different segment widths (different values of D2), have different segment lengths (different values of D3), and / or have different segment angles (different values of D4). Figure 1A Figure 1A Figure 1A Figure 1A

[0061] Additionally and / or alternatively, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b can be fabricated to have different top view orientations, respectively. For example, the closed-loop optical waveguide structure 104a can be fabricated to have an octagonal top view shape, while the closed-loop optical waveguide structure 104b can be fabricated to have an octagonal top view shape that is rotated with respect to the octagonal top view shape of the closed-loop optical waveguide structure 104a.

[0062] Figure 2B A top view of another example embodiment 202 of a semiconductor photonic device 102 is shown, which is similar to the example embodiment 200 of the semiconductor photonic device 102 shown in FIG. 1. Figure 2A However, in the example embodiment 202, the closed-loop optical waveguide structure 104a has a different radius (D1 in FIG. 2) than the closed-loop optical waveguide structure 104b. Figure 2B ​​​​In example embodiment 202 of the semiconductor photonic device 102, the semiconductor photonic device 102 includes more than two closed-loop optical waveguide structures 104a-104n, wherein the closed-loop optical waveguide structures 104a-104n are arranged in the x-direction and optically coupled in parallel with bus optical waveguide structures 106a and 106b. The number of closed-loop optical waveguide structures 104a-104n can be selected to achieve filtering of a specific number of optical signal frequencies and / or to achieve WDM of a specific number of optical signal frequencies.

[0063] Figure 2C A top view of another example embodiment 204 of the semiconductor photonic device 102 is shown, which is similar to... Figure 2A Example embodiment 200 of the semiconductor photonic device 102 shown. However, in Figure 2C In example embodiment 204 of the semiconductor photonic device 102, the semiconductor photonic device 102 includes a closed-loop optical waveguide structure 104a having a polygonal top-view shape and an annular closed-loop optical waveguide structure 104b adjacent to the closed-loop optical waveguide structure 104a, wherein a plurality of segments 108 of the polygonal top-view shape are interconnected at connection points 110 at opposite ends of the segments 108. In other words, the closed-loop optical waveguide structure 104b has an annular top-view shape.

[0064] Figure 2D A top view of another example embodiment 206 of the semiconductor photonic device 102 is shown, which is similar to... Figure 2A The semiconductor photonic device 102 shown in the example is similar to embodiment 200. However, in Figure 2D In an example embodiment 206 of the semiconductor photonic device 102, the semiconductor photonic device 102 includes closed-loop optical waveguide structures 104a and 104b with different polygonal top-view shapes. For example, closed-loop optical waveguide structure 104a may have a dodecagonal top-view shape (e.g., it may have twelve (12) segments 108), while closed-loop optical waveguide structure 104b may have a hexagonal top-view shape (e.g., it may have six (6) segments 108).

[0065] As shown above, Figures 2A-2D Provided as an example. Other examples may be related to... Figures 2A-2D The content described is different.

[0066] Figures 3A-3E This is a schematic diagram of an example embodiment of the example semiconductor photonic device 102 described herein. Figures 3A-3E Example embodiments of the semiconductor photonic device 102 shown and described, and Figures 1A-1E Similar to what is shown and described, except Figures 3A-3EExample embodiments of the semiconductor photonic device 102 shown and described each include at least one closed-loop optical waveguide structure 104 having a polygonal top-view shape, and a plurality of bus optical waveguide structures 106a and 106b, each bus optical waveguide structure 106a and 106b being at least symmetrical to a portion of the closed-loop optical waveguide structure 104. This allows the inherent losses in the bus optical waveguide structures 106a and 106b to be adjusted in a manner similar to the inherent losses in the closed-loop optical waveguide structure 104.

[0067] Figure 3A A top view of an example embodiment 300 of the semiconductor photonic device 102 is shown. Figure 3A As shown in the top view, the example embodiment 300 of the semiconductor photonic device 102 is similar to the example embodiment 100 of the semiconductor photonic device 102, except that in example embodiment 300, the bus optical waveguide structures 106a and 106b of the semiconductor photonic device 102 each have a polygonal top view. Therefore, the bus optical waveguide structures 106a and 106b also include a plurality of segments 108 connected at the ends of the segments 108 at connection point 110. The number of segments 108 in the bus optical waveguide structure 106a can be an odd number (e.g., 5 segments, 17 segments) or an even number (e.g., 10 segments, 20 segments). Similarly, the number of segments 108 in the bus optical waveguide structure 106b can be an odd number (e.g., 5 segments, 17 segments) or an even number (e.g., 10 segments, 20 segments). In some embodiments, bus optical waveguide structures 106a and 106b each have the same number of segments 108. In some embodiments, bus optical waveguide structures 106a and 106b have different numbers of segments 108.

[0068] The top view shape of each bus waveguide structure 106a and 106b can be symmetrical to a portion of the top view shape of the closed loop waveguide structure 104. For example, the closed loop waveguide structure 104 can have a top view shape that is approximately a dodecagon, and each of the bus waveguide structures 106a and 106b can have a top view shape that is half a dodecagon. In some embodiments, the bus waveguide structure 106a and / or 106b has a number of segments 108 and an arrangement of the segments such that the bus waveguide structure 106a and / or 106b is axisymmetric about one or more lines that pass through the center of the bus waveguide structure 106a and / or 106b. In some embodiments, the bus waveguide structure 106a and / or 106b has a number of segments 108 and an arrangement of the segments such that the bus waveguide structure 106a and / or 106b is point-symmetric, which means that the top view shape of the bus waveguide structure 106a and / or 106b has a number of points that are the same distance away from a center point of the bus waveguide structure 106a and / or 106b in opposite directions.

[0069] The top view shape of the bus waveguide structures 106a and 106b can be mirror images of each other (e.g., mirror images in the x-direction and along the y-direction) and mirror images relative to the side of the closed loop waveguide structure 104 adjacent to the bus waveguide structures 106a and 106b. Thus, the center point 302 of the bus waveguide structure 106a is adjacent to a first side of the closed loop waveguide structure 104, and the end point 304 of the bus waveguide structure 106a faces away from the first side of the closed loop waveguide structure 104. The center point 302 of the bus waveguide structure 106b is adjacent to a second side of the closed loop waveguide structure 104, which is opposite the first side, and the end point 304 of the bus waveguide structure 106b faces away from the first side of the closed loop waveguide structure 104.

[0070] Figure 3B A top view of an example embodiment 306 of the semiconductor photonic device 102 is shown. As shown in the top view in Figure 3B The example embodiment 306 is similar to the example embodiment 300 in Figure 3A except that the bus waveguide structures 106a and 106b in the example embodiment 306 in Figure 3B are rotated relative to the bus waveguide structures 106a and 106b of the example embodiment 300 in Figure 3A Thus, compared to the embodiment 300 in Figure 3A the center points 302 of the bus waveguide structures 106a and 106b are not aligned in the x-direction, and the connection points 110 between the segments 108 of each bus waveguide structure 106a and 106b are adjacent to the closed loop waveguide structure 104.

[0071] Figure 3CA top view of another example embodiment 308 of the semiconductor photonic device 102 is shown, in which a plurality of closed-loop optical waveguide structures 104a and 104b are included between the bus optical waveguide structures 106a and 106b. This arrangement enables a cascade modulator photonic integrated circuit or a cascade resonator photonic integrated circuit to be implemented in the semiconductor photonic device 102. As shown in Figure 3C Further shown, the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b each have a top view shape of a polygon, and each include a plurality of segments 108 interconnected at junction points 110. This enables optical loss (e.g., intrinsic loss) in each of the closed-loop optical waveguide structure 104a and the closed-loop optical waveguide structure 104b to be independently adjusted.

[0072] Figure 3D A top view of another example embodiment 310 of the semiconductor photonic device 102 is shown, which is similar to the example embodiment 308 of the semiconductor photonic device 102 shown and described in Figure 3C However, in the example embodiment 310 of the semiconductor photonic device 102 in Figure 3D The example embodiment 310 of the semiconductor photonic device 102 in includes the closed-loop optical waveguide structure 104a having a top view shape of a polygon, and the ring-shaped closed-loop optical waveguide structure 104b adjacent to the closed-loop optical waveguide structure 104a, in which a plurality of segments 108 of the top view shape of the polygon are interconnected at junction points 110 at opposite ends of the segments 108.

[0073] Figure 3E A top view of another example embodiment 312 of the semiconductor photonic device 102 is shown, which is similar to the example embodiment 308 of the semiconductor photonic device 102 shown and described in Figure 3C However, in the example embodiment 312 of the semiconductor photonic device 102 in Figure 3E The example embodiment 312 of the semiconductor photonic device 102 in includes the closed-loop optical waveguide structure 104a and 104b having different top view shapes of polygons. For example, the closed-loop optical waveguide structure 104a can have a top view shape of a dodecagon (e.g., can have twelve (12) segments 108), and the closed-loop optical waveguide structure 104b can have a top view shape of a hexagon (e.g., can have six (6) segments 108).

[0074] As shown above, Figures 3A-3E Examples are provided as a representative. Other examples can differ from what is described. Figures 3A-3E For example, some examples described with respect to the

[0075] Figures 4A-4E A schematic diagram of an example embodiment of the example semiconductor photonic device 102 described herein. Figures 4A-4E The example embodiments of the semiconductor photonic device 102 shown and described in are similar to the example embodiments of the semiconductor photonic device 102 shown and described in Figures 1A-1ESimilar to that shown and described in Figures 4A-4E Each of the example embodiments of the semiconductor photonic device 102 shown and described in

[0076] Figure 4A A top view and associated cross-sectional view along line A-A of an example embodiment 400 of the semiconductor photonic device 102 is shown. As shown in the top view of Figure 4A The closed-loop optical waveguide structure 104 of the semiconductor photonic device 102 has a top view shape that is polygonal, including a plurality of segments 108 that are connected to one another at connection points 110 at opposite ends of the segments 108. The bus optical waveguide structure 106a can be positioned over a first portion of the closed-loop optical waveguide structure 104 on a first side of the closed-loop optical waveguide structure 104, such that the first portion of the closed-loop optical waveguide structure 104 is aligned with the bus optical waveguide structure 106a in an x-direction in the semiconductor photonic device 102. The bus optical waveguide structure 106b can be positioned over a second portion of the closed-loop optical waveguide structure 104 on a second side of the closed-loop optical waveguide structure 104, the second side being opposite the first side. Thus, the second portion of the closed-loop optical waveguide structure 104 is aligned with the bus optical waveguide structure 106b in the x-direction in the semiconductor photonic device 102.

[0077] As shown in the cross-sectional view of Figure 4A The first portion of the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a can be vertically arranged in a z-direction in the semiconductor photonic device 102. Similarly, the second portion of the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106b can be vertically arranged in the z-direction in the semiconductor photonic device 102. The closed-loop optical waveguide structure 104 and the bus optical waveguide structures 106a and 106b can be contained within a dielectric layer 402 in the semiconductor photonic device 102. The dielectric layer 402 can contain one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Six N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials.

[0078] The closed-loop optical waveguide structure 104 can include a different material or a different composition of materials than the bus optical waveguide structures 106a and 106b. For example, the closed-loop optical waveguide structure 104 can include one or more semiconductor materials, while the bus optical waveguide structures 106a and 106b can each include one or more dielectric materials. As another example, the closed-loop optical waveguide structure 104 can include one or more dielectric materials, while the bus optical waveguide structures 106a and 106b can each include one or more semiconductor materials. Examples of these semiconductor materials include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with one or more types of dopants (e.g., p-type dopants, n-type dopants), germanium doped with one or more types of dopants, and / or other semiconductor materials. Examples of these dielectric materials include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxide doped with one or more types of dopants, silicon nitride doped with one or more types of dopants, and / or other dielectric materials.

[0079] In some embodiments, the z-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, the z-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are different distances.

[0080] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the bus optical waveguide structure 106b. In some embodiments, the thickness of the bus optical waveguide structure 106a is different from the thickness of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is different from the width of the bus optical waveguide structure 106b.

[0081] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106a is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is different from the width of the closed-loop optical waveguide structure 104.

[0082] In some embodiments, the thickness of the bus optical waveguide structure 106b is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106b is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is different from the width of the closed-loop optical waveguide structure 104.

[0083] Figure 4B A top view and a related cross-sectional view along line AA are shown for an example embodiment 404 of the semiconductor photonic device 102. Figure 4B As shown, Figure 4B Example embodiment 404 of the semiconductor photonic device 102 shown Figure 4A The example embodiment 400 of the semiconductor photonic device 102 shown is similar. However, in Figure 4B In the example embodiment 404 of the semiconductor photonic device 102 shown, bus optical waveguide structures 106a and 106b are horizontally adjacent to opposite sides of the closed-loop optical waveguide structure 104 in the x-direction. For example, bus optical waveguide structure 106a is horizontally adjacent to a first side of the closed-loop optical waveguide structure 104 in the x-direction, and bus optical waveguide structure 106b is horizontally adjacent to a second side of the closed-loop optical waveguide structure 104 in the x-direction, the second side being opposite to the first side.

[0084] Similar to Figure 4A Example embodiment 400 of the semiconductor photonic device 102 shown, the closed-loop optical waveguide structure 104 may include andFigure 4B The bus optical waveguide structures 106a and 106b in the example embodiment 404 of the semiconductor photonic device 102 are of different materials or different material compositions. For example, the closed-loop optical waveguide structure 104 can include one or more semiconductor materials, while the bus optical waveguide structures 106a and 106b can each include one or more dielectric materials. As another example, the closed-loop optical waveguide structure 104 can include one or more dielectric materials, while the bus optical waveguide structures 106a and 106b can each include one or more semiconductor materials. Examples of these semiconductor materials include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with one or more types of dopants (e.g., p-type dopants, n-type dopants), germanium doped with one or more types of dopants, and / or other semiconductor materials. Examples of these dielectric materials include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxide doped with one or more types of dopants, silicon nitride doped with one or more types of dopants, and / or other dielectric materials.

[0085] In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the x-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the x-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are different distances.

[0086] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the bus optical waveguide structure 106b. In some embodiments, the thickness of the bus optical waveguide structure 106a is different than the thickness of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is different than the width of the bus optical waveguide structure 106b.

[0087] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106a is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is different from the width of the closed-loop optical waveguide structure 104.

[0088] In some embodiments, the thickness of the bus optical waveguide structure 106b is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106b is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is different from the width of the closed-loop optical waveguide structure 104.

[0089] Figure 4C A top view and a related cross-sectional view along line AA are shown for an example embodiment 406 of the semiconductor photonic device 102. Figure 4C As shown, Figure 4C Example embodiment 406 of the semiconductor photonic device 102 shown Figure 4A The example embodiment 400 of the semiconductor photonic device 102 shown is similar. However, in Figure 4C In the example embodiment 406 of the semiconductor photonic device 102 shown, the bus optical waveguide structure 106a is horizontally adjacent to the first side of the closed-loop optical waveguide structure 104 in the x direction, while the bus optical waveguide structure 106b is vertically adjacent to the second side of the closed-loop optical waveguide structure 104 in the z direction.

[0090] Similar to Figure 4A Example embodiment 400 of the semiconductor photonic device 102 shown, the closed-loop optical waveguide structure 104 may include and Figure 4CThe bus optical waveguide structures 106a and 106b in the example embodiment 406 of the semiconductor photonic device 102 are shown to be of different materials or different material compositions. For example, the closed-loop optical waveguide structure 104 can include one or more semiconductor materials, while the bus optical waveguide structures 106a and 106b can each include one or more dielectric materials. As another example, the closed-loop optical waveguide structure 104 can include one or more dielectric materials, while the bus optical waveguide structures 106a and 106b can each include one or more semiconductor materials. Examples of such semiconductor materials include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with one or more types of dopants (e.g., p-type dopants, n-type dopants), germanium doped with one or more types of dopants, and / or other semiconductor materials. Examples of such dielectric materials include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxide doped with one or more types of dopants, silicon nitride doped with one or more types of dopants, and / or other dielectric materials.

[0091] In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are different distances.

[0092] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the bus optical waveguide structure 106b. In some embodiments, the thickness of the bus optical waveguide structure 106a is different than the thickness of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is different than the width of the bus optical waveguide structure 106b.

[0093] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106a is different than the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is different than the width of the closed-loop optical waveguide structure 104.

[0094] In some embodiments, the thickness of the bus optical waveguide structure 106b is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106b is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is different from the width of the closed-loop optical waveguide structure 104.

[0095] Figure 4D A top view and a related cross-sectional view along line AA are shown for an example embodiment 408 of a semiconductor photonic device 102. Figure 4D As shown, Figure 4D Example embodiment 408 of the semiconductor photonic device 102 shown Figure 4B The example embodiment 404 of the semiconductor photonic device 102 shown is similar. However, in Figure 4D In the example embodiment 408 of the semiconductor photonic device 102 shown, the bus optical waveguide structure 106a contains the same material and / or material composition as the closed-loop optical waveguide structure 104. For example, the bus optical waveguide structure 106a and the closed-loop optical waveguide structure 104 may each contain a semiconductor material, such as silicon (Si) or doped silicon, while the bus optical waveguide structure 106b may contain a dielectric material. Therefore, the bus optical waveguide structures 106a and 106b contain different materials and / or different material compositions.

[0096] In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the x-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are approximately the same. In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the x-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are different.

[0097] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same as the thickness of the bus optical waveguide structure 106b. In some embodiments, the thickness of the bus optical waveguide structure 106a is different from the thickness of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same as the width of the bus optical waveguide structure 106b. In some embodiments, the width of the bus optical waveguide structure 106a is different from the width of the bus optical waveguide structure 106b.

[0098] In some embodiments, the thickness of the bus optical waveguide structure 106a is approximately the same thickness as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106a is a different thickness than the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is approximately the same width as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106a is a different width than the width of the closed-loop optical waveguide structure 104.

[0099] In some embodiments, the thickness of the bus optical waveguide structure 106b is approximately the same thickness as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the thickness of the bus optical waveguide structure 106b is a different thickness than the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is approximately the same width as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the bus optical waveguide structure 106b is a different width than the width of the closed-loop optical waveguide structure 104.

[0100] Figure 4E A top view and a related cross-sectional view along line A-A of an example embodiment 410 of the semiconductor photonic device 102 is shown. As shown, Figure 4E Figure 4E The example embodiment 410 of the semiconductor photonic device 102 shown in FIG. 4B is similar to the example embodiment 406 of the semiconductor photonic device 102 shown in FIG. 4A. However, in the example embodiment 410 of the semiconductor photonic device 102 shown in FIG. 4B, the bus optical waveguide structure 106a includes the same material and / or material composition as the material and / or material composition of the closed-loop optical waveguide structure 104. For example, the bus optical waveguide structure 106a and the closed-loop optical waveguide structure 104 can each include a semiconductor material, such as silicon (Si) or doped silicon, while the bus optical waveguide structure 106b can include a dielectric material. Thus, the bus optical waveguide structures 106a and 106b include different materials and / or different material compositions. Figure 4C Figure 4E In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are different distances.

[0101] In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, the x-direction distance between the bus optical waveguide structure 106a and the first portion of the closed-loop optical waveguide structure 104, and the z-direction distance between the bus optical waveguide structure 106b and the second portion of the closed-loop optical waveguide structure 104, are different distances.

[0102] ​​In some embodiments, the thickness of bus optical waveguide structure 106a is substantially the same as the thickness of bus optical waveguide structure 106b. In some embodiments, the thickness of bus optical waveguide structure 106a is a different thickness than the thickness of bus optical waveguide structure 106b. In some embodiments, the width of bus optical waveguide structure 106a is substantially the same as the width of bus optical waveguide structure 106b. In some embodiments, the width of bus optical waveguide structure 106a is a different width than the width of bus optical waveguide structure 106b.

[0103] In some embodiments, the thickness of bus optical waveguide structure 106a is substantially the same as the thickness of closed-loop optical waveguide structure 104. In some embodiments, the thickness of bus optical waveguide structure 106a is a different thickness than the thickness of closed-loop optical waveguide structure 104. In some embodiments, the width of bus optical waveguide structure 106a is substantially the same as the width of closed-loop optical waveguide structure 104. In some embodiments, the width of bus optical waveguide structure 106a is a different width than the width of closed-loop optical waveguide structure 104.

[0104] In some embodiments, the thickness of bus optical waveguide structure 106b is substantially the same as the thickness of closed-loop optical waveguide structure 104. In some embodiments, the thickness of bus optical waveguide structure 106b is a different thickness than the thickness of closed-loop optical waveguide structure 104. In some embodiments, the width of bus optical waveguide structure 106b is substantially the same as the width of closed-loop optical waveguide structure 104. In some embodiments, the width of bus optical waveguide structure 106b is a different width than the width of closed-loop optical waveguide structure 104.

[0105] As shown above, Figures 4A-4E provided by way of example. Other examples can differ Figures 4A-4E from the one described.

[0106] Figures 5A-5F is a schematic representation of an example embodiment 500 of forming a semiconductor photonic device 102 (or portions thereof) described herein. In some embodiments, one or more semiconductor processing operations related to example embodiment 500 can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or wafer / chip transport tools, among other examples. In some embodiments, one or more semiconductor processing operations related to embodiment 500 can be performed to form one or more example embodiments of a semiconductor photonic device 102 schematically and described in Figures 1A-1E , Figures 2A-2D and / or Figures 3A-3E other embodiments.

[0107] Turning to Figure 5AA substrate 502 may be provided. The substrate 502 may include a silicon on insulator (SOI) substrate, which includes a semiconductor substrate 504 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a dielectric layer 506 (e.g., a buried oxide or bottom oxide (BOX) layer and / or another type of insulating layer) on and / or on the semiconductor substrate 504, and a semiconductor layer 508 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) on and / or on the dielectric layer 506.

[0108] Alternatively, the semiconductor substrate 504 can be provided as a semiconductor wafer, and a dielectric layer 506 can be formed on and / or on the semiconductor substrate 504 using deposition tools, and a semiconductor layer 508 can be formed on and / or on the dielectric layer 506. The dielectric layer 506 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. The first semiconductor layer 508 can be formed using CVD, PVD, epitaxial, and / or other types of deposition techniques.

[0109] like Figures 5B-5D As shown, multiple bus optical waveguide structures 106a and 106b, and a closed-loop optical waveguide structure 104 can be formed in the semiconductor layer 508. In some embodiments, the semiconductor layer 508 is etched using a pattern in the hard mask layer 510 to form the bus optical waveguide structures 106a and 106b and the closed-loop optical waveguide structure 104. Figure 5B As shown, a hard mask layer 510 can be formed on the semiconductor layer 508 using a deposition tool (e.g., using CVD, PVD and / or other types of deposition techniques).

[0110] like Figure 5C As shown, the hard mask layer 510 can be patterned. The hard mask layer 510 can be patterned using a photoresist layer. A photoresist layer can be formed on the hard mask layer 510 using a deposition tool with spin coating and / or other types of deposition techniques. An exposure tool can be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The pattern can be transferred to the hard mask layer 510 by etching the hard mask layer according to the pattern in the photoresist layer.

[0111] like Figure 5DAs shown, the semiconductor layer 508 can be etched using an etching tool to remove portions of the semiconductor layer 508 according to a pattern in the hard mask layer 510, thereby forming bus optical waveguide structures 106a and 106b and a closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a planarization tool removes the remaining portions of the hard mask layer 510 using chemical mechanical polishing (CMP) and / or other types of planarization techniques.

[0112] Figure 5D Example cross-sectional profiles of bus optical waveguide structures 106a and 106b and closed-loop optical waveguide structure 104 are further shown. Alternative embodiments of the bus optical waveguide structures 106a and 106b and / or closed-loop optical waveguide structure 104 are described below. Figures 11A-11C As shown in the figure, bus optical waveguide structures 106a and 106b may each include a strip waveguide having an approximately rectangular or approximately square cross-sectional shape. Closed-loop optical waveguide structure 104 may also have a strip waveguide cross-sectional profile. In some embodiments, closed-loop optical waveguide structure 104 may have terminals or contacts on opposite sides of the strip waveguide to allow a voltage to be applied to the closed-loop optical waveguide structure 104, thereby modifying the refractive index of the closed-loop optical waveguide structure 104 to modulate the optical signal.

[0113] like Figure 5E As shown in the top view of the semiconductor photonic device 102, the closed-loop optical waveguide structure 104 can be formed into a polygonal top view shape with multiple segments 108 connected at connection points 110 located at opposite ends of the segments 108, as in Figures 1A-1E , Figures 2A-2D and / or Figures 3A-3E Example embodiment of the closed-loop optical waveguide structure 104 shown.

[0114] like Figure 5FAs shown, additional material can be deposited for dielectric layer 506 to encapsulate bus optical waveguide structures 106a and 106b and closed-loop optical waveguide structure 104 within dielectric layer 506. Deposition tools can be used to deposit the additional material for dielectric layer 506 using CVD, PVD, oxidation (e.g., thermal oxidation) and / or other types of deposition techniques. In some embodiments, one or more additional semiconductor processing operations can be performed to deposit the additional material for dielectric layer 506. For example, shallow trench isolation (STI) substrate oxidation and / or high-density plasma (HDP) deposition operations can be performed using deposition tools to deposit the additional material for dielectric layer 506. As another example, after depositing the additional material for dielectric layer 506, chemical mechanical polishing (CMP) and / or other types of planarization operations can be performed using planarization tools to planarize dielectric layer 506.

[0115] As shown above, Figures 5A-5F Provided as an example. Other examples may be related to... Figures 5A-5F The content described is different.

[0116] Figures 6A-6F This is a schematic diagram of an exemplary embodiment 600 of forming a semiconductor photonic device 102 (or a portion thereof) as described herein. In some embodiments, one or more semiconductor processing operations associated with exemplary embodiment 600 may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or wafer / chip transport tools, and other examples. In some embodiments, one or more semiconductor processing operations associated with exemplary embodiment 600 may be performed to form one or more semiconductor photonic devices 102 (or a portion thereof). Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4D Example embodiments of the semiconductor photonic device 102 shown and described in the figures.

[0117] Transfer to Figure 6A A substrate 602 may be provided. The substrate 602 may include a semiconductor substrate 604, a dielectric layer 606, and a semiconductor layer 608, similar to the substrate 502 in example embodiment 500. Figure 6A As further shown, the hard mask layer 610 may be formed and patterned on the semiconductor layer 608, similar to the hard mask layer 510 in Example Embodiment 500. However, in Example Embodiment 600, the hard mask layer 610 is patterned to form the closed-loop optical waveguide structure 104 and the bus-only optical waveguide structure 106a (e.g., not for the bus optical waveguide structure 106b).

[0118] like Figure 6BAs shown, a portion of the semiconductor layer 608 is removed by etching a semiconductor layer 608 using an etching tool based on a pattern in the hard mask layer 610 to form a closed-loop optical waveguide structure 104, and a bus optical waveguide structure 106a is formed adjacent to the first side of the closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer is removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, the remaining portion of the hard mask layer 610 is removed using a planarization tool via CMP techniques and / or other types of planarization techniques. The closed-loop optical waveguide structure 104 may be formed with a polygonal top-view shape having a plurality of segments 108 connected at connection points 110 at opposite ends of the segments 108, such as... Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4D Examples of closed-loop optical waveguide structures 104 shown in examples.

[0119] like Figure 6C As shown, additional material for the dielectric layer 606 can be deposited around the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a. The additional material for the dielectric layer 606 can be deposited using deposition tools via CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. In some embodiments, CMP operations and / or other types of planarization operations can be performed using planarization tools to planarize the dielectric layer 606 after the deposition of the additional material.

[0120] like Figure 6DAs shown, a recess 612 can be formed in the dielectric layer 606. The recess 612 is formed laterally adjacent to a second side of the closed-loop optical waveguide structure 104 in the x-direction, the second side being opposite to a first side adjacent to the formed bus optical waveguide structure 106a. In some embodiments, the recess 612 is etched in the dielectric layer 606 using a pattern in a photoresist layer. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 606. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 606 based on the pattern to form the recess 612 in the dielectric layer 606. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as another technique to etch the dielectric layer 606 based on the pattern.

[0121] As shown, Figure 6E a dielectric material can be deposited in the recess 612 to form a bus optical waveguide structure 106b in the recess 612. Thus, the bus optical waveguide structure 106b is formed laterally adjacent to a second side of the closed-loop optical waveguide structure 104 in the x-direction, the second side being opposite to a first side adjacent to the formed bus optical waveguide structure 106a. A deposition tool can be used to deposit the dielectric material of the bus optical waveguide structure 106b using a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques. In some embodiments, a planarization tool can be used to perform a CMP operation and / or other types of planarization operations to planarize the bus optical waveguide structure 106b after additional material deposition of the dielectric material of the bus optical waveguide structure 106b.

[0122] As shown, Figure 6F additional material for the dielectric layer 606 can be deposited to encapsulate the closed-loop optical waveguide structure 104 and the bus optical waveguide structures 106a and 106b in the dielectric layer 606. A deposition tool can be used to deposit the additional material of the dielectric layer 606 using a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or other types of deposition techniques. In some embodiments, a planarization tool can be used to perform a chemical mechanical polishing (CMP) operation and / or other types of planarization operations to planarize the dielectric layer 606 after additional material deposition of the dielectric layer 606.

[0123] As shown above, Figures 6A-6F is provided by way of example. Other examples can differ from what is described Figures 6A-6F without departing from the spirit of the disclosure.

[0124] Figures 7A-7D is a schematic diagram of an example embodiment 700 of forming a semiconductor photonic device 102 (or portions thereof) described herein. In some embodiments, one or more semiconductor processing operations related to example embodiment 700 can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or wafer / chip transport tools, etc. In some embodiments, one or more semiconductor processing operations related to example embodiment 700 can be performed to form one or more example embodiments of a semiconductor photonic device 102 as shown and described in Figures 1A-1E 、 Figures 2A-2D 、 Figures 3A-3E and / or Figure 4B , etc.

[0125] Turning to Figure 7A , a substrate 702 can be provided. The substrate 702 can include a semiconductor substrate 704, a dielectric layer 706, and a semiconductor layer 708, similar to the substrate 502 in example embodiment 500. As further shown, a photoresist layer 710 can be formed on the semiconductor layer 708 and patterned, similar to the photoresist layer 510 in example embodiment 500. However, in example embodiment 700, the photoresist layer 710 is patterned only for forming the closed-loop optical waveguide structure 104, and not for forming the bus optical waveguide structures 106a and 106b. Figure 7A Further shown, a hardmask layer 710 can be formed on the semiconductor layer 708 and patterned, similar to the hardmask layer 510 in example embodiment 500. However, in example embodiment 700, the hardmask layer 710 is patterned only for forming the closed-loop optical waveguide structure 104, and not for forming the bus optical waveguide structures 106a and 106b.

[0126] As shown, the semiconductor layer 708 is etched according to the pattern in the hardmask layer 710 using an etching tool to remove portions of the semiconductor layer 708, thereby forming the closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the remaining photoresist layer portions are removed using a photoresist removal tool (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some embodiments, the remaining portions of the hardmask layer 710 are removed using a planarization tool employing a CMP technique and / or other types of planarization techniques. The closed-loop optical waveguide structure 104 can be formed to have a polygonal top view shape with a plurality of segments 108 connected at connection points 110 at opposite ends, as shown in example embodiments of a closed-loop optical waveguide structure 104 in Figure 7B 、 Figures 1A-1E 、 Figures 2A-2D 、 Figures 3A-3E and / or Figure 4B , etc.

[0127] As shown, the semiconductor layer 708 is etched according to the pattern in the hardmask layer 710 using an etching tool to remove portions of the semiconductor layer 708, thereby forming the closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the remaining photoresist layer portions are removed using a photoresist removal tool (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some embodiments, the remaining portions of the hardmask layer 710 are removed using a planarization tool employing a CMP technique and / or other types of planarization techniques. The closed-loop optical waveguide structure 104 can be formed to have a polygonal top view shape with a plurality of segments 108 connected at connection points 110 at opposite ends, as shown in example embodiments of a closed-loop optical waveguide structure 104 in Figure 7CAs shown, additional material for dielectric layer 706 can be deposited around closed-loop optical waveguide structure 104. Deposition tools can be used to deposit the additional material for dielectric layer 706 using CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. In some embodiments, planarization tools can be used to perform CMP operations and / or other types of planarization operations to planarize dielectric layer 706 after the deposition of additional material.

[0128] like Figure 7C Further, a plurality of grooves 712 may be formed in the dielectric layer 706. A first groove 712 is formed laterally adjacent to a first side of the closed-loop optical waveguide structure 104 in the x-direction. A second groove 712 is formed laterally adjacent to a second side of the closed-loop optical waveguide structure 104 in the x-direction, the second side being opposite to the first side adjacent to the formed first groove 712. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric layer 706 to form the grooves 712. In these embodiments, a photoresist layer may be formed on the dielectric layer 706 using a deposition tool. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer 706 according to the pattern to form the grooves 712 in the dielectric layer 706. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as another technique for pattern-based etching of the dielectric layer 706.

[0129] In some embodiments, the distance between the first groove 712 and the first side of the closed-loop optical waveguide structure 104, and the distance between the second groove 712 and the second side of the closed-loop optical waveguide structure 104, are approximately the same. In some embodiments, the distance between the first groove 712 and the first side of the closed-loop optical waveguide structure 104, and the distance between the second groove 712 and the second side of the closed-loop optical waveguide structure 104, are different.

[0130] In some embodiments, the depth of the first groove 712 and the depth of the second groove 712 are approximately the same. In some embodiments, the depth of the first groove 712 and the depth of the second groove 712 are different. In some embodiments, the width of the first groove 712 and the width of the second groove 712 are approximately the same. In some embodiments, the width of the first groove 712 and the width of the second groove 712 are different.

[0131] In some embodiments, the depth of the first groove 712 is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the depth of the first groove 712 is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the first groove 712 is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the first groove 712 is different from the width of the closed-loop optical waveguide structure 104.

[0132] In some embodiments, the depth of the second groove 712 is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the depth of the second groove 712 is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the second groove 712 is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the second groove 712 is different from the width of the closed-loop optical waveguide structure 104.

[0133] like Figure 7D As shown, dielectric material can be deposited in the groove 712 to form bus optical waveguide structures 106a and 106b. Dielectric material can be deposited in the first groove 712 to form bus optical waveguide structure 106a, which is laterally adjacent to a first side of closed-loop optical waveguide structure 104 in the x-direction. Dielectric material can be deposited in the second groove 712 to form bus optical waveguide structure 106b, which is laterally adjacent to a second side of closed-loop optical waveguide structure 104 in the x-direction, the second side being opposite to the first side. The dielectric material of bus optical waveguide structures 106a and 106b can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation) and / or other types of deposition techniques. In some embodiments, a planarization tool may be used to perform CMP operations and / or other types of planarization operations to planarize the bus optical waveguide structures 106a and 106b after additional material has been deposited for the dielectric material of the bus optical waveguide structures 106a and 106b.

[0134] like Figure 7D Further, additional material can be deposited for dielectric layer 706 to encapsulate closed-loop optical waveguide structure 104 and bus optical waveguide structures 106a and 106b within dielectric layer 706. The additional material for dielectric layer 706 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. In some embodiments, planarization tools can be used to perform CMP operations and / or other types of planarization operations to planarize dielectric layer 706 after the deposition of additional material.

[0135] As mentioned above, Figures 7A-7DProvided by way of example only. Other examples can differ Figures 7A-7D as described.

[0136] Figures 8A-8D schematic diagram of an example embodiment 800 of forming a semiconductor photonic device 102 (or portions thereof) as described herein. In some embodiments, one or more semiconductor processing operations related to example embodiment 800 can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or wafer / chip transport tools, etc. In some embodiments, one or more semiconductor processing operations related to example embodiment 800 can be performed to form example embodiments of one or more semiconductor photonic devices 102 as shown in the descriptions and illustrations related to Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4E example embodiments of one or more semiconductor photonic devices 102 as shown in the descriptions and illustrations related to

[0137] Turning to Figure 8A , a substrate 802 can be provided. The substrate 802 can include a semiconductor substrate 804, a dielectric layer 806, and a semiconductor layer 808, similar to the substrate 502 in example embodiment 500. As Figure 8A further shown, a hardmask layer 810 can be formed on the semiconductor layer 808 and patterned, similar to the hardmask layer 510 in example embodiment 500. However, in example embodiment 800, the hardmask layer 810 is patterned for forming the closed-loop optical waveguide structure 104 and only the bus optical waveguide structure 106a (e.g., not for the bus optical waveguide structure 106b).

[0138] As Figure 8B shown, the semiconductor layer 808 is etched using an etching tool by removing portions of the semiconductor layer 808 to form the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a adjacent to the first side of the closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a remaining portion of the photoresist layer is removed using a photoresist removal tool (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some embodiments, a remaining portion of the hardmask layer 810 is removed using a planarization tool using a CMP technique and / or other types of planarization techniques. The closed-loop optical waveguide structure 104 can be formed to have a polygonal top view shape with a plurality of segments 108 connected at connection points 110 at opposite ends, as Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4EExample embodiments of the closed-loop optical waveguide structure 104 shown in the examples.

[0139] As shown in FIG. 8A, an additional material for a dielectric layer 806 can be deposited over the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a such that the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a are encapsulated in the dielectric layer 806. The additional material for the dielectric layer 806 can be deposited using a deposition tool using a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, a CMP operation and / or another type of planarization operation can be performed using a planarization tool to planarize the dielectric layer 806 after the additional material for the dielectric layer 806 is deposited. Figure 8C

[0140] As shown in FIG. 8B, a recess 812 can be formed in the dielectric layer 806. The recess 812 is formed over a second side of the closed-loop optical waveguide structure 104 that is opposite a first side that is adjacent to the formed bus optical waveguide structure 106a. In some embodiments, the dielectric layer 806 is etched using a pattern of a photoresist layer to form the recess 812. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 806. An exposure tool can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 806 based on the pattern to form the recess 812 in the dielectric layer 806. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as another technique to etch the dielectric layer 806 based on the pattern. Figure 8C In some embodiments, a z-direction distance between the recess 812 and the second side of the closed-loop optical waveguide structure 104, and an x-direction distance between the bus optical waveguide structure 106a and the first side of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, the z-direction distance between the recess 812 and the second side of the closed-loop optical waveguide structure 104, and the x-direction distance between the bus optical waveguide structure 106a and the first side of the closed-loop optical waveguide structure 104, are different distances.

[0141]

[0142] ​​In some embodiments, the depth of the groove 812 is approximately the same as the thickness of the bus optical waveguide structure 106a. In some embodiments, the depth of the groove 812 is different from the thickness of the bus optical waveguide structure 106a. In some embodiments, the width of the groove 812 is approximately the same as the width of the bus optical waveguide structure 106a. In some embodiments, the width of the groove 812 is different from the width of the bus optical waveguide structure 106a.

[0143] In some embodiments, the depth of the groove 812 is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the depth of the groove 812 is different from the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the groove 812 is approximately the same as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the groove 812 is different from the width of the closed-loop optical waveguide structure 104.

[0144] like Figure 8D As shown, dielectric material can be deposited in the groove 812 to form a bus optical waveguide structure 106b in the groove 812. Therefore, the bus optical waveguide structure 106b is formed on the second side of the closed-loop optical waveguide structure 104, such that the bus optical waveguide structure 106b is perpendicularly adjacent to the second side of the closed-loop optical waveguide structure 104 in the z-direction. The dielectric material of the bus optical waveguide structure 106b can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or another deposition technique. In some embodiments, a planarization tool can be used to perform a CMP operation and / or another planarization operation to planarize the bus optical waveguide structure 106b after additional material deposition of the dielectric material.

[0145] like Figure 8D As further shown, additional material can be deposited for dielectric layer 806 to encapsulate the bus optical waveguide structure 106b within dielectric layer 806. The additional material for dielectric layer 806 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. In some embodiments, planarization tools can be used to perform CMP operations and / or other types of planarization operations to planarize dielectric layer 806 after the deposition of the additional material.

[0146] As shown above, Figures 8A-8D Provided as an example. Other examples may be related to... Figures 8A-8D The content described is different.

[0147] Figures 9A-9EA schematic diagram of an example embodiment 900 of forming a semiconductor photonic device 102 (or portions thereof) is described herein. In some embodiments, one or more semiconductor processing operations related to example embodiment 900 can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or wafer / chip transport tools, etc. In some embodiments, one or more semiconductor processing operations related to example embodiment 900 can be performed to form example embodiments of one or more semiconductor photonic devices 102 shown in the descriptions and illustrations related to Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4C , etc.

[0148] Turning to Figure 9A , a substrate 902 can be provided. The substrate 902 can include a semiconductor substrate 904, a dielectric layer 906, and a semiconductor layer 908, similar to the substrate 502 in example embodiment 500. As Figure 9A Further shown, a hardmask layer 910 can be formed on the semiconductor layer 908 and patterned, similar to the hardmask layer 510 in example embodiment 500. However, in example embodiment 900, the hardmask layer 910 is only patterned for forming the closed-loop optical waveguide structure 104, but not for forming the bus optical waveguide structures 106a and 106b.

[0149] As Figure 9B shown, the semiconductor layer 908 is etched by removing portions of the semiconductor layer 908 according to the pattern in the hardmask layer 910 using an etching tool to form the closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the remaining portions of the photoresist layer are removed using a photoresist removal tool (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some embodiments, the remaining portions of the hardmask layer 910 are removed using a planarization tool with a CMP technique and / or other types of planarization techniques. The closed-loop optical waveguide structure 104 can be formed to have a polygonal top view shape with a plurality of segments 108 connected at connection points 110 at opposite ends, as shown in example embodiments of the closed-loop optical waveguide structure 104 in Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4C , etc.

[0150] As Figure 9CAs shown, additional material for the dielectric layer 906 can be deposited around the closed-loop optical waveguide structure 104. The additional material for the dielectric layer 906 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. In some embodiments, CMP operations and / or other types of planarization operations can be performed using planarization tools to planarize the dielectric layer 906 after the deposition of the additional material.

[0151] like Figure 9C Further, a groove 912 may be formed in the dielectric layer 906. This groove 912 may be formed laterally adjacent to a first side of the closed-loop optical waveguide structure 104 in the x-direction. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric layer 906 to form the groove 912. In these embodiments, a deposition tool may be used to form a photoresist layer on the dielectric layer 906. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer 906 based on the pattern to form the groove 912 in the dielectric layer 906. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as another technique for pattern-based etching of the dielectric layer 906.

[0152] like Figure 9D As shown, dielectric material can be deposited in the groove 912 to form a bus optical waveguide structure 106a, which is laterally adjacent to a first side of the closed-loop optical waveguide structure 104 in the x-direction. The dielectric material of the bus optical waveguide structure 106a can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation) and / or another deposition technique. In some embodiments, planarization tools can be used to perform CMP operations and / or another planarization operation to planarize the bus optical waveguide structure 106a after additional material deposition of the dielectric material.

[0153] like Figure 9DAs further shown, additional material for the dielectric layer 906 can be deposited to encapsulate the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a in the dielectric layer 906. The additional material for the dielectric layer 906 can be deposited using a deposition tool via a CVD technique, a PVD technique, an oxidation technique (e.g., a thermal oxidation technique), and / or another type of deposition technique. In some embodiments, a CMP operation and / or another type of planarization operation can be performed using a planarization tool to planarize the dielectric layer 906 after the additional material for the dielectric layer 906 is deposited.

[0154] As further shown, Figure 9D As further shown, after the additional material for the dielectric layer 906 can be deposited to encapsulate the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a, a recess 914 can be formed in the dielectric layer 906. The recess 914 is formed over a second side of the closed-loop optical waveguide structure 104 that is opposite a first side adjacent to the formed bus optical waveguide structure 106a. In some embodiments, the dielectric layer 906 is etched using a pattern in a photoresist layer to form the recess 914. In these embodiments, a photoresist layer can be formed on the dielectric layer 906 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 906 based on the pattern to form the recess 914 in the dielectric layer 906. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as another technique to etch the dielectric layer 906 based on the pattern.

[0155] As further shown, Figure 9E As further shown, after the additional material for the dielectric layer 906 can be deposited to encapsulate the closed-loop optical waveguide structure 104 and the bus optical waveguide structure 106a, a recess 914 can be formed in the dielectric layer 906. The recess 914 is formed over a second side of the closed-loop optical waveguide structure 104 that is opposite a first side adjacent to the formed bus optical waveguide structure 106a. In some embodiments, the dielectric layer 906 is etched using a pattern in a photoresist layer to form the recess 914. In these embodiments, a photoresist layer can be formed on the dielectric layer 906 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 906 based on the pattern to form the recess 914 in the dielectric layer 906. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as another technique to etch the dielectric layer 906 based on the pattern.

[0156] As further shown, Figure 9EFurther shown, additional material for the dielectric layer 906 can be deposited to encapsulate the bus optical waveguide structure 106b in the dielectric layer 906. The additional material for the dielectric layer 906 can be deposited using a deposition tool using CVD techniques, PVD techniques, oxidation techniques (e.g., thermal oxidation techniques), and / or other types of deposition techniques. In some embodiments, a CMP operation and / or other types of planarization operations can be performed using a planarization tool to planarize the dielectric layer 906 after the additional material for the dielectric layer 906 is deposited.

[0157] As shown above, Figures 9A-9E are merely examples. Other examples can differ from what is described Figures 9A-9E in this regard.

[0158] Figures 10A-10D is a schematic diagram of an example embodiment 1000 of forming a semiconductor photonic device 102 (or portions thereof) as described herein. In some embodiments, one or more semiconductor processing operations related to the example embodiment 1000 can be performed using one or more semiconductor processing tools, such as a deposition tool, an exposure tool, a development tool, an etch tool, a planarization tool, an ion implantation tool, and / or a wafer / chip transport tool, etc. In some embodiments, one or more semiconductor processing operations related to the example embodiment 1000 can be performed to form example embodiments of one or more semiconductor photonic devices 102 described and illustrated in one or more of the descriptions and illustrations related to Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4A example embodiments of one or more semiconductor photonic devices 102 described and illustrated in one or more of the descriptions and illustrations related to

[0159] Turning to Figure 10A , a substrate 1002 can be provided. The substrate 1002 can include a semiconductor substrate 1004, a dielectric layer 1006, and a semiconductor layer 1008, similar to the substrate 502 in the example embodiment 500. As Figure 10A Further shown, a hardmask layer 1010 can be formed on the semiconductor layer 1008 and patterned, similar to the hardmask layer 510 in the example embodiment 500. However, in the example embodiment 1000, the hardmask layer 1010 is patterned only to form the closed-loop optical waveguide structure 104 (e.g., and not to form the bus optical waveguide structures 106a and 106b).

[0160] As Figure 10BAs shown, the semiconductor layer 1008 is etched using an etching tool to remove portions of the semiconductor layer 1008 according to a pattern in the hard mask layer 1010, thereby forming a closed-loop optical waveguide structure 104. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, the remaining portions of the photoresist layer are removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, the remaining portions of the hard mask layer 1010 are removed using a planarization tool employing CMP techniques and / or other types of planarization techniques. The closed-loop optical waveguide structure 104 may be formed with a polygonal top-view shape having a plurality of segments 108 connected at connection points 110 at opposite ends, such as... Figures 1A-1E , Figures 2A-2D , Figures 3A-3E and / or Figure 4A Examples of closed-loop optical waveguide structures 104, as shown in other examples.

[0161] like Figure 10C As shown, additional material for the dielectric layer 1006 can be deposited on the closed-loop optical waveguide structure 104, such that the closed-loop optical waveguide structure 104 is encapsulated within the dielectric layer 1006. The additional material for the dielectric layer 1006 can be deposited using deposition tools employing CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. In some embodiments, CMP operations and / or other types of planarization operations can be performed using planarization tools to planarize the dielectric layer 1006 after the deposition of the additional material.

[0162] like Figure 10CFurther shown, a plurality of recesses 1012 can be formed in the dielectric layer 1006. A first recess 1012 is formed over a first side of the closed-loop optical waveguide structure 104. A second recess 1012 is formed over a second side of the closed-loop optical waveguide structure 104, the second side being opposite the first side with the first recess 1012 formed over the first side. In some embodiments, the dielectric layer 1006 is etched using a pattern in a photoresist layer to form the recesses 1012. In these embodiments, a deposition tool can be used to form the photoresist layer over the dielectric layer 1006. An exposure tool can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 1006 according to the pattern to form the recesses 1012 in the dielectric layer 1006. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as another technique to pattern etch the dielectric layer 1006.

[0163] In some embodiments, a distance between the first recess 1012 and the first side of the closed-loop optical waveguide structure 104, and a distance between the second recess 1012 and the second side of the closed-loop optical waveguide structure 104, are approximately the same distance. In some embodiments, a distance between the first recess 1012 and the first side of the closed-loop optical waveguide structure 104, and a distance between the second recess 1012 and the second side of the closed-loop optical waveguide structure 104, are different distances.

[0164] In some embodiments, a depth of the first recess 1012 is approximately the same as a depth of the second recess 1012. In some embodiments, a depth of the first recess 1012 is different than a depth of the second recess 1012. In some embodiments, a width of the first recess 1012 is approximately the same as a width of the second recess 1012. In some embodiments, a width of the first recess 1012 is different than a width of the second recess 1012.

[0165] In some embodiments, a depth of the first recess 1012 is approximately the same as a thickness of the closed-loop optical waveguide structure 104. In some embodiments, a depth of the first recess 1012 is different than a thickness of the closed-loop optical waveguide structure 104. In some embodiments, a width of the first recess 1012 is approximately the same as a width of the closed-loop optical waveguide structure 104. In some embodiments, a width of the first recess 1012 is different than a width of the closed-loop optical waveguide structure 104.

[0166] In some embodiments, the depth of the second recess 1012 is approximately the same as the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the depth of the second recess 1012 is different than the thickness of the closed-loop optical waveguide structure 104. In some embodiments, the width of the second recess 1012 is approximately the same width as the width of the closed-loop optical waveguide structure 104. In some embodiments, the width of the second recess 1012 is a different width than the width of the closed-loop optical waveguide structure 104.

[0167] As shown above, Figure 10D the dielectric material can be deposited in the recess 1012 to form bus optical waveguide structures 106a and 106b. The dielectric material can be deposited in the first recess 1012 to form the bus optical waveguide structure 106a over the first side of the closed-loop optical waveguide structure 104 such that the bus optical waveguide structure 106a is vertically adjacent to the first side of the closed-loop optical waveguide structure 104 in the z-direction. The dielectric material can be deposited in the second recess 1012 to form the bus optical waveguide structure 106b over the second side of the closed-loop optical waveguide structure 104 (e.g., opposite the first side) such that the bus optical waveguide structure 106b is vertically adjacent to the second side of the closed-loop optical waveguide structure 104 in the z-direction. The dielectric material of the bus optical waveguide structures 106a and 106b can be deposited using a deposition tool utilizing CVD techniques, PVD techniques, oxidation techniques (e.g., thermal oxidation techniques), and / or other types of deposition techniques. In some embodiments, a CMP operation and / or other types of planarization operations can be performed using a planarization tool to planarize the bus optical waveguide structures 106a and 106b after additional material deposition of the dielectric material of the bus optical waveguide structures 106a and 106b.

[0168] As shown above, Figure 10D additional material for the dielectric layer 1006 can be deposited to encapsulate the bus optical waveguide structures 106a and 106b in the dielectric layer 1006. The additional material of the dielectric layer 1006 can be deposited using a deposition tool utilizing CVD techniques, PVD techniques, oxidation techniques (e.g., thermal oxidation techniques), and / or other types of deposition techniques. In some embodiments, a CMP operation and / or other types of planarization operations can be performed using a planarization tool to planarize the dielectric layer 1006 after additional material deposition of the dielectric layer 1006.

[0169] As shown above, Figures 10A-10D are merely examples. Other examples can differ from what is described. Figures 10A-10D

[0170] Figures 11A-11C ​FIG. 1 illustrates a schematic diagram of an example embodiment of a cross-sectional profile of one or more waveguide structures described herein. The closed-loop optical waveguide structure 104 and / or the bus optical waveguide structure 106 (e.g., bus optical waveguide structure 106a, bus optical waveguide structure 106b) described herein can be fabricated to have one or more of the example embodiments of cross-sectional profiles shown in FIG. 1. Figures 11A-11C In some embodiments, the closed-loop optical waveguide structure 104 and / or the bus optical waveguide structure 106 (e.g., bus optical waveguide structure 106a, bus optical waveguide structure 106b) described herein can be fabricated to have another cross-sectional profile.

[0171] Figure 11A An example embodiment 1100 of a cross-sectional profile of a closed-loop optical waveguide structure 104 is shown. Figure 11A The cross-sectional profile in FIG. 1 100 can be referred to as a strip waveguide. The strip waveguide has a square cross-sectional profile or a rectangular cross-sectional profile and includes a strip of semiconductor material or dielectric material. The strip waveguide can be formed over a semiconductor substrate 1102 (which can correspond to semiconductor substrates 504, 604, 704, 804, 904, and / or 1004, among other examples) and over a dielectric layer 1104 (which can correspond to dielectric layers 402, 506, 606, 706, 806, 906, and / or 1006, among other examples).

[0172] Figure 11B An example embodiment 1106 of a cross-sectional profile of a closed-loop optical waveguide structure 104 is shown. Figure 11B The cross-sectional profile in FIG. 1 106 can be referred to as a rib waveguide. The rib waveguide includes a strip portion 1108 on top of a planar portion 1110, where the planar portion laterally extends outward in the x-direction beyond the strip portion 1108 on opposite sides of the strip portion 1108. In some embodiments, an extension portion 1112 can also be included on the planar portion 1110 and adjacent to the strip portion 1108. The extension portion 1112 can include the same material and / or material composition as the strip portion 1108. Alternatively, the extension portion 1112 and the strip portion 1108 can include different materials and / or different material compositions.

[0173] Figure 11C An example embodiment 1114 of a cross-sectional profile of a closed-loop optical waveguide structure 104 is shown. Figure 11C The cross-sectional profile in FIG. 1 114 can be referred to as a deep rib waveguide. The deep rib waveguide includes a strip portion 1108 on top of a planar portion 1110, where the planar portion laterally extends outward in the x-direction beyond the strip portion 1108 on opposite sides of the strip portion 1108. Figure 11C The cross-sectional profile of the deep rib waveguide shown in FIG. 1 114 is similar to the cross-sectional profile of the rib waveguide shown in FIG. 1 106. Figure 11BThe difference between the cross-sectional profiles of the ridge waveguides shown is that Figure 11C The difference between the thickness of the strip portion 1108 and the thickness of the planar portion 1110 in the deep-ridge waveguide cross-sectional profile shown can be less than Figure 11B The difference between the thickness of the strip portion 1108 and the thickness of the planar portion 1110 in the ridge waveguide cross-sectional profile shown. Figure 11C The thickness of the planar portion 1110 in the deep-ridge waveguide cross-sectional profile shown can be greater than Figure 11B The thickness of the planar portion 1110 in the ridge waveguide cross-sectional profile shown, and / or Figure 11C The thickness of the strip portion 1108 in the deep-ridge waveguide cross-sectional profile shown can be less than Figure 11B The thickness of the strip portion 1108 in the ridge waveguide cross-sectional profile shown.

[0174] As shown above, Figures 11A-11C are provided by way of example. Other examples can differ Figures 11A-11C from the examples described.

[0175] Figure 12 is a flow diagram of an example process 1200 related to forming a semiconductor photonic device described herein. In some embodiments, Figure 12 One or more of the process blocks of the process 1200 are performed using one or more semiconductor processing tools, such as a deposition tool, an exposure tool, a development tool, an etching tool, a planarization tool, an ion implantation tool, and / or a wafer / chip transport tool, among other examples.

[0176] As shown, Figure 12 The process 1200 can include forming a first optical waveguide structure having a first top-view shape over a semiconductor substrate of a semiconductor photonic device (block 1210). For example, one or more semiconductor processing tools can be used to form a first optical waveguide structure (e.g., bus optical waveguide structure 106a) having a first top-view shape over a semiconductor substrate (e.g., semiconductor substrate 504, 604, 704, 804, 904, and / or 1004) of a semiconductor photonic device 102, as described herein.

[0177] As further shown, Figure 12 The process 1200 can include forming a second optical waveguide structure having a second top-view shape over the semiconductor substrate (block 1220). For example, one or more semiconductor processing tools can be used to form a second optical waveguide structure (e.g., bus optical waveguide structure 106b) having a second top-view shape over the semiconductor substrate, as described herein.

[0178] As further shown, Figure 12It is further shown that process 1200 can include forming a third optical waveguide structure over the semiconductor substrate (block 1230). For example, one or more semiconductor processing tools can be used to form a third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) over the semiconductor substrate, as described herein. In some embodiments, the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) is positioned between the first optical waveguide structure (e.g., bus optical waveguide structure 106a) and the second optical waveguide structure (e.g., bus optical waveguide structure 106b). In some embodiments, the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) contains a third top-view shape having a plurality of segments 108. Segments 108 can be connected at connection points 110 at opposite ends of segments 108.

[0179] Process 1200 can include additional implementations, such as any single implementation of one or more other processes described below and / or elsewhere herein or any combination of any implementations of the processes.

[0180] In a first implementation, forming an optical waveguide structure (e.g., bus optical waveguide structure 106a) includes forming the first optical waveguide structure (e.g., bus optical waveguide structure 106a) from a semiconductor layer 508 positioned over the semiconductor substrate, forming a second optical waveguide structure (e.g., bus optical waveguide structure 106b) includes forming the second optical waveguide structure (e.g., bus optical waveguide structure 106b) from the semiconductor layer 508, and forming a third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) includes forming the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) from the semiconductor layer 508.

[0181] In a second implementation, alone or in combination with the first implementation, forming a first optical waveguide structure (e.g., bus optical waveguide structure 106a) includes forming the first optical waveguide structure (e.g., bus optical waveguide structure 106a) from a semiconductor layer 608 positioned over the semiconductor substrate, forming a third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) includes forming the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) from the semiconductor layer 608, and forming a second optical waveguide structure (e.g., bus optical waveguide structure 106b) includes depositing a dielectric material in a recess 612 horizontally adjacent to the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) to form the second optical waveguide structure (e.g., bus optical waveguide structure 106b).

[0182] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) includes forming the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) from a semiconductor layer 708 located above the semiconductor substrate, forming the first optical waveguide structure (e.g., the bus optical waveguide structure 106a) includes depositing a dielectric material in a first recess 712 horizontally adjacent to a first side of the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) to form the first optical waveguide structure (e.g., the bus optical waveguide structure 106a), and forming the second optical waveguide structure (e.g., the bus optical waveguide structure 106b) includes depositing a dielectric material in a second recess 712 horizontally adjacent to a second side of the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) opposite the first side to form the second optical waveguide structure (e.g., the bus optical waveguide structure 106b).

[0183] In a fourth embodiment, alone or in combination with one or more of the first through third embodiments, forming the first optical waveguide structure (e.g., the bus optical waveguide structure 106a) includes forming the first optical waveguide structure (e.g., the bus optical waveguide structure 106a) from a semiconductor layer 808 located above the semiconductor substrate, forming the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) includes forming the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) from the semiconductor layer, and forming the second optical waveguide structure (e.g., the bus optical waveguide structure 106b) includes depositing a dielectric material in a recess 812 vertically adjacent to the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) to form the second optical waveguide structure (e.g., the bus optical waveguide structure 106b).

[0184] In a fifth embodiment, alone or in combination with one or more of the first through fourth embodiments, forming the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) includes forming the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) from a semiconductor layer 908 located above the semiconductor substrate, forming the first optical waveguide structure (e.g., the bus optical waveguide structure 106a) includes depositing a dielectric material in a first recess 912 horizontally adjacent to a first side of the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) to form the first optical waveguide structure (e.g., the bus optical waveguide structure 106a), and forming the second optical waveguide structure (e.g., the bus optical waveguide structure 106b) includes depositing a dielectric material in a second recess 914 vertically adjacent to a second side of the third optical waveguide structure (e.g., the closed-loop optical waveguide structure 104) opposite the first side to form the second optical waveguide structure (e.g., the bus optical waveguide structure 106b).

[0185] In a sixth embodiment, alone or in combination with one or more of the first through fifth embodiments, forming the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) includes forming the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) from a semiconductor layer 1008 located above a semiconductor substrate, forming the first optical waveguide structure (e.g., bus optical waveguide structure 106a) includes depositing a dielectric material in a first recess 1012 vertically adjacent to a first side of the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) to form the first optical waveguide structure (e.g., bus optical waveguide structure 106a), and forming the second optical waveguide structure (e.g., bus optical waveguide structure 106b) includes depositing a dielectric material in a second recess 1012 vertically adjacent to a second side (opposite the first side) of the third optical waveguide structure (e.g., closed-loop optical waveguide structure 104) to form the second optical waveguide structure (e.g., bus optical waveguide structure 106b).

[0186] While Figure 12 Example blocks of the process 1200 are shown, in some embodiments, the process 1200 can include more blocks, fewer blocks, different blocks, or differently configured blocks than those depicted in FIG. 12. Additionally or alternatively, two or more of the blocks of the process 1200 can be performed in parallel. Figure 12

[0187] As such, the semiconductor photonic device includes a plurality of bus optical waveguide structures and one or more closed-loop optical waveguide structures arranged in a cascaded photonic integrated circuit, such as a cascaded resonator circuit. At least one of the closed-loop optical waveguide structures is fabricated to have a polygonal top view shape, where the closed-loop optical waveguide structure includes a plurality of segments. This allows the intrinsic loss of the closed-loop optical waveguide structure to be adjusted to achieve optical loss matching in the photonic integrated circuit.

[0188] As described above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes a first optical waveguide structure. The semiconductor photonic device includes a second optical waveguide structure. The semiconductor photonic device includes a third optical waveguide structure located between the first optical waveguide structure and the second optical waveguide structure, the third optical waveguide structure having a top view shape including a plurality of segments.

[0189] ​In some embodiments, a first segment of the plurality of segments at a first side of the third optical waveguide structure is adjacent to the first optical waveguide structure; and a second segment of the plurality of segments at a second side of the third optical waveguide structure is adjacent to the second optical waveguide structure, wherein the first side and the second side are opposite sides of the third optical waveguide structure. In some embodiments, the third optical waveguide structure is a first closed-loop optical waveguide structure in a semiconductor photonic device, the first closed-loop optical waveguide structure comprising a first top-view shape having a first plurality of segments; and the semiconductor photonic device further comprises: a second closed-loop optical waveguide structure adjacent to the first closed-loop optical waveguide structure, the second closed-loop optical waveguide structure comprising a second top-view shape having a second plurality of segments. In some embodiments, the first top-view shape and the second top-view shape are different top-view shapes. In some embodiments, the first closed-loop optical waveguide structure is adjacent to the first optical waveguide structure; wherein the second closed-loop optical waveguide structure is adjacent to the second optical waveguide structure; and the second closed-loop optical waveguide structure is between the first closed-loop optical waveguide structure and the second optical waveguide structure. In some embodiments, the first closed-loop optical waveguide structure is adjacent to the first optical waveguide structure at a first side of the first closed-loop optical waveguide structure and is adjacent to the second optical waveguide structure at a second side of the first closed-loop optical waveguide structure, the second side of the first closed-loop optical waveguide structure being opposite the first side of the first closed-loop optical waveguide structure; wherein the second closed-loop optical waveguide structure is adjacent to the first optical waveguide structure at a first side of the second closed-loop optical waveguide structure and is adjacent to the second optical waveguide structure at a second side of the second closed-loop optical waveguide structure, the second side of the second closed-loop optical waveguide structure being opposite the first side of the second closed-loop optical waveguide structure. In some embodiments, the third optical waveguide structure is a first closed-loop optical waveguide structure in a semiconductor photonic device; and the semiconductor photonic device further comprises: a second closed-loop optical waveguide structure adjacent to the first closed-loop optical waveguide structure, the second closed-loop optical waveguide structure comprising a ring top-view shape. In some embodiments, the first optical waveguide structure and the second optical waveguide structure have different material compositions. In some embodiments, the first optical waveguide structure comprises a semiconductor material; and the second optical waveguide structure comprises a dielectric material.

[0190] As described in more detail above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device comprises a first optical waveguide structure having a first top-view shape, the first top-view shape having a plurality of first segments. The semiconductor photonic device comprises a second optical waveguide structure having a second top-view shape, the second top-view shape having a plurality of second segments. The semiconductor photonic device comprises a third optical waveguide structure between the first optical waveguide structure and the second optical waveguide structure, the third optical waveguide structure having a third top-view shape, the third top-view shape having a plurality of third segments.

[0191] In some embodiments, the first top-view shape and the second top-view shape are each substantially symmetrical with at least a portion of the third top-view shape. In some embodiments, the first top-view shape and the second top-view shape are substantially mirror image top-view shapes. In some embodiments, the third optical waveguide structure is a first closed-loop optical waveguide structure, and the semiconductor photonic device further includes: a second closed-loop optical waveguide structure located between the first closed-loop optical waveguide structure and the second optical waveguide structure, wherein the second closed-loop optical waveguide structure includes a fourth top-view shape having a plurality of fourth segments.

[0192] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first optical waveguide structure having a first top-view shape over a semiconductor substrate of a semiconductor photonic device. The method includes forming a second optical waveguide structure having a second top-view shape over the semiconductor substrate. The method includes forming a third optical waveguide structure over the semiconductor substrate, wherein the third optical waveguide structure is located between the first optical waveguide structure and the second optical waveguide structure, and the third optical waveguide structure has a third top-view shape having a plurality of segments.

[0193] In some embodiments, forming the first optical waveguide structure includes forming the first optical waveguide structure from a semiconductor layer located above a semiconductor substrate; forming the second optical waveguide structure includes forming the second optical waveguide structure from the semiconductor layer; and forming the third optical waveguide structure includes forming the third optical waveguide structure from the semiconductor layer. In some embodiments, forming the first optical waveguide structure includes forming the first optical waveguide structure from a semiconductor layer located above a semiconductor substrate; forming the third optical waveguide structure includes forming the third optical waveguide structure from the semiconductor layer; and forming the second optical waveguide structure includes depositing a dielectric material in a recess horizontally adjacent to the third optical waveguide structure to form the second optical waveguide structure. In some embodiments, forming the third optical waveguide structure includes forming the third optical waveguide structure from a semiconductor layer located above a semiconductor substrate; forming the first optical waveguide structure includes depositing a dielectric material in a first recess horizontally adjacent to a first side of the third optical waveguide structure to form the first optical waveguide structure; and forming the second optical waveguide structure includes depositing a dielectric material in a second recess vertically adjacent to a second side of the third optical waveguide structure opposite the first side to form the second optical waveguide structure. In some embodiments, forming the first optical waveguide structure includes forming the first optical waveguide structure from a semiconductor layer located above a semiconductor substrate; forming the third optical waveguide structure includes forming the third optical waveguide structure from the semiconductor layer; and forming the second optical waveguide structure includes depositing a dielectric material in a recess vertically adjacent to the third optical waveguide structure to form the second optical waveguide structure. In some embodiments, forming the third optical waveguide structure includes forming the third optical waveguide structure from a semiconductor layer located above a semiconductor substrate; forming the first optical waveguide structure includes depositing a dielectric material in a first recess vertically adjacent to a first side of the third optical waveguide structure to form the first optical waveguide structure; and forming the second optical waveguide structure includes depositing a dielectric material in a second recess vertically adjacent to a second side of the third optical waveguide structure opposite the first side to form the second optical waveguide structure.

[0194] As used herein, “satisfies a threshold” can refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like, depending on the context.

[0195] The terms "about" and "substantially" can refer to a given value varying within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. It is to be understood that the terms "about" and "substantially" can refer to a percentage of a given value in view of the contents of the embodiments of the present disclosure.

[0196] The features of the embodiments described above can be better understood with reference to the drawings, from the detailed description that follows, and from the claims. A person skilled in the art should understand that the present disclosure can be used as a basis to design or modify other processes and structures in order to achieve the same objectives and / or to achieve the same advantages as the embodiments described herein. A person skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor photonic device, characterized by, comprising: a first optical waveguide structure; a second optical waveguide structure; and a third optical waveguide structure between the first optical waveguide structure and the second optical waveguide structure, the third optical waveguide structure comprising a top view shape having a plurality of segments. a first segment of the plurality of segments at a first side of the third optical waveguide structure is adjacent to the first optical waveguide structure; and 2. The semiconductor photonic device of claim 1, wherein wherein a second segment of the plurality of segments at a second side of the third optical waveguide structure is adjacent to the second optical waveguide structure, wherein the first side and the second side are opposite sides of the third optical waveguide structure. the third optical waveguide structure is a first closed-loop optical waveguide structure in the semiconductor photonic device, the first closed-loop optical waveguide structure comprising a first top view shape having a first plurality of segments; 3. The semiconductor photonic device of claim 1, wherein and wherein the semiconductor photonic device further comprises: a second closed-loop optical waveguide structure adjacent to the first closed-loop optical waveguide structure, the second closed-loop optical waveguide structure comprising a second top view shape having a second plurality of segments. the first top view shape and the second top view shape are different top view shapes.

4. The semiconductor photonic device of claim 3, wherein the first closed-loop optical waveguide structure is adjacent to the first optical waveguide structure; 5. The semiconductor photonic device of claim 3, wherein wherein the second closed-loop optical waveguide structure is adjacent to the second optical waveguide structure; and wherein the second closed-loop optical waveguide structure is between the first closed-loop optical waveguide structure and the second optical waveguide structure. the first closed-loop optical waveguide structure is adjacent to the first optical waveguide structure at a first side of the first closed-loop optical waveguide structure and is adjacent to the second optical waveguide structure at a second side of the first closed-loop optical waveguide structure, the second side of the first closed-loop optical waveguide structure being opposite the first side of the first closed-loop optical waveguide structure; 6. The semiconductor photonic device of claim 3, wherein, wherein the second closed-loop optical waveguide structure is adjacent to the first optical waveguide structure at a first side of the second closed-loop optical waveguide structure and is adjacent to the second optical waveguide structure at a second side of the second closed-loop optical waveguide structure, the second side of the second closed-loop optical waveguide structure being opposite the first side of the second closed-loop optical waveguide structure. the third optical waveguide structure is a first closed-loop optical waveguide structure in the semiconductor photonic device; and 7. The semiconductor photonic device of claim 1, wherein wherein the semiconductor photonic device further comprises: a second closed-loop optical waveguide structure adjacent to the first closed-loop optical waveguide structure, the second closed-loop optical waveguide structure comprising a ring top view shape. comprising:

8. A semiconductor photonic device, comprising: a first optical waveguide structure comprising a first top view shape having a first plurality of segments; a second optical waveguide structure comprising a second top view shape having a second plurality of segments; and a third optical waveguide structure between the first optical waveguide structure and the second optical waveguide structure, the third optical waveguide structure comprising a third top view shape having a third plurality of segments. the first top view shape and the second top view shape are each symmetrical with at least a portion of the third top view shape.

9. The semiconductor photonic device of claim 8, wherein, the first top view shape and the second top view shape are mirror image top view shapes.

10. The semiconductor photonic device of claim 8, wherein, ​

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