Digital low dropout voltage regulator circuit and power system

Abstract

Circuits and systems related to digital low dropout voltage regulators are provided. In an embodiment, a driver array of a digital low dropout voltage regulator is configured to output a supply voltage to a load, and an analog-to-digital converter is configured to compare the supply voltage to a reference voltage to determine a level difference between the supply voltage and the reference voltage. A digital controller is connected to the analog-to-digital converter and is configured to modulate a gate voltage supplied to the driver array based on a difference in level. In addition, the duty cycle control module is configured to modify a duty cycle of a gate voltage provided to the driver array.

Description

TECHNICAL FIELD

[0001] The present utility model relates to a circuit and system, and particularly to a digital low-dropout voltage regulator circuit and power system. BACKGROUND

[0002] In certain integrated circuits and power systems, it can be desirable to provide a stable voltage source to connected loads. To this end, a voltage regulator can be provided between the power source and the connected loads. Certain applications can use a digital low-dropout voltage regulator to achieve this functionality. SUMMARY

[0003] In an example circuit, a driver array comprising a plurality of transistors is configured to output a voltage source. The circuit further comprises an analog-to-digital converter configured to compare the voltage source to a reference voltage to determine a level difference between the voltage source and the reference voltage, a digital controller connected to the analog-to-digital converter, and a duty cycle control module configured to modify a duty cycle signal of the gate voltage provided to the driver array based on the level difference.

[0004] In an example system, a power source configured to provide an input / output (IO) voltage and a core voltage is connected to a digital low-dropout voltage regulator (DLVR). In this system, the DLVR is configured to receive a high voltage input from the power source and deliver an output voltage. The high voltage input is the IO voltage, and the power source is configured to provide the core voltage for computation. BRIEF DESCRIPTION OF DRAWINGS

[0005] The various embodiments of the present utility model will be best understood by reading a detailed description with reference to the drawings, in which:

[0006] Figure 1 is a circuit diagram illustrating a digital low-dropout voltage regulator (DLVR) circuit with duty cycle control according to an embodiment;

[0007] Figure 2 is a circuit diagram illustrating a power system according to an embodiment;

[0008] Figure 3 is a signal diagram illustrating duty cycle control behavior according to an embodiment;

[0009] Figure 4 is a circuit diagram of a DLVR driver array and a signal diagram showing input signals of the circuit according to an embodiment;

[0010] Figure 5 a table of SHE loss and current source capability for a circuit that is a function of low-dropout voltage and duty cycle control according to an embodiment;

[0011] Figure 6 a schematic diagram of a duty cycle control circuit according to an embodiment;

[0012] Figure 7 a signal diagram of a duty cycle control system according to an embodiment;

[0013] Figure 8 a circuit diagram of a duty cycle control circuit according to an embodiment;

[0014] Figure 9 a flowchart of a method of operating a digital low-dropout voltage regulator circuit according to an embodiment;

[0015] Figure 10 a flowchart of a method of regulating a voltage supplied to a load according to an embodiment.

[0016] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless context dictates otherwise. The figures are drawn for simplicity and for illustrating concepts underlying the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description of a first feature over or adjacent to a second feature, the example can include embodiments where the first feature and the second feature are formed in direct contact with each other, and can also include embodiments where additional features can be formed between the first feature and the second feature. The first and second features are such that the first and second features can not be directly in contact with each other. Additionally, the present disclosure can repeat certain previously described

[0018] Furthermore, spatially relative terms, such as "below", "above", "lower", "upper", "upward", "downward", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Some embodiments of the present disclosure will be described. Additional operations can be provided before, during, and / or after these described stages. Some stages described can be replaced or eliminated for different embodiments. Additional features can be added to the stages. Some features described below can be replaced or eliminated in different embodiments. Although some embodiments are discussed with reference to operations performed in a particular order, these operations can be performed in another logical order.

[0020] As described above, voltage regulators can be used to deliver a stable supply voltage to a coupled load. For example, in certain power systems, energy efficiency can be improved by regulating the supply voltage to various elements in the system, such as processors, artificial intelligence (AI) units, and other digital circuits. To achieve this, voltage regulators can be incorporated into circuits or systems.

[0021] The operation of a voltage regulator can be performed by taking an input voltage and producing a different output voltage that matches a desired level. Some voltage regulators are characterized by their dropout voltage, which refers to the difference between the input level and the output level at which the voltage regulator can no longer regulate. Thus, some voltage regulators begin to lose functionality when the input voltage begins to approach the output level. To provide sufficient regulation in these cases, certain integrated circuits and power systems can be used in digital low-dropout voltage regulators (DLVRs) to control the supply voltage provided to a coupled load.

[0022] In some embodiments, a DLVR includes a driver array and is configured to receive an input voltage from a power supply and deliver an output voltage with a desired level to a connected load. To maintain the output voltage at a stable level, some DLVRs include an analog-to-digital converter (A / D) and a digital controller to modulate the gate voltage of the driver array. The A / D converter can receive a reference voltage, which is set to the level that is to be provided to the load. The A / D converter and the controller can be configured to change the gate voltage of the driver array of the DLVR such that the output voltage of the driver array is approximately equal to the reference voltage. This, in turn, can maintain the supply voltage provided to the load at a specified level. DLVRs are efficient in lower voltage applications, but when connected to a high supply voltage, the dropout can increase, resulting in a decrease in the accuracy of the regulation.

[0023] In the embodiments described herein, the DLVR can be configured for high-voltage and high-speed operation. Additionally, the systems, circuits, and methods described herein can incorporate duty cycle control to dynamically output control phase to the DLVR's driver array. As a result, the systems, circuits, and methods described herein can reduce the risk of voltage fluctuations (low ΔV), reduce the risk of self-heating effect (SHE), and have the ability to provide a resilient current source.

[0024] Figure 1 This is a circuit diagram illustrating a digital low-dropout voltage regulator (DLVR) circuit with duty cycle control according to one embodiment. In the example circuit, the DLVR may include a driver array 101 configured to receive at least one input voltage and supply an output voltage V to a coupled load 110. OUT The driver array 101 may contain multiple transistors. The driver array may include a cascode configuration of its constituent elements.

[0025] In some embodiments, the plurality of transistors may include a plurality of transistor pairs, wherein the transistor pairs are arranged in parallel. Each pair may include a first transistor having a first drain / drain coupled to at least one input voltage and a second drain / drain coupled to the first drain / drain of a second transistor in the pair. The first transistor may also include a gate coupled to other components of the DLVR, which will be described in more detail in the following paragraphs. The second transistor may also include an output V OUT It is also coupled to the second drain / drain of load 110. The coupled load can be any type of resistive load, including but not limited to processors, AI units, or digital circuits. The second transistor may also include a gate coupled to a second input voltage.

[0026] In one embodiment, the first and second transistors may be p-type metal-oxide-semiconductor (PMOS) transistors. However, the driver array is not limited to this, and other transistor types may be included in different embodiments. The first PMOS transistor may be coupled to a first input voltage VDDHD at a first high level. The second PMOS transistor may be coupled to a second input voltage V MID The second input voltage V MID This can be a second level, lower than the first level. In an embodiment, the first input voltage can represent the input / output (IO) voltage domain of the power system. Dividing the input voltage into a high-voltage IO domain and a low core voltage domain allows the DLVR to be used in high-voltage and high-speed applications.

[0027] The circuit can also include an analog-to-digital converter 103 and a digital controller 105. The analog-to-digital converter 103 can have a first input that receives a reference voltage VREF. This reference voltage can be set to a particular level, allowing a desired level to be provided to the load 110. The analog-to-digital converter 103 is also connected to the output voltage VOUT of the driver array through a first level shifter 107. OUT The analog-to-digital converter 103, along with the digital controller 105, can control the gate voltages applied to the transistors of the driver array 101 to produce an output voltage VOUT at the desired level. The analog-to-digital converter 103 can compare the output voltage to the reference voltage and communicate a signal to the digital controller 105. The digital controller 105 can determine the difference between the output voltage and the reference voltage and can apply a digital algorithm to determine how the voltage applied to the driver array is to be adjusted. The signal from the digital controller 105 to the driver array 101 can pass through a second level shifter 109.

[0028] In an embodiment, the DLVR also includes a duty cycle control module 111 connected to a frequency control module 113. The frequency control module 113 can include any clock source capable of providing a reliable frequency, including but not limited to a ring oscillator. The duty cycle control module 111 can control the ON / OFF switching of the driver array 101. The DLVR can also include a capacitor 115 coupled in parallel with the load 110. By controlling the ON / OFF of the driver array 101, the duty cycle control implemented by the embodiments described herein can reduce the risk of voltage fluctuations and overheating.

[0029] Figure 2 is a circuit diagram of a power system according to an embodiment. DLVRs 210A and 210B can be included in the power system, and these DLVRs can be similar to those described above in relation to Figure 1 . In an embodiment, the power system is a high voltage power system. As shown Figure 2 , the power system can include a power source 215. The power source can be configured to supply current to a plurality of loads within the power system in order to power the plurality of loads. For example, each load can include a processor, an AI unit, or other digital circuitry of a system, and the power source 215 can be configured to supply operating current to each of these. In order to optimize power usage for the entire system, each load can be coupled to a particular DLVR circuit (e.g., a DLVR dedicated to that load) connected between the load and the power source. Although Figure 2 two DLVR circuits are shown connected to the power source 215, it should be understood that the power source can be coupled to any number of DLVRs.

[0030] Power supply 215 can provide an IO voltage and a core voltage. The IO voltage can be higher than the core voltage. A high voltage power system can separate the core voltage domain from the IO voltage domain. This can allow the core voltage to be provided to high speed operations and allow the use of an IO voltage source in high voltage applications. High speed operations using the core voltage can be used to monitor the power system and ensure proper distribution and performance. High voltage applications using the IO voltage can include providing the IO voltage as a high voltage signal VDDHD to a driver array of the DLVR of the power system. As described further below, the risk of applying a high (IO) voltage to the driver array of the DLVR can be mitigated by the duty cycle control solutions of the embodiments described herein.

[0031] Figure 3 is a signal diagram 301 of a duty cycle control behavior according to an embodiment. A duty cycle control system according to an embodiment can adjust the proportion of time that a gate signal is ON (referred to at some points herein as the “ON percentage,” or alternatively as the “duty cycle” of the signal) during a time period T. The signal period can be controlled by the frequency control module 113.

[0032] In one embodiment, duty cycle control can be implemented using binary weighting. As the number of ONs in the driver control bits increases, the proportion of time that the signal is ON also increases. The signal diagram 301 shows the duty cycle (ON percentage) along the y-axis, and the width of the modulating pulse along the x-axis. Binary weighting control can allow for precise, fine-grained control of the duty cycle. In a binary phase split according to an embodiment example, the duty cycle can be split into the following levels by turning on or off individual driver control bits: 3.125%; 6.25%; 12.5%; 25%; 50%; 75%; 87.5%. This precise duty cycle control can reduce the risk of voltage fluctuations and minimize SHE loss.

[0033] Figure 4 is a circuit diagram of a DLVR driver array according to an embodiment and a signal diagram showing the input signals to the circuit. As shown in the circuit diagram 403, the DLVR driver array can include a DLVR driver circuit 410 and a high voltage pre-driver circuit 412. The DLVR driver circuit 410 can be similar to the DLVR driver array described above in relation to Figure 1 and can include a pair of transistors M3, M4 connected between a high voltage input HV and an output voltage V OUT The transistors M3 and M4 can include PMOS transistors. The gate of transistor M4 can be connected to a voltage V MID , and the gate of transistor M3 can receive a voltage signal from the high voltage pre-driver circuit, which will be described in more detail below.

[0034] The high-voltage pre-driver circuit 412 may also include a pair of transistors M1 and M2. These transistors may include a PMOS transistor M1 and an N-type metal-oxide-semiconductor (NMOS) transistor M2. The PMOS transistor M1 may have a first drain / drain connected to the high-voltage rail HV and a second drain / drain connected to the first drain / drain of the NMOS transistor M2. Transistors M1 and M2 may each include a component coupled to the input voltage V. CTRL The gate. In one embodiment, the input voltage V CTRL It could be related to the above. Figure 1 The signal described is modulated by a digital controller and a duty cycle control module. Input voltage V CTRL The level shifter in the DLVR circuit can pass the signal to the high-voltage pre-driver circuit 412. Transistors M1 and M2 can be configured as complementary metal-oxide-semiconductor (CMOS) transistors. The high-voltage pre-driver circuit 412 can receive the input voltage V. CTRL and output voltage V GATE The first transistor M3 is passed to the DLVR driver circuit. The transistor M2 of the high-voltage pre-driver circuit 412 can also be connected to the high-voltage side ground terminal HGND.

[0035] Input voltage V CTRL The input voltage V can be modulated by the duty cycle control module as described above. Signal diagram 401 shows the input voltage V set by the duty cycle control module. CTRL The pulse signal can be transmitted to the high-voltage pre-driver circuit 412, which can further modulate the voltage applied to the DLVR driver circuit 410. According to the embodiment, the DLVR driver circuit with pre-driver can provide a lower risk of voltage fluctuations in the output voltage, and dynamic duty cycle control can reduce the stress on the driver array and reduce the effects of the self-heating effect (SHE).

[0036] Figure 5 Table 501 illustrates the SHE losses and current source capabilities of a circuit that functions as low dropout voltage and duty cycle control according to one embodiment. In Table 501, the first column plots the on-state of the input voltage provided by the aforementioned duty cycle control mechanism. The first row plots the dropout voltage of the DLVR according to the embodiment. Each box shows the SHE losses and current source capabilities that may occur based on the relevant duty cycle control and dropout voltage. SHE losses are expressed as temperature rise, while current source capability is expressed as a percentage of the maximum current that the component can deliver to the load.

[0037] The embodiments described herein can allow for SHE loss reduction through dynamic duty cycle control in order to optimize current source capability. For example, SHE loss is less than 5°C. Generally, SHE loss can increase as the voltage drop increases. As shown in the table, in order to offset this, duty cycle control can be employed so that a DLVR can be provided that operates at higher voltage differentials without exceeding a SHE loss of 5°C.

[0038] Figure 6 is a schematic diagram of a duty cycle control circuit according to an embodiment. In an embodiment, the duty cycle control circuit 600 can include a digital phase control circuit with a shift register. For example, the duty cycle control can include a ring oscillator 601, a down sampling circuit 603, a shift register 605, and a plurality of logic gates 607. Reference numeral 609 represents the output of the duty cycle control circuit 600 and can include different outputs. The level depends on the selected duty cycle.

[0039] In an embodiment, the ring oscillator 601 can operate as a frequency controller and set the frequency of the signal input to the down sampling circuit 603 and the shift register 605. The logic gates 607 can include AND gates. During operation, the down sampling circuit can output a signal with a reduced period than the input signal from the ring oscillator 601. The output of the down sampling circuit is provided to one input terminal of each of the plurality of logic gates. The shift register 605 can include a plurality of outputs, each output associated with a particular binary weight (e.g., 6.25%, 12.5%, 25%, 50% as shown). Each output of the shift register 605 can be connected to a second input of a particular AND gate. The plurality of logic gates 607 can in turn pass an output signal to the duty cycle control circuit output 609 based on the applied input signal. Figure 6

[0040] Figure 7 is a signal diagram of a duty cycle control system according to an embodiment. In an embodiment, the duty cycle control can be implemented through an analog phase control circuit with pulse width modulation. For example, the analog phase control circuit can include one or more comparators that compare an input triangular wave signal V TRI to expected levels V LVL1 , V LVL2 .

[0041] The signal diagram includes a first portion 701 that illustrates a triangular wave signal V TRI and two levels. As shown, as the signal ramps from a minimum to a maximum, it passes through the levels V LVL1 and V​LVL2 The same operation is performed when the signal is decreasing from the maximum to the minimum. The duty cycle control system according to an embodiment can use these as threshold voltages to generate pulses with widths corresponding to the periods when the level of the triangular wave signal is above V LVL1 and V LVL2 . The second portion 703 illustrates a first pulse width modulation output that sets the pulse width for the period when the signal is above the level V LVL2 . The third portion 705 illustrates a second pulse width modulation output that sets the pulse width for the period when the signal is above the level V

[0042] Figure 8 is a circuit diagram of a duty cycle control circuit 800 according to an embodiment. In the example circuit, the duty cycle control circuit 800 can include both a digital phase control circuit 815 and an analog phase control circuit 813. The digital phase control circuit 815 can include components similar to those described above with respect to Figure 6 . The control circuit 813 can include a comparator and can operate in a manner similar to that described above with respect to Figure 7 . The phase control can switch between digital control and analog control through a multiplexer (MUX) 817. The duty cycle control circuit can then pass a duty cycle control signal to the drivers 819 of the DLVR to provide a stable, regulated output voltage V OUT .

[0043] Figure 9 is a flowchart of a method of operating a digital low-dropout voltage regulator circuit according to an embodiment. The method can begin 901 by selecting a level to provide to a circuit including a DLVR. For example, the circuit can be a circuit as described above with respect to Figure 1 . The DLVR can be configured to receive an input voltage supply from a power source and pass an output voltage to a connected load.

[0044] In an embodiment, the DLVR circuit can operate at a high voltage, thus being a high-dropout voltage. However, operating at a high voltage can cause an unintended self-heating effect. To mitigate this, a duty cycle control module can be provided and can be configured to control the duty cycle (percentage of on time) of the gate signal provided to the DLVR.

[0045] To optimize its performance, at 903 the duty cycle of the gate signal to be provided to the driver array of the DLVR is also selected. The selected values of the supply voltage and the duty cycle can avoid the undesired (SHE) penalty.

[0046] In 905, the method provides the selected level and selected duty cycle to the DLVR to operate the circuit at a level that avoids SHE penalties. In one embodiment, these selected values ​​can tolerate any SHE loss of less than 5°C. These values ​​can be determined based on the above related... Figure 5 The selection is made based on the presented and described data. For example, the selected input voltage can result in a differential voltage of 200mV, and the ON percentage can be selected as 12.5%, thereby avoiding SHE penalties exceeding 5°C.

[0047] Figure 10 This is a flowchart illustrating a method for regulating the voltage supplied to a load according to one embodiment. The example method may begin at 1001, receiving input via a digital low-dropout voltage regulator (DLVR). The DLVR's driver array (e.g., as described above) Figure 1 The described driver array 101 can receive this voltage as input and can generate an output voltage to be delivered to the coupled load. This process continues at 1003, where the output voltage of the DLVR is compared with a reference voltage. In one embodiment, the DLVR can be connected in parallel with... Figure 1 In the circuits shown and described above, the comparison in 1001 can be performed by the analog-to-digital converter 103 to compare the output voltage V from the driver array 101. OUT It is performed in conjunction with the reference voltage VREF.

[0048] This method can then be connected to 1005, and the digital controller 105 can determine the output voltage V. OUT The difference between the reference voltage VREF and the reference voltage. Figure 1 As shown, the digital controller 105 can be connected to the driver array 101 via the level shifter 109. Based on the determined difference, the digital controller 105 can provide a modulated gate signal to the driver array 101 of the DLVR at 1007.

[0049] This circuit may also include a duty cycle control module 111, which may also be connected to the driver array 101 via a level shifter 109. At 1009, the duty cycle control module 111 may provide a duty cycle control signal to the DLVR.

[0050] This method can then be continued to 1011, and based on the received modulated gate signal and duty cycle control signal, the DLVR can generate a modified output voltage. This modified output voltage can then be provided to the connected load. This signal is also compared with a reference voltage VREF via an analog-to-digital converter, and their cycling can be performed as follows: Figure 10 The dashed line in the diagram indicates repetition. This method allows for an output voltage V. OUTapproximately equal to an expected voltage for connecting a load, thereby improving efficiency of the system.

[0051] Circuits, systems, and methods are described herein. In an example circuit, a driver array including a plurality of transistors is configured to output a voltage source. The circuit further includes an analog-to-digital converter configured to compare the voltage source to a reference voltage to determine a level difference between the voltage source and the reference voltage, a digital controller connected to the analog-to-digital converter, and a duty cycle control module configured to modulate a gate voltage provided to the driver array based on the level difference, and a duty cycle control module configured to modify a duty cycle signal of the gate voltage provided to the driver array.

[0052] In some embodiments, the circuit further includes a frequency control module connected to the duty cycle control module, wherein the frequency control module includes a ring oscillator.

[0053] In some embodiments, the gate voltage is a first gate voltage; and wherein the plurality of transistors includes a first transistor including a first drain / drain connected to a high voltage signal and a first gate configured to receive the first gate voltage, and a second transistor including a second gate configured to receive a second gate voltage, wherein a level of the second gate voltage is lower than a level of the high voltage signal.

[0054] In some embodiments, the analog-to-digital converter is connected to the driver array through a first level shifter; and the digital controller and the duty cycle control module are connected to the driver array through a second level shifter.

[0055] In some embodiments, the driver array includes a DLVR driver circuit and a high voltage pre-driver circuit.

[0056] In some embodiments, the high voltage pre-driver circuit receives an input voltage from the second level shifter and outputs the gate voltage to a first transistor of the DLVR driver circuit.

[0057] In some embodiments, the duty cycle control module includes a digital phase control circuit.

[0058] In some embodiments, the digital phase control circuit includes a reduced order sampling circuit and a shift register configured to receive a frequency input from a ring oscillator.

[0059] In some embodiments, the duty cycle control module includes an analog phase control circuit.

[0060] In some embodiments, the analog phase control circuit includes a comparator configured to provide pulse width modulation.

[0061] In some embodiments, the duty cycle control module includes a digital phase control circuit and an analog phase control circuit.

[0062] In some embodiments, the circuit further includes a multiplexer connected to the digital phase control circuit and the analog phase control circuit and configured to switch the duty cycle control module circuit between the digital phase control circuit and the analog phase control circuit.

[0063] In an example system, a power supply configured to provide an input / output (IO) voltage and a core voltage is connected to a digital low-dropout voltage regulator (DLVR). In this system, the DLVR is configured to receive a high voltage input from the power supply and deliver an output voltage. The high voltage input is the IO voltage, and the power supply is configured to provide the core voltage for computation.

[0064] In some embodiments, the DLVR is a first DLVR of a plurality of DLVRs; and the power supply is connected to each DLVR of the plurality of DLVRs.

[0065] In some embodiments, the system further includes a processor, an artificial intelligence (AI) unit, or a digital circuit; and the processor, the AI unit, or the digital circuit is configured to receive the output voltage.

[0066] In some embodiments, the DLVR includes a duty cycle control module.

[0067] In an example method of operating a circuit, a driver array of a digital low-dropout voltage regulator (DLVR) receives an input voltage and generates an output voltage. The output voltage is compared to a reference voltage and a difference between the output voltage and the reference voltage is determined. Based on this determined difference, a modulated gate signal is provided to the driver array of the DLVR. A duty cycle control signal is also provided to the driver array of the DLVR, and a modified output voltage is generated based on the modulated gate signal and the duty cycle control signal.

[0068] In some embodiments, the input voltage and the duty cycle control signal are selected such that the circuit maintains self-heating effect (SHE) losses at less than 5 °C.

[0069] In some embodiments, the input voltage is a high supply voltage.

[0070] In some embodiments, providing the duty cycle control signal is controlled using a binary weighting process that includes selecting a number of driver control bits that are in an ON state.

[0071] The foregoing has outlined rather broadly the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the conception and the specific embodiments disclosed as a basis for design or modification of other operations and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments presented herein. Those skilled in the art will also recognize the equivalents of the Laiture described herein which is within the scope of the present disclosure and which is intended to be covered.

Claims

1. A digital low-dropout voltage regulator circuit, comprising: comprises a plurality of transistors; an analog-to-digital converter configured to compare the supply voltage to a reference voltage to determine a level difference between the supply voltage and the reference voltage; a digital controller configured to modulate a gate voltage provided to the driver array based on the level difference; and a duty cycle control module configured to modify a duty cycle of the gate voltage provided to the driver array.

2. The circuit of claim 1, further comprising: a frequency control module connected to the duty cycle control module, wherein the frequency control module comprises a ring oscillator.

3. The circuit of claim 1, wherein the gate voltage is a first gate voltage; and wherein the plurality of transistors comprises a first transistor comprising a first drain / drain connected to a high voltage signal and a first gate configured to receive the first gate voltage; and a second transistor comprising a second gate configured to receive a second gate voltage, wherein the second gate voltage is lower than a level of the high voltage signal.

4. The circuit of claim 1, wherein the analog-to-digital converter is connected to the driver array through a first level shifter; and the digital controller and the duty cycle control module are connected to the driver array through a second level shifter.

5. The circuit of claim 4, wherein the driver array comprises a digital low-dropout voltage regulator driver circuit and a high voltage pre-driver circuit.

6. The circuit of claim 1, wherein the duty cycle control module comprises a digital phase control circuit.

7. The circuit of claim 1, wherein the duty cycle control module comprises an analog phase control circuit.

8. The circuit of claim 1, wherein the duty cycle control module comprises a digital phase control circuit and an analog phase control circuit.

9. The circuit of claim 8, further comprising a multiplexer connected to the digital phase control circuit and the analog phase control circuit and configured to switch the duty cycle control module circuit between the digital phase control circuit and the analog phase control circuit. comprises a power supply configured to provide an input / output voltage and a core voltage; and a digital low-dropout voltage regulator configured to receive a high voltage input from the power supply and generate an output voltage, 10. A power system characterized by, wherein the high voltage input is the input / output voltage, and the power supply is configured to provide the core voltage for computation. ​ ​ ​ ​

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