Power supply protection device and power supply system for engineering machinery

Abstract

The utility model relates to a power supply protection device and a power supply system for engineering machinery. The power supply protection device comprises a power supply input pin; a power output pin; the power management chip is configured to automatically enter a self-locking state when the input voltage at the power input pin is smaller than a set threshold value, and the power management chip comprises a wake-up pin; the wake-up circuit comprises a monitoring end, a feedback end and a wake-up output end, and the monitoring end is connected to the power supply input pin; the feedback end is connected to the power supply output pin; the wake-up output end is connected to the wake-up pin, and the wake-up circuit is configured to output a corresponding wake-up signal to the power management chip through the wake-up output end based on the voltage values at the monitoring end and the feedback end, so that the power management chip is released from the self-locking state. The power supply protection device can monitor and control the self-locking state of the PMIC through a simple circuit structure, and has the advantages of low cost, high reliability and quick response.

Description

TECHNICAL FIELD

[0001] The utility model relates to the power management field of engineering machinery, more specifically, the utility model relates to a power protection device and a power system comprising the device. BACKGROUND

[0002] A car-grade power management chip (PMIC) usually has a functional safety protection mechanism. That is, when the input power voltage is too low and the input current is too large, the power management chip can automatically identify and actively stop the output of the chip power, thereby realizing the protection of the chip itself and the circuit board.

[0003] The self-protection mechanism of such a power management chip is reasonable and effective for most application occasions, but chip manufacturers design chips for general scenarios to expand the chip sales object, which cannot cover the special needs of various sub-application markets. For some high-demand, harsh environment application occasions, for example, for engineering machinery controllers working in mines and tunnels, once the input power voltage is too low, the total power required by the controller will cause the input current to be too large. This low voltage and large current condition is easily misidentified by the PMIC as an "short circuit" fault of the input power, thereby triggering the power management chip to enter the functional safety protection mechanism and cutting off the power on the circuit board. Moreover, the PMIC output lock caused by the mis-triggering of the "short circuit protection" often needs to be sustained for tens of seconds and cannot be released, causing the engineering vehicle to be unable to move in an emergency working condition, thereby causing unnecessary risks. SUMMARY

[0004] The utility model provides a kind of power protection device, it is aimed at realizing the monitoring and control to PMIC self-lock state by simple circuit structure.

[0005] The first aspect of the utility model provides a power protection device, which comprises:

[0006] a power input pin connected to a vehicle power supply to receive power supply power from the vehicle power supply;

[0007] a power output pin connected to a load to be powered by the vehicle power supply;

[0008] a power management chip disposed between the power input pin and the power output pin and configured to automatically enter a self-lock state when the input voltage at the power input pin is less than a set threshold to interrupt the power supply path of the vehicle power supply to the load, the power management chip comprising a wake-up pin for releasing the self-lock state; and

[0009] a wake-up circuit, the wake-up circuit comprising a monitoring terminal, a feedback terminal and a wake-up output terminal, the monitoring terminal being connected to the power input pin for monitoring the input voltage at the power input pin, the feedback terminal being connected to the power output pin for detecting the output voltage at the power output pin, the wake-up output terminal being connected to a wake-up pin of the power management chip,

[0010] wherein the wake-up circuit is configured to output a wake-up signal to the power management chip via the wake-up output terminal based on the voltage values at the monitoring terminal and the feedback terminal, so as to make the power management chip release the self-locking state.

[0011] According to an optional embodiment, the wake-up circuit comprises a first switch tube, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein:

[0012] the first switch tube comprises a control terminal, a power input terminal and a power output terminal, and the power output terminal is connected to the wake-up output terminal of the wake-up circuit;

[0013] the first resistor is arranged between the monitoring terminal of the wake-up circuit and a first terminal of the third resistor;

[0014] the second resistor is arranged between the monitoring terminal of the wake-up circuit and the power input terminal of the first switch tube;

[0015] a second terminal of the third resistor is connected to the control terminal of the first switch tube;

[0016] a first terminal of the fourth resistor is connected to the power output terminal of the first switch tube, and a second terminal of the fourth resistor is grounded.

[0017] According to an optional embodiment, the first switch tube is selected from a group consisting of bipolar transistors, field effect transistors, junction field effect transistors and insulated gate bipolar transistors.

[0018] According to an optional embodiment, the wake-up circuit further comprises:

[0019] a first diode, a positive electrode of the first diode being grounded, and a negative electrode of the first diode being connected to the first terminal of the third resistor.

[0020] According to an optional embodiment, the wake-up circuit further comprises:

[0021] a second switch tube, the second switch tube comprising a control terminal, a power input terminal and a power output terminal, the power input terminal of the second switch tube being connected to the power output terminal of the first switch tube, and the power output terminal of the second switch tube being grounded;

[0022] a fifth resistor disposed between a control terminal of the second switch tube and a feedback terminal of the wake-up circuit; and

[0023] a sixth resistor, a first terminal of the sixth resistor connected to the control terminal of the second switch tube, a second terminal of the sixth resistor grounded.

[0024] According to an optional embodiment, the second switch tube is selected from a group comprising bipolar transistors, field effect transistors, junction field effect transistors and insulated gate bipolar transistors.

[0025] According to an optional embodiment, the wake-up circuit further comprises:

[0026] a second diode, a positive terminal of the second diode connected to the fifth resistor, a negative terminal of the second diode connected to the feedback terminal of the wake-up circuit.

[0027] The second aspect of the utility model proposes a power supply system for engineering machinery, the power supply system includes vehicle-mounted power supply for supplying power to load, the power supply system further includes the power supply protection device according to as described above.

[0028] Compared with the safety protection mechanism in the conventional power management chip, the power supply protection device has the following advantages:

[0029] The power supply protection device is composed of simple circuit components (such as triode, zener diode and resistor, etc.), without using expensive special chips, reducing the circuit cost;

[0030] The voltage protection threshold (V1) of the power supply protection device can be set as the minimum working voltage of PMIC, which means that the power supply protection device will only start when the system voltage drops to the level where PMIC cannot work normally, which effectively avoids the false triggering problem caused by voltage fluctuation or temporary drop, and improves the stability and reliability of the system; and

[0031] The power supply protection device has a PMIC output state feedback loop, which can directly restore PMIC to normal state through wake-up signal after PMIC enters self-locking state, without going through the cumbersome process of power-off and re-powering, which greatly shortens the fault recovery time and ensures that the system can respond quickly in emergency. BRIEF DESCRIPTION OF DRAWINGS

[0032] The other features and advantages of the method of the utility model will become clear or more specifically explained by incorporating the drawings into this document and subsequently describing the drawings with the drawings Figure One The specific embodiments for explaining some principles of the utility model, other features and advantages of the method of the utility model will become clear or more specifically explained.

[0033] Figure 1 An internal structure diagram of the power protection device according to one example embodiment of the present application is shown.

[0034] Figure 2 An internal circuit diagram of the wake-up circuit in the power protection device shown in Figure 1

[0035] Figure 3 A waveform variation diagram of the wake-up signal outputted by the wake-up circuit shown in Figure 2

[0036] Figure 4 A waveform diagram of the voltage signal at each terminal in the wake-up circuit shown in Figure 2 DETAILED DESCRIPTION

[0037] The power protection device according to the present application will be described below with reference to the accompanying drawings and by way of example. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without some of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application. Accordingly, the following aspects, features, embodiments and advantages are merely illustrative and are not considered to be limiting the scope of the claims or the present application.

[0038] For the problem that the power management chip cannot be released from self-locking in time when entering the functional safety protection mechanism, a special monitoring chip has been developed and used by chip manufacturers. This special power monitoring chip will automatically cut off the input power of the power management chip (hereinafter also referred to as "PMIC") when the input power voltage is too low, thereby avoiding the PMIC from entering the self-locking protection mode. However, this protection mechanism, whether in the power-on or power-off situation, as long as the power voltage is lower than the set threshold, the chip will cut off the PMIC input power through its peripheral circuit, so that the PMIC cannot work. Only when the input voltage is restored and exceeds the set threshold, the input power supply of the PMIC can be normally restored. This scheme is equivalent to cutting off the power supply of the PMIC in advance before the PMIC enters the self-locking protection, thereby avoiding the PMIC from entering the self-locking state. After waiting for the system voltage to recover to the normal working interval, the power supply of the PMIC is restored, thereby completely avoiding the self-locking state of the PMIC.

[0039] ​​​However, this monitoring mechanism lacks the feedback of the PMIC, and each protection operation will trigger a series of actions such as voltage too low, power off, power voltage recovery, PMIC restart, etc. That is, after each protection operation, the PMIC needs to go through a complete restart cycle before performing normal output control, which is relatively time-consuming. In addition, this abnormal power failure may cause the vehicle controller to shut down, which may bring additional risks to the vehicle or driver in severe working conditions.

[0040] In view of the above defects existing in the traditional special power supply monitoring chip, the utility model provides a new power protection device, which adopts a circuit design scheme based on the "wake up" pin of the PMIC itself. When the input power voltage is too low, the PMIC enters the self-locking protection mode, and as soon as the power supply recovers to normal, the PMIC is immediately released from the self-locking state, and the normal work of the PMIC is restored, thereby avoiding the chip being in the self-locking protection mode for a long time. Since the PMIC is switched from one state (self-locking state) to another state (normal output state), this avoids the time consumption caused by the power-off and restart of the PMIC circuit of the traditional monitoring chip.

[0041] Figure 1 The internal structure diagram of the power protection device according to an example embodiment of the utility model is shown. When the power voltage drops below the set threshold, the power protection device can generate a wake-up signal on the wake-up pin of the PMIC, and after the PMIC recovers to normal output, the power protection device can automatically stop outputting the wake-up signal. The internal structure and working principle of the power protection device are described in detail below. Figure 1 The internal structure and working principle of the power protection device are described in detail below.

[0042] Firstly, the power protection device includes a power input pin connected to the vehicle power supply and a power output pin connected to the load to be powered by the vehicle power supply. The power supply power from the vehicle power supply can be received through the power input pin, and the load here can be, for example, an MCU or other load circuit in an engineering machinery. The power supply power is further transmitted to a power management chip (PMIC) in the power protection device, which is arranged between the power input pin and the power output pin. When the input voltage is lower than the set threshold, the PMIC will automatically enter the self-locking state to cut off the power supply path to the load. In addition, the PMIC is also provided with a wake-up pin, and by means of the level signal provided at the wake-up pin, the self-locking state of the PMIC can be automatically released.

[0043] In order to release the self-locking state of the PMIC, a wake-up circuit is designed in the power protection device. The wake-up circuit includes a monitoring end, a feedback end and a wake-up output end. The monitoring end is connected to the power input pin for real-time monitoring of the input voltage at the power input pin. The wake-up output end is connected to the wake-up pin of the PMIC. When the monitoring end detects that the power input voltage is lower than the set threshold, the wake-up circuit detects this voltage anomaly and outputs a low-level signal to the PMIC through the wake-up output end. The output voltage state of the PMIC is detected through the feedback end. The feedback end is connected to the output end of the PMIC for confirming whether the PMIC has entered the self-locking state.

[0044] Figure 2 The internal circuit diagram of the wake-up circuit in the power protection device of Figure 1 is shown. The main function of the wake-up circuit is to monitor the power input voltage and the output voltage of the power management chip (PMIC), and output a wake-up signal to release the self-locking state of the PMIC when the predetermined condition is met. The specific circuit structure and operation process of the wake-up circuit are described below with reference to Figure 2 .

[0045] The core elements of the wake-up circuit include two switching tubes (first switching tube Q1 and second switching tube Q2) and multiple resistors R1-R6 and diodes D1, D2, which work together to realize the monitoring and control of the self-locking state of the PMIC. In Figure 2 the embodiment, the two switching tubes Q1, Q2 are in the form of bipolar transistors (also known as "triodes"), however, it can also be understood that the two switching tubes can also be selected from field effect transistors, junction field effect transistors or insulated gate bipolar transistors.

[0046] The first switching tube Q1 is a key control element of the wake-up circuit, which is turned off or on according to the size change of the power input voltage. The resistor network plays a role in voltage division and current limiting in the wake-up circuit. The first resistor R1 is arranged between the monitoring end and the third resistor R3 of the wake-up circuit. The second resistor R2 is connected between the monitoring end and the power input end of the first switching tube Q1. The second end of the third resistor R3 is connected to the control end of the first switching tube Q1 for adjusting the switching state of the first switching tube Q1. The fourth resistor R4 is connected between the power output end of the first switching tube Q1 and the ground, and the power output end of the first switching tube Q1 is connected to the wake-up output end of the wake-up circuit for outputting a wake-up signal to the PMIC. In addition, the wake-up circuit also includes a first diode D1, the positive electrode of which is grounded and the negative electrode of which is connected to the first end of R3. The first diode D1 prevents reverse current flow, thereby protecting the control end of the first switching tube Q1.

[0047] The power input end of the second switch tube Q2 is connected to the power output end of the first switch tube Q1 and the wake-up output end of the wake-up circuit to receive the wake-up signal from the first switch tube Q1. When the PMIC output voltage is lower than the set value, the second switch tube Q2 is turned on to ground the wake-up output end of the wake-up circuit, ensuring that the wake-up signal can effectively release the self-locking state of the PMIC. The control end of the second switch tube Q2 is connected to the feedback end of the wake-up circuit through the fifth resistor R5, and R5 is used to control the conduction state of the second switch tube Q2. The sixth resistor R6 is connected between the control end of the second switch tube Q2 and the ground to limit the current and protect the circuit. The anode of the second diode D2 is connected to R5, and the cathode is connected to the feedback end of the wake-up circuit.

[0048] Figure 3 The wake-up circuit is shown Figure 2 The wake-up signal waveform change diagram output by the wake-up circuit to the wake-up pin of the PMIC during operation is shown. Under normal working conditions, the wake-up pin of the PMIC is required to be at a low level (no wake-up signal), and if wake-up is required, a high level is required on the wake-up pin as a wake-up signal. When the PMIC is successfully woken up, the level of the wake-up pin needs to be set to low again (return to the default low level under normal working conditions).

[0049] Assuming that the power input voltage is recorded as V_IN, which is the voltage value at the monitoring end of the wake-up circuit, the output voltage of the PMIC is recorded as V_OUT, which is the voltage value received at the feedback end of the wake-up circuit, and the voltage on the wake-up pin of the PMIC is recorded as V_WAKE, which is the voltage value output by the wake-up output end of the wake-up circuit. The voltage signal change at the wake-up pin of the PMIC during the operation of the wake-up circuit can be summarized as follows:

[0050] When the power input voltage V_IN abnormally drops below the set threshold V1, the zener diode D1 is cut off and the transistor Q1 is cut off. The PMIC automatically enters the output lock state due to insufficient input voltage, the PMIC output voltage V_OUT is 0, and the loop composed of the zener diode D2, R5 and Q2 cannot be turned on, and Q2 is cut off. Therefore, the wake-up circuit generates a low level on the wake-up pin of the PMIC, and the PMIC enters the self-locking state.

[0051] When the power input voltage V_IN recovers to the set threshold V2, the zener diode D1 is turned on and the transistor Q1 is turned on. When the output voltage V_OUT of the PMIC does not reach its set voltage V3, it is not enough to turn on the loop composed of the zener diode D2, R5 and Q2, and Q2 is cut off. At this time, the wake-up circuit generates a high level (assuming that the high level is the effective wake-up level) on the wake-up pin of the PMIC, and the PMIC circuit starts to recover from the output lock state to the normal state.

[0052] When the PMIC output voltage V_OUT recovers to the normal output voltage, i.e., the set voltage V3, the voltage stabilizing diode D1 remains conducting, and the transistor Q1 remains conducting. The output voltage V_OUT of the PMIC turns on the loop composed of the voltage stabilizing diode D2, R5 and Q2, and Q2 is turned on. At this time, the wake-up circuit re-pulls down the PMIC wake-up pin to low level through the switch control of the feedback end.

[0053] The threshold V1 is set by the minimum working voltage of the PMIC itself. The threshold V2 is set by V D1 +V Q1_be +V R3 +V R2 , i.e., V2 = V D1 +V Q1_be +V R3 +V R2 . The set voltage V3 is set by V D2 +V Q2_be +V R5 , i.e., V3 = V D2 +V Q2_be +V R5 . Wherein, V D1 and V D2 represent the voltage values across the voltage stabilizing diodes D1 and D2 respectively, V R2 , V R3 , V R5 represent the voltage values across the resistors R2, R3 and R5 respectively, and V Q1_be , V Q2_be represent the voltage values between the collector B and the emitter E of the transistors Q1 and Q2 respectively.

[0054] As can be seen from the above working process, the wake-up circuit can directly convert the output lock state of the PMIC to the output normal state after power failure, without the need to restart the PMIC, and has the advantages of fast response time and rapid fault recovery. For the engineering machinery vehicle using a general passenger car PMIC, the hydraulic system failure caused by the self-locking of the chip can be prevented. Only when the system voltage is lower than V1, the power protection device will act; unlike the existing scheme which forcibly powers off and then powers on when the PMIC approaches the self-locking risk area, the power protection device of the utility model can avoid the delay and false triggering caused by restarting the PMIC. In addition, compared with the conventional passenger car power management wake-up chip, the power protection device of the utility model has a lower cost.

[0055] In particular, the conventional solution relies on a power supply voltage monitoring chip, which usually needs to cut off the power input before the PMIC enters the self-locking state to avoid self-locking. This design needs to set a high voltage threshold, which is easy to trigger the protection action due to voltage fluctuations, resulting in unnecessary power-off and restart. The voltage protection threshold (V1) of the power supply protection device of the utility model can be set as the minimum working voltage of the PMIC, which means that only when the system voltage drops to the level that the PMIC cannot work normally, the power supply protection device will start. This design effectively avoids the problem of false triggering caused by voltage fluctuations or temporary drop, and improves the stability and reliability of the system.

[0056] In addition, the conventional solution needs to go through a complete power-off, voltage recovery and re-powering process after the PMIC enters the self-locking state, which takes a long time, especially in emergency situations. The power supply protection device of the utility model can quickly release the self-locking and restore normal output through the wake-up signal after the PMIC enters the self-locking state, which significantly shortens the system recovery time and improves the reliability and response speed of the system.

[0057] Figure 4 The waveforms of the voltage signals at each terminal of the wake-up circuit during the working process are shown. Figure 2 The waveforms of the voltage signals at each terminal of the wake-up circuit during the working process are shown. Figure 2 And Figure 4 The waveforms of the voltage signals at each terminal of the wake-up circuit during the working process are shown.

[0058] During the working process of the power supply protection device, the wake-up circuit monitors the power input voltage through the monitoring terminal. When the power input voltage V_IN is normal, Q1 is in the on state, and the PMIC works normally. When the power input voltage V_IN is detected to drop below the set threshold V1, D1 and Q1 are cut off; when the power voltage rises above the set threshold V2, D1 and Q1 are turned on again.

[0059] Specifically, when the power input voltage V_IN drops below a set threshold V1, due to insufficient input voltage, the PMIC automatically enters an output lock state, that is, the output voltage V_OUT of the PMIC (i.e., the voltage at the feedback end of the wake-up circuit) drops to 0V, at this time D2, Q2 are cut off, the voltage value V_WAKE provided at the wake-up output end of the wake-up circuit is low; when the power input voltage V_IN rises above the set threshold V2, the output voltage V_OUT of the PMIC is still 0V, D2, Q2 are cut off, at this time due to the conduction of Q1, the voltage V_WAKE provided at the wake-up output end of the wake-up circuit becomes high; when the output voltage V_OUT of the PMIC rises above the set threshold V3, D2, Q2 are turned on, at this time the voltage V_WAKE provided at the wake-up pin of the PMIC of the wake-up circuit becomes 0V.

[0060] The power protection device according to the present application can realize the monitoring and control of the PMIC self-locking state through a simple circuit structure, and has the advantages of low cost, high reliability and fast response. Specifically, compared with the safety protection mechanism in the traditional power management chip, the power protection device has the following advantages:

[0061] The power protection device is composed of simple circuit components (such as transistors, zener diodes and resistors, etc.), without the need to use expensive special chips, reducing the circuit cost;

[0062] The voltage protection threshold (V1) of the power protection device can be set to the minimum working voltage of the PMIC, which means that only when the system voltage drops to the level at which the PMIC cannot work normally, the power protection device will start, this design effectively avoids the problem of false triggering caused by voltage fluctuation or temporary drop, and improves the stability and reliability of the system; and

[0063] The power protection device has a PMIC output state feedback loop, which can directly restore the PMIC to a normal state through a wake-up signal after the PMIC enters a self-locking state, without going through the cumbersome process of power failure and re-powering, this design greatly shortens the fault recovery time, ensuring that the system can respond quickly in an emergency.

[0064] In the present application, the term "connection" means "electrical connection" or "communication connection". In addition, the terms such as "contain" and "include" mean that the technical solutions of the present application do not exclude the presence of other units that are not directly or explicitly expressed in addition to the units having direct and explicit expressions in the specification and claims.

[0065] In the utility model, the person skilled in the art can understand that the disclosed system can be realized by other modes. The system implementation mode described above is only illustrative, for example, the division of the module is only a logical function division, and another division mode can be used in actual implementation, for example, the functions of multiple modules can be combined or the function of a certain module can be further split. The modules in various embodiments of the utility model can be integrated in a processing unit, or each module can exist physically, or two or more modules can be integrated in a unit.

[0066] Although the utility model has disclosed as above with preferred embodiments, the utility model is not limited to this. Various changes and modifications made without departing from the spirit and scope of the utility model should be included in the protection scope of the utility model, therefore the protection scope of the utility model should be limited by the range defined in the claims.

Claims

1. A power protection device, characterized by, The power supply protection device comprises: a power input pin connected to a vehicle power supply to receive power supply power from the vehicle power supply; a power output pin connected to a load to be powered by the vehicle power supply; a power management chip arranged between the power input pin and the power output pin and configured to automatically enter a self-locking state when an input voltage at the power input pin is less than a set threshold to interrupt a power supply path of the vehicle power supply to the load, the power management chip comprising a wake-up pin for releasing the self-locking state; and a wake-up circuit comprising a monitoring end, a feedback end and a wake-up output end, the monitoring end being connected to the power input pin for monitoring the input voltage at the power input pin, the feedback end being connected to the power output pin for detecting an output voltage at the power output pin, and the wake-up output end being connected to the wake-up pin of the power management chip, wherein the wake-up circuit is configured to output a wake-up signal to the power management chip via the wake-up output end based on voltage values at the monitoring end and the feedback end to cause the power management chip to release the self-locking state.

2. The power protection device of claim 1, wherein The wake-up circuit comprises a first switch tube (Q1), a first resistor (R1), a second resistor (R2), a third resistor (R3) and a fourth resistor (R4), wherein: the first switch tube (Q1) comprises a control end, a power input end and a power output end, and the power output end is connected to the wake-up output end of the wake-up circuit; the first resistor (R1) is arranged between the monitoring end of the wake-up circuit and a first end of the third resistor (R3); the second resistor (R2) is arranged between the monitoring end of the wake-up circuit and the power input end of the first switch tube (Q1); a second end of the third resistor (R3) is connected to the control end of the first switch tube (Q1); a first end of the fourth resistor (R4) is connected to the power output end of the first switch tube (Q1), and a second end of the fourth resistor is grounded.

3. The power protection device of claim 2, wherein The first switch tube (Q1) is selected from a group comprising a bipolar transistor, a field effect transistor, a junction field effect transistor and an insulated gate bipolar transistor.

4. The power protection device of claim 2 or 3, wherein The wake-up circuit further comprises: a first diode (D1) having a positive electrode grounded and a negative electrode connected to the first end of the third resistor (R3).

5. The power protection device of claim 2 or 3, wherein The wake-up circuit further comprises: a second switch tube (Q2) comprising a control end, a power input end and a power output end, the power input end of the second switch tube being connected to the power output end of the first switch tube, and the power output end of the second switch tube being grounded; a fifth resistor (R5) arranged between the control end of the second switch tube (Q2) and the feedback end of the wake-up circuit; and a sixth resistor (R6) having a first end connected to the control end of the second switch tube (Q2) and a second end grounded.

6. The power protection device of claim 5, wherein, The second switch tube (Q2) is selected from a group consisting of bipolar transistors, field effect transistors, junction field effect transistors and insulated gate bipolar transistors.

7. The power protection device of claim 5, wherein, The wake-up circuit further comprises: A second diode (D2) having a positive electrode connected to the fifth resistor (R5) and a negative electrode connected to a feedback terminal of the wake-up circuit.

8. A power supply system for a working machine, the power supply system comprising an on-board power source for supplying power to a load, characterized in that, The power supply system further comprises a power supply protection device according to any one of claims 1 to 7.

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