Low-on-resistance trench gate silicon carbide VDMOS
By using a low on-resistance trench-gate silicon carbide VDMOS structure, and by employing the design of P-type and P+ well regions and a floating gate structure, the problems of large gate-drain capacitance and high switching loss of silicon carbide VDMOS devices are solved, achieving faster switching speed and lower on-resistance.
Patent Information
- Application Number
- CN202423285931.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing silicon carbide VDMOS devices have shortcomings in terms of voltage withstand capability, on-resistance, switching speed and reliability in different fields. In particular, the large gate-drain capacitance leads to high switching losses.
A low on-resistance trench gate silicon carbide VDMOS structure is adopted. The inversion inside the device is achieved through the design of P-type well region and P+ well region. A floating gate structure is constructed to shield the parasitic capacitance of gate and drain. A low-resistance region is distributed under the insulating dielectric layer to ensure uniform current flow and reduce on-resistance.
This reduces the gate-drain capacitance of the device, improves the switching speed, reduces switching losses, and maintains the device's withstand voltage capability.
Smart Images
Figure CN223758659U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of low-conducting resistance trench gate silicon carbide VDMOS. BACKGROUND
[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements of device are different in different fields, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode on-resistance. SUMMARY
[0003] The technical problem to be solved by the utility model is to provide a kind of low-conducting resistance trench gate silicon carbide VDMOS, reduce gate-drain capacitance, improve the switching speed of device, reduce switching loss.
[0004] In the first aspect, the utility model provides a kind of low-conducting resistance trench gate silicon carbide VDMOS, comprising:
[0005] Silicon carbide substrate,
[0006] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0007] Low resistance zone, the lower side of the low resistance zone is connected to the drift layer, and the low resistance zone is provided with protruding part, and the recess is provided in the protruding part;
[0008] P+ trap area, the lower side of the P+ trap area is connected to the upper side of the low resistance zone, and the inner side of the P+ trap area is connected to the outer side of the protruding part;
[0009] P-type trap area, the outer side of the P-type trap area is connected to the P+ trap area, and the lower side of the P-type trap area is connected to the upper side of the protruding part and P+ trap area;N-type source area is provided on the P-type trap area;
[0010] Insulating medium layer, the insulating medium layer passes through the N-type source area and P-type trap area, and the lower part of the insulating medium layer is arranged in the recess;Suspension gate and trench are provided in the insulating medium layer, and the trench is located above the suspension gate;
[0011] Gate metal layer, the gate metal layer is arranged in the trench;
[0012] Source metal layer, the source metal layer is connected to the N-type source area, P-type trap area and P+ trap area respectively;
[0013] and a drain metal layer, the drain metal layer is connected to the silicon carbide substrate lower side.
[0014] The utility model discloses the advantages are:
[0015] I, the utility model discloses a structure of P type trap area and P+ trap area, P type trap area is wrapped to N type source area, completes the reverse type of device gate to this area, realizes the gate function, P+ trap area is wrapped to P type trap area, and the doping of P+ trap area is higher than the doping concentration of P type trap area, guarantees the pn junction voltage withstand capability inside device.
[0016] II, the utility model constructs the suspension gate structure, can evade the gate reliability problem of device trench gate corner due to electric field concentration, and at the same time, the suspension gate can shield the parasitic capacitance of device gate and drain, thereby reduces device gate-drain capacitance, improves the switching speed of device, reduces switching loss.
[0017] III, the low resistance area is built in the left and right sides and bottom of the device suspension gate, and the low resistance area is below the insulating medium layer and is distributed in the whole layer, can effectively realize the current equalization inside device and reduce the on-resistance of device, and the low resistance area distributed in the left and right sides of insulating medium layer can effectively reduce the on-resistance from N type source area to the reverse type area of P type trap area below the insulating medium when the device is turned on.
[0018] IV, the low resistance area of the both sides of insulating medium layer only distributes in very small width, does not affect the device voltage withstand capability of P+ trap area construction. BRIEF DESCRIPTION OF DRAWINGS
[0019] The utility model will be further explained in connection with the embodiments with reference to the drawings.
[0020] Figure 1 It is the schematic diagram of the utility model low on-resistance trench gate silicon carbide VDMOS.
[0021] Figure 2 It is the process section view of the utility model low on-resistance trench gate silicon carbide VDMOS Figure 1 .
[0022] Figure 3 It is the process section view of the utility model low on-resistance trench gate silicon carbide VDMOS Figure 2 .
[0023] Figure 4 It is the process section view of the utility model low on-resistance trench gate silicon carbide VDMOS Figure 3 .
[0024] Figure 5 It is the process section view of the utility model low on-resistance trench gate silicon carbide VDMOSFigure 4 .
[0025] Figure 6 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 5 .
[0026] Figure 7 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 6 .
[0027] Figure 8 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 7 .
[0028] Figure 9 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 8 .
[0029] Figure 10 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 9 .
[0030] Figure 11 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 .
[0031] Figure 12 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 one.
[0032] Figure 13 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 two.
[0033] Figure 14 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 three.
[0034] Figure 15 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 Four.
[0035] Figure 16 This is a cross-sectional view of the process of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 five. Detailed Implementation
[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0040] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0041] As shown in the drawings, Figure 1 The embodiment of the present application provides a low on-resistance trench gate silicon carbide VDMOS, which comprises:
[0042] a silicon carbide substrate 1,
[0043] a drift layer 2, which is connected to the upper side of the silicon carbide substrate 1;
[0044] a low resistance region 3, which is connected to the lower side of the drift layer 2, and is provided with a protruding part 31, and the protruding part 31 is provided with a groove 311;
[0045] a P+ well region 4, which is connected to the upper side of the low resistance region 3, and is connected to the outer side of the protruding part 31;
[0046] a P-type well region 5, which is connected to the outer side of the P+ well region 4, and is connected to the upper side of the protruding part 31 and the P+ well region 4, and is provided with an N-type source region 51;
[0047] an insulating medium layer 6, which passes through the N-type source region 51 and the P-type well region 5, and is arranged in the groove 311; and the insulating medium layer 6 is provided with a floating gate 61 and a trench 62, and the trench 62 is located above the floating gate 61;
[0048] a gate metal layer 7, which is arranged in the trench 62;
[0049] a source metal layer 8, which is connected to the N-type source region 51, the P-type well region 5 and the P+ well region 4, respectively;
[0050] and a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.
[0051] Preferably, the doping concentration of the P+ well region 4 is greater than the doping concentration of the P-type well region 5.
[0052] In this embodiment, preferably, the width of the gate metal layer 7 is greater than the width of the suspended gate 61.
[0053] In this embodiment, preferably, the lower side of the gate metal layer 7 is in the same plane as the lower side of the P-type well region 5.
[0054] In this embodiment, preferably, the distance between the suspended gate 61 and the lower side of the gate metal layer 7 is 200-500 nm.
[0055] In this embodiment, preferably, the doping concentration of the low-resistance region 3 is greater than the doping concentration of the drift layer 2.
[0056] As shown in Figures 1 to 16 The method for manufacturing the silicon carbide VDMOS includes the following steps:
[0057] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially growing on the upper side of the silicon carbide substrate 1 to form a drift layer 2;
[0058] Step 2: forming a low-resistance region 3 by ion implantation on the drift layer 2;
[0059] Step 3: forming a barrier layer a, etching the barrier layer a to form a via, and forming a first well region 41 by ion implantation on the low-resistance region 3;
[0060] Step 4: removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, and forming a second well region 42 by ion implantation on the drift layer 2; the P+ well region 4 includes the first well region 41 and the second well region 42;
[0061] Step 5: removing the original barrier layer a, re-forming the barrier layer, etching the barrier layer a to form a via, and forming a P-type well region 5 by ion implantation on the drift layer 2;
[0062] Step 6: removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, and forming an N-type source region 51 by ion implantation on the P-type well region 5;
[0063] Step 7: removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, etching the drift layer 2 and the low-resistance region 3, forming a groove 311 in the low-resistance region 3, and depositing an insulating medium;
[0064] Step 8: removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, etching the insulating medium, and then depositing metal to form a suspended gate 61;
[0065] Step 9: removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a via, and depositing to form an insulating medium layer 6;
[0066] Step 10, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, etch the insulating dielectric layer 6 to form a trench 62, deposit metal to form a gate metal layer 7;
[0067] Step 11, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, etch the drift layer 2 to the upper side of the P-type well region 5, deposit metal to form a source metal layer 8, remove the barrier layer a, and complete the preparation.
[0068] In another embodiment, the silicon carbide substrate 1, the drift layer 2, and the low resistance region 3 are all N-type, the doping concentration of the silicon carbide substrate 1 is 2-8e18cm-3, the doping concentration of the n-type drift layer 2 is 1-5e16cm-3, the doping concentration of the n-type low resistance region 3 is 1-5e17cm-3, the doping concentration of the P+well region 4 is 1-2e18cm-3, the doping concentration of the P-type well region 5 is 1-5e17cm-3, the insulating dielectric layer 6 is silicon dioxide, and the doping concentration of the N-type source region 51 is 2-8e18cm-3; the doping concentration of the silicon carbide substrate 1 is to ensure the formation of a low resistance ohmic contact with the drain metal layer 9 and reduce the overall on-resistance of the device; the doping concentration of the n-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the n-type low resistance region 3 is designed with two considerations, one is to achieve current sharing in the device body and reduce the on-resistance of the device; the other is to ensure the formation of a pn junction with the P+well region 4; since the device uses a floating gate 61, the insulating dielectric on both sides of the floating gate 61 is thick, and the gate reliability of the device is high, so there is no need for an additional p-type shielding region, thereby allowing the n-type low resistance region 3 to be set with high doping on both sides and below the floating gate 61, thereby reducing the on-resistance of the device; the P+well region 4 can effectively achieve the pn junction withstand voltage of the device and construct the body diode of the device; the relatively low doping of the P-type well region 5 can reduce the gate inversion voltage of the device, thereby reducing the drive loss of the device.
[0069] The thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the n-type drift layer 2 is 30-100 μm, which is adjusted within the above range according to the requirements of the voltage resistance characteristics of the device, the thickness of the contact part of the n-type low-resistance region 3 and the P+ well region 4 is 500 nm, the thickness of the low-resistance region 3 is 1500 nm, the thickness of the P+ well region 4 is 1500 nm, the thickness of the P-type well region 5 is 500 nm, the thickness of the N-type source region is 200 nm, the width of the N-type source region 51 is 50-70% of the width of the P-type well region 5, the width of the P-type well region 5 accounts for 50-60% of the device cell, the width of the contact part of the P+ well region 4 and the source metal layer 8 accounts for 20-40% of the width of the device cell, the width of the insulating medium layer accounts for 10% of the device cell, the width of the device cell is 100-500 μm, the total width of the insulating medium on the left and right sides of the gate metal layer 7 is 50 nm, the distance between the gate metal layer 7 and the suspended gate 61 is 200-500 nm, the total width of the insulating medium on the left and right sides of the suspended gate 61 is 500-1000 nm, and the thickness of the insulating medium at the bottom of the suspended gate 61 is 100-200 nm.
[0070] The P-type well region 5 of the embodiment wraps the bottom and side surface of the N-type source region 51, completes the inversion of the region by the device gate metal layer 7, realizes the gate function, and since the doping concentration of the P-type well region 5 is low, the inversion controlled by the gate metal layer 7 is easier, the gate capacitance is smaller, the driving loss of the device can be reduced, and the switching speed of the device can be improved, the P+ well region 4 wraps the side surface and part of the bottom surface of the P-type well region 5, and the pn junction voltage resistance capability inside the device is ensured by increasing the doping concentration.
[0071] The device constructs the suspended gate 61 structure, there is a relatively thick insulating medium under the device gate metal layer 7, which can withstand higher voltage, and the reliability problem of the gate corner of the device trench gate due to electric field concentration can be avoided, at the same time, the suspended gate 61 can shield the parasitic capacitance between the gate and the drain of the device, thereby reducing the gate-drain capacitance of the device, improving the switching speed of the device, and reducing the switching loss.
[0072] The n-type low-resistance region 3 is constructed on the left and right sides and the bottom of the suspended gate 61 of the device, the low-resistance region 3 is distributed in the whole layer at the bottom of the device insulating medium, can effectively realize the current sharing and reduce the on-resistance of the device, the low-resistance region 3 distributed on the left and right sides of the gate insulating medium layer 6 can effectively reduce the on-resistance from the N-type source region 51 to the inversion region of the P-type well region 5 to the bottom of the insulating medium layer 6 when the device is turned on, and the n-type low-resistance region 3 distributed on the left and right sides of the gate insulating medium layer 6 of the device is only distributed in a small width, which does not affect the device voltage resistance capability constructed by the P+ well region 4.
[0073] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described by us are only illustrative, not for limiting the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.
Claims
1. A low on-resistance trench-gate silicon carbide VDMOS, characterized in that: Comprise: Silicon carbide substrate, Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; Low resistance zone, the lower side of the low resistance zone is connected to the drift layer, and the low resistance zone is provided with a protruding part, and the protruding part is provided with a groove; P+ trap area, the lower side of the P+ trap area is connected to the upper side of the low resistance zone, and the inner side of the P+ trap area is connected to the outer side of the protruding part; P-type trap area, the outer side of the P-type trap area is connected to the P+ trap area, and the lower side of the P-type trap area is connected to the upper side of the protruding part and the P+ trap area; the P-type trap area is provided with an N-type source area; Insulating medium layer, the insulating medium layer passes through the N-type source area and the P-type trap area, and the lower part of the insulating medium layer is arranged in the groove; the insulating medium layer is provided with a floating gate and a groove, and the groove is located above the floating gate; Gate metal layer, the gate metal layer is arranged in the groove; Source metal layer, the source metal layer is connected to the N-type source area, the P-type trap area and the P+ trap area respectively; And drain metal layer, the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.
2. The low on-resistance trench-gate silicon carbide VDMOS of claim 1, wherein: The doping concentration of the P+ trap area is greater than the doping concentration of the P-type trap area.
3. The low on-resistance trench-gate silicon carbide VDMOS of claim 1, wherein: The width of the gate metal layer is greater than the width of the floating gate.
4. The low on-resistance trench-gate silicon carbide VDMOS of claim 1, wherein: The lower side of the gate metal layer and the lower side of the P-type trap area are located in the same plane.
5. The low on-resistance trench-gate silicon carbide VDMOS of claim 1, wherein: The distance between the floating gate and the lower side of the gate metal layer is 200-500nm.
6. The low on-resistance trench-gate silicon carbide VDMOS of claim 1, wherein: The doping concentration of the low resistance zone is greater than the doping concentration of the drift layer.