Wafer-level multi-cavity fusion sealing cover plate

Abstract

The utility model discloses a wafer-level multi-cavity fusion sealing cover plate, which comprises a substrate and a plurality of fusion sealing units distributed on a first surface of the substrate in an array manner, each heat sealing unit comprises a large cavity and a small cavity which are arranged on the first surface of the substrate, are adjacently designed and have a preset distance; and the supporting column is arranged in the large chamber. The utility model discloses a wafer-level multi-cavity fusion sealing cover plate, which is characterized in that a plurality of fusion sealing units distributed in an array are designed on a substrate to directly seal devices arranged in an array, the sealed devices are cut through along a notch groove and a V-shaped groove by a carborundum grinding wheel scribing machine, and a single device is separated after cleaning and drying. The sealing efficiency of the devices arranged in the array is improved; meanwhile, the supporting columns are designed in the large cavity, so that the mechanical strength of the large cavity is improved, and deformation is prevented.

Description

Technical Field

[0001] This utility model relates to the field of electronic packaging, specifically a wafer-level multi-cavity fusion seal cover. Background Technology

[0002] MEMS chips such as airtight accelerometers and inertial gyroscopes require vacuum airtight packaging. Vacuum packaging is achieved using ceramic shells and metal covers, but this results in large packaging volume and weight, and is gradually being phased out. Wafer-level packaging is currently the mainstream.

[0003] Currently, wafer-level vacuum packaging primarily employs high-temperature silicon fusion bonding (500℃~1000℃), gold, gold-silicon, or low-temperature glass.

[0004] The sealing process using high-temperature silicon fusion bonding (500℃~1000℃), gold, and gold-silicon has high requirements for process equipment: it requires very high temperatures, or ultra-high vacuum supplemented by plasma surface activation to achieve sealing, or it requires a certain temperature and simultaneous friction and vibration to achieve sealing. All of these require large equipment investment and relatively low production efficiency, and are not suitable for high-reliability, low-cost, mass production.

[0005] Low-temperature glass sealing technology has low cost and high mass production efficiency, but glass materials have a higher leakage rate compared to the previous sealing technologies. High vacuum can usually be maintained for 1 to 5 years and can only be used in some applications where lifespan requirements are not high.

[0006] Existing vacuum packaging using Au80Sn20 fusion sealing for ceramic housings and metal covers consists of a single cover. This single cover cannot be directly sealed on wafer-level array devices, affecting the sealing efficiency of wafer-level array devices. Utility Model Content

[0007] Purpose of the utility model: To provide a wafer-level multi-cavity sealing cover plate to solve the above-mentioned problems existing in the prior art.

[0008] Technical solution: A wafer-level multi-cavity fusion seal cover, comprising:

[0009] A substrate, with multiple sealing units arranged in rows on the first side of the substrate;

[0010] Each sealing unit includes:

[0011] Large chambers and small chambers are arranged adjacent to each other on the first surface of the substrate and have a predetermined distance between them.

[0012] Support columns are installed inside the large cavity.

[0013] This utility model discloses a wafer-level multi-cavity sealing cover plate. This utility model directly seals arrayed devices by designing multiple neatly arranged sealing units on the substrate. After sealing, the device is cut through along grooves and V-grooves by a diamond wheel scribing machine, cleaned and dried, and then separated into individual devices, which improves the sealing efficiency of arrayed devices.

[0014] Meanwhile, support columns were designed inside the large cavity to improve the mechanical strength of the large cavity and prevent deformation.

[0015] In a further embodiment, the first side of the substrate is provided with a groove, and the second side is provided with a V-shaped groove, the groove and the V-shaped groove being located between two adjacent sealing units.

[0016] In a further embodiment, the substrate surface is provided with an adhesion layer, the adhesion layer including a Ti-Ni layer, the Ti layer being located on the substrate surface and the Ni layer being located on the Ti layer surface.

[0017] In a further embodiment, the substrate surface is provided with a low-temperature solder layer, which includes multiple Au-Sn layers.

[0018] Beneficial effects: This utility model discloses a wafer-level multi-cavity sealing cover plate. This utility model directly seals arrayed devices by designing multiple neatly arranged sealing units on the substrate. After sealing, the device is cut through along grooves and V-grooves by a diamond wheel scribing machine, cleaned and dried, and then separated into individual devices, which improves the sealing efficiency of arrayed devices.

[0019] Meanwhile, support columns were designed inside the large cavity to improve the mechanical strength of the large cavity and prevent deformation. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of this utility model.

[0021] Figure 2 This is a schematic diagram of the sealing unit structure of this utility model.

[0022] Figure 3 This is a top view schematic diagram of the sealing unit of this utility model.

[0023] Figure 4 This is a schematic diagram of the sealing wafer-level device after cutting using the sealing unit of this utility model.

[0024] The attached figures are labeled as follows:

[0025] 1. Substrate; 2. Large chamber; 21. Support pillar; 3. Small chamber; 4. Low-temperature solder layer; 5. Adhesion layer; 6. Groove; 7. V-groove; 8. Wafer-level device to be sealed; Detailed Implementation

[0026] This application relates to a wafer-level multi-cavity sealing cover, which will be explained in detail below through specific embodiments.

[0027] A wafer-level multi-cavity fusion seal cover includes:

[0028] Substrate 1, multiple sealing units arranged in rows on the first surface of substrate 1;

[0029] Each sealing unit includes:

[0030] Large chamber 2 and small chamber 3 are disposed on the first surface of the substrate 1, arranged adjacently and with a predetermined distance between them;

[0031] When large chamber 2 and small chamber 3 are formed on substrate 1, each set of sealing units has three protrusions in the low-lying large chamber 2 and small chamber 3 and the groove of substrate 1.

[0032] Support column 21 is installed inside large chamber 2.

[0033] The first side of the substrate 1 is provided with a groove 6, and the second side is provided with a V-shaped groove 7. The groove 6 and the V-shaped groove 7 are located between two adjacent sealing units.

[0034] The substrate 1 has an adhesion layer 5 on its surface. The adhesion layer 5 includes a Ti-Ni layer, with the Ti layer located on the surface of the substrate 1 and the Ni layer located on the surface of the Ti layer.

[0035] The substrate 1 has a low-temperature solder layer 4 on its surface, and the low-temperature solder layer 4 includes multiple Au-Sn layers.

[0036] In the fabrication of the cover plate of this application, a silicon wafer of the same size as the wafer-level device is first thinned to the required thickness and then polished and cleaned; then, a photoresist is applied to the surface of the silicon wafer, and exposure and baking, development and hardening are performed on a mask according to the size of the device to be sealed to prepare the etching pattern of the chamber and groove 6.

[0037] The silicon wafer is etched using a wet etching process, including the etching chamber and grooves.

[0038] Remove glue;

[0039] Sputtering or evaporating a Ti-Ni metal substrate in a vacuum sputtering or evaporation stage, followed by forming an Au-Sn-Au-Sn multilayer with Au:Sn = 100:60;

[0040] Then, a V-shaped groove 7 is cut on the back side of the silicon wafer cavity and groove 6.

[0041] A whole silicon wafer-level low-temperature sealing cover plate with a certain thickness of Au-Sn-Au-Sn…Au multilayer is prepared and aligned with the wafer-level device 8 to be sealed. The surface of the cover plate with Au-Sn-Au-Sn…Au multilayer is opposite to the sealing surface of the device. A certain pressure and a certain temperature are applied and the cover plate is fused in a nitrogen-filled or vacuum environment (depending on the requirements of the internal cavity of the device).

[0042] Finally, a diamond wheel scribing machine is used to cut the components into discrete individual parts along groove 6 and V-groove 7.

[0043] Specifically, the silicon wafer is thinned to the required thickness of 200μm to 750μm and then cleaned.

[0044] Then, a 1-5 μm thick UV positive photoresist is coated on the surface and pre-baked. Then, it is exposed and post-baked and hardened through a customized mask to expose the patterned area of ​​the chamber and groove 6 to be etched on the silicon wafer.

[0045] Next, use an etchant to wet-etch chambers and grooves 50μm to 150μm deep; then use a chemical resist remover to remove all UV positive photoresist from the clean silicon wafer.

[0046] The etched silicon wafer is placed into a vacuum evaporation stage, a vacuum is drawn, and the etched surface is cleaned with an electron gun. Then, the evaporation chamber and groove 6 are used for evaporation. Ti, Ni layer, Au-Sn-Au-Sn…Au layer with a thickness of 1-10μm.

[0047] Specifically, the wafer-level multi-cavity sealing cover plate is aligned with and pressed tightly against the sealing surface of the wafer-level device 8 to be sealed. It is then kept in a clean oven at 290℃~340℃ for 10s~300s, and then cooled to room temperature. The device is then removed, placed on a dicing film, and cut through along the grooves 6 and V-groove 7 using a diamond wheel dicing machine. After cleaning and drying, the individual devices are separated.

[0048] The sealing cover of this application is arranged at the wafer level. It can achieve hermetic encapsulation at a low temperature of 280-320℃ and a low pressure of 0.8-3.0kg (8-inch wafer). The sealing does not require friction vibration, high temperature above 500℃, ultra-high vacuum and plasma surface activation and other complex processing processes. It also does not have the low-speed leakage problem of low temperature glass seals. It has high sealing reliability and wafer-level sealing efficiency.

[0049] The low-temperature solder layer 4Au-Sn-Au-Sn…Au layer of the wafer-level multi-cavity sealing cover plate covers the entire surface of the sealing area level cover plate. The low-temperature solder layer 4 will not have the problem of insufficient local solder due to the spot welding displacement of the pre-made Au80Sn20 solder sheet.

[0050] The support pillars 21 of the wafer-level multi-cavity sealing cover plate enhance the mechanical strength of the large cavity and prevent deformation;

[0051] The Au-Sn-Au-Sn…Au layer of the wafer-level multi-cavity sealing cover covers the entire surface, eliminating the need for masking with adhesive or adhesive film. At the same time, the Au-Sn-Au-Sn…Au layer and Ti-Ni layer, which are not in the non-sealing area of ​​the device, do not need to be etched away, saving masking, metal etching and other process steps, resulting in high cover production efficiency.

[0052] Example 1:

[0053] In practical use,

[0054] A wafer-level multi-cavity sealing cap is developed. A 12" silicon wafer with a thickness of 750μm is thinned and polished to a thickness of 380μm. After baking at 180℃ for 2 minutes, a 2μm thick layer of UV positive g-line photoresist is applied to the surface using a spin coater and pre-baked at 80℃. Then, using a 2" quartz mask with a custom 7.40mm×7.40mm device (including a 7.52mm×7.52mm dicing groove), the photoresist layer is aligned and exposed using a g-line photomask, followed by post-baking at 100℃ to harden the film. This exposes the 4.50mm×6.80mm area to be etched on the silicon wafer. The wafer features two chambers measuring 2.00mm × 6.80mm and a 0.12mm wide groove pattern area, arranged in an array with a pitch of 7.52mm. The larger chamber (4.50mm × 6.80mm) has a central support pillar (0.30mm × 0.30mm × 0.10mm). A 100μm deep chamber, support pillar 21, and groove 6 are then etched using a wet etching process. All photoresist on the clean silicon wafer is removed using a chemical resist remover. The etched silicon wafer is then placed in a vacuum evaporation stage, evaporated, and the etched surface is cleaned with an electron gun. Finally, the patterned surface is vapor-deposited. Ti, The Ni layer and the Au-Sn-Au-Sn…Au layer with a thickness of 5±1μm.

[0055] Specifically, the wafer-level low-temperature sealing cover plate is aligned with and pressed tightly against the sealing surface of the wafer-level device 8 to be sealed. It is then kept in a clean oven at 290℃~340℃ for 10s~300s, and then cooled to room temperature. After vacuum degassing, it is removed and the wafer is attached to the dicing film. A V-shaped diamond abrasive wheel is used to cut a V-shape with a step size of 7.52mm on the non-metallized side of the wafer, corresponding to the groove 6 with a depth of 0.10mm. Then, a diamond abrasive wheel with a thickness of 25~60μm is used to cut through the wafer along the middle of the V-shaped groove 7 with a step size of 7.52mm. After cleaning and drying, the wafer is separated into individual packaged devices.

[0056] In summary, by utilizing the above-mentioned technical solution of the present invention, the present invention achieves large-wafer hermetic packaging of devices at the wafer level by fabricating a wafer-level cover plate. The hermetic seal can be completed at a low temperature of 280-320℃ and a pressure of 0.8-3.0kg (taking an 8-inch wafer as an example). The atmosphere of the sealed cavity can be selected according to the requirements of the device (such as vacuum, helium or nitrogen). In addition to silicon, the cover plate material can also be quartz glass, silicon nitride ceramic, etc. (selected according to the material of the sealing device). The number, size, shape, arrangement and depth of the cavities on the cover plate are also obtained by mask fabrication and wet etching according to the design of the sealing device and its wafer layout. A 0.1-2.0μm Ti-Ni layer and a 1-10μm thick Au-Sn-Au-Sn…Au layer are sputtered or vacuum evaporated.

[0057] Working principle description: Align and press the wafer-level multi-cavity sealing cover plate with the sealing surface of the wafer-level device 8 to be sealed. Hold it in a clean oven at 290℃~340℃ for 10s~300s, then cool it to room temperature. Remove it and place it on the dicing film. Use a diamond wheel dicing machine to cut through along the groove 6 and V-groove 7. After cleaning and drying, separate the individual devices.

[0058] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and all such equivalent transformations fall within the protection scope of the present invention.

Claims

1. A wafer level multi-cavity frit capped lid, characterized by, The application relates to a substrate (1) and a plurality of sealing units arranged in an array on the first surface of the substrate (1). Each sealing unit comprises: a large cavity (2) and a small cavity (3) arranged on the first surface of the substrate (1) and adjacent to each other with a predetermined distance; a supporting column (21) arranged in the large cavity (2). The first surface of the substrate (1) is provided with a groove (6), and the second surface is provided with a V-shaped groove (7), the groove (6) and the V-shaped groove (7) being located between two adjacent sealing units.

2. The wafer level multi-cavity frit capped lid panel of claim 1, wherein: The surface of the substrate (1) is provided with an adhesion layer (5), the adhesion layer (5) comprising a Ti-Ni layer, a Ti layer being located on the surface layer of the substrate (1), and a Ni layer being located on the surface layer of the Ti layer.

3. The wafer level multi-cavity frit capped lid panel of claim 1, wherein: The surface of the substrate (1) is provided with a low-temperature solder layer (4), the low-temperature solder layer (4) comprising a plurality of Au-Sn layers. ​ 4. The wafer level multi-cavity frit capped lid panel of claim 1, wherein: ​

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