Synchronous communication system and embedded system

Abstract

The utility model discloses a synchronous communication system and an embedded system, and the system comprises a first communication device which is provided with a first communication port and a first time sequence port; the second communication equipment is provided with a second communication port and a second time sequence port; the communication synchronization module comprises a first field-effect transistor and a first resistor, a source electrode of the first field-effect transistor is connected with the first communication port, a grid electrode of the first field-effect transistor is connected with the first power supply, a drain electrode of the first field-effect transistor is connected with the second communication port, one end of the first resistor is connected with the first power supply, and the other end of the first resistor is connected with the second communication port; the other end of the first resistor is connected with the first communication port, and the second communication port is connected with the second power supply; one end of the time sequence synchronization module is connected with the first time sequence port, and the other end of the time sequence synchronization module is connected with the second time sequence port; the synchronous communication system provided by the utility model can ensure that the first communication port and the second communication port receive stable voltage values, thereby obtaining an accurate logic level.

Description

Technical Field

[0001] This utility model relates to the field of communication equipment technology, and in particular to a synchronous communication system and an embedded system. Background Technology

[0002] A communication system generates a certain action in response to the requirements of an external event. To accomplish this function, the communication system acquires and processes data at high speed through voltage interaction between different devices, and then generates a response action through the execution device. The entire process is carried out under strict time and reliability constraints.

[0003] In existing technology, when a high-voltage signal is input from a high-voltage side device to a low-voltage side device, the low-voltage side device may be damaged if its output voltage exceeds the withstand voltage of the high-voltage side device, since the withstand voltage of the input circuit of the low-voltage side device is usually low. Furthermore, when a low-voltage signal is input from a low-voltage side device to a high-voltage side device, if the voltage signal obtained on the high-voltage side device is close to the voltage threshold representing logic "1", the high-voltage side device may be unable to recognize logic "1", leading to a communication system malfunction where the device cannot recognize the logic "1". Utility Model Content

[0004] The following is an overview of the subject matter described in detail herein, and this overview is not intended to limit the scope of the claims.

[0005] This invention proposes a synchronous communication system that can ensure that the first and second communication ports receive stable voltage values, thereby obtaining accurate logic levels.

[0006] To achieve the above objectives, the first aspect of this utility model proposes a synchronous communication system, characterized in that it includes: a first communication device, provided with a first communication port and a first timing port; a second communication device, provided with a second communication port and a second timing port; a communication synchronization module, including a first field-effect transistor (FET) and a first resistor, wherein the source of the first FET is connected to the first communication port, the gate of the first FET is connected to a first power supply, the drain of the first FET is connected to the second communication port, one end of the first resistor is connected to the first power supply, the other end of the first resistor is connected to the first communication port, and the second communication port is connected to a second power supply; and a timing synchronization module, one end of the timing synchronization module is connected to the first timing port, and the other end of the timing synchronization module is connected to the second timing port; wherein, when the output voltage of the first communication port is greater than a preset first voltage, the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than a first threshold voltage of the first FET; or, when the output voltage of the first communication port is less than a preset second voltage, the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage, and the second voltage is less than the first voltage.

[0007] In one embodiment, the timing synchronization module includes a second field-effect transistor (FET) and a second resistor. The source of the second FET is connected to the first timing port, and the gate of the second FET is connected to the second timing port. One end of the second resistor is connected to the first power supply, and the other end of the second resistor is connected to the first timing port. The second timing port is connected to the second power supply. When the output voltage of the first timing port is greater than a preset third voltage, the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than a second threshold voltage of the second FET; or, when the output voltage of the first timing port is less than a preset fourth voltage, the difference between the supply voltage of the second power supply and the output voltage of the first timing port is less than the second threshold voltage, and the fourth voltage is less than the third voltage.

[0008] In one embodiment, the communication synchronization module further includes a first diode, the anode of which is connected to the second power supply, and the cathode of which is connected to the second communication port.

[0009] In one embodiment, the communication synchronization module further includes a third resistor, one end of which is connected to the second power supply, and the other end of which is connected to the second communication port.

[0010] In one embodiment, the communication synchronization module further includes a fourth resistor, one end of which is connected to the first power supply, and the other end of which is connected to the gate of the first field-effect transistor.

[0011] In one embodiment, the communication synchronization module further includes a capacitor, one end of which is connected to the gate of the first field-effect transistor, and the other end of which is connected to the source of the first field-effect transistor.

[0012] In one embodiment, the timing synchronization module further includes a second diode, the anode of which is connected to the second power supply, and the cathode of which is connected to the second timing port.

[0013] In one embodiment, the timing synchronization module further includes a fifth resistor, one end of which is connected to the second power supply, and the other end of which is connected to the second timing port.

[0014] In one embodiment, the first communication device includes a first control chip and a first transistor, and the second communication device includes a second control chip and a second transistor. The collector of the first transistor is connected to a third power supply, the base of the first transistor is connected to the first control chip, the emitter of the first transistor is grounded, and the collector of the first transistor is also connected to the source of the first field-effect transistor. The collector of the second transistor is connected to a fourth power supply, the base of the second transistor is connected to the drain of the first field-effect transistor, the emitter of the second transistor is grounded, and the collector of the second transistor is also connected to the second control chip.

[0015] To achieve the above objectives, the second aspect of this utility model provides an embedded system, including the synchronous communication system described in the first aspect.

[0016] The embodiments of this application include at least the following beneficial effects: When the first communication device performs synchronous communication with the second communication device, when the output voltage of the first communication port is greater than the first voltage, that is, the first communication port outputs logic "1", the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage of the first field-effect transistor, that is, the voltage difference between the gate and source of the first field-effect transistor is less than the first threshold voltage, and the first field-effect transistor is not turned on. At this time, the input voltage of the second communication port is equal to the voltage of the second power supply, and the second communication port obtains logic "1"; when the output voltage of the first communication port is less than the first voltage, that is, the first communication port outputs logic "0", the difference between the supply voltage of the first power supply and the output voltage of the first communication port is greater than the first threshold voltage of the first field-effect transistor, and the first field-effect transistor is turned on. At this time, the voltage value of the second communication port is equal to the output voltage of the first communication port, that is, the second communication port obtains logic "0".

[0017] When the second communication device synchronously communicates with the first communication device, if the output voltage of the second communication port outputs logic "1", and the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage of the first field-effect transistor, the first field-effect transistor is not turned on, and the voltage value of the first communication port is equal to the supply voltage of the first power supply, thus the first communication port receives logic "1". If the output voltage of the second communication port outputs logic "1", and the difference between the supply voltage of the first power supply and the output voltage of the first communication port is greater than the first threshold voltage of the first field-effect transistor, the first field-effect transistor is turned on, and the voltage value of the first communication port is equal to the output voltage of the second communication port, thus the first communication port receives logic "1". If the second communication port outputs logic "0", and the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage of the first field-effect transistor, the first field-effect transistor is not turned on. At this time, due to the parasitic diode of the first field-effect transistor, the voltage value of the first communication port is equal to the output voltage of the second communication port, and the supply voltage of the first power supply and the first threshold voltage of the first communication port are equal. When the difference between the output voltages of the first communication port is greater than the first threshold voltage of the first field-effect transistor, the first field-effect transistor is turned on, and the first communication port receives a logic "0". When the second communication port outputs a logic "0", and the difference between the supply voltage of the first power supply and the output voltage of the first communication port is greater than the first threshold voltage of the first field-effect transistor, the first field-effect transistor is turned on, and the first communication port receives a logic "0". In summary, when the first communication port outputs a logic "1" to the second communication port, the voltage value of the second communication port is equal to the supply voltage of the second power supply, and the second communication port receives a logic "1". When the second communication port outputs a logic "1", the voltage value of the first communication control is equal to the supply voltage in the first power supply, and the first communication port receives a logic "1". Therefore, by selecting appropriate first and second power supplies, it is possible to ensure that the first and second communication ports receive stable voltage values, thereby obtaining accurate logic levels. It is also possible to avoid the output voltage of the first or second communication port from exceeding the withstand voltage value of the second or first communication port, thereby protecting the first and second communication ports.

[0018] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0019] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.

[0020] Figure 1 A schematic diagram of an optional structure of the synchronous communication system provided in this embodiment of the present utility model;

[0021] Figure 2 An optional system block diagram of a synchronous communication system provided in an embodiment of this utility model. Detailed Implementation

[0022] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0023] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0024] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used in the description, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0025] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0026] Currently, when a signal from a high-voltage side device is input to a low-voltage side device, the low-voltage side device may be damaged if its output voltage exceeds the withstand voltage of the high-voltage side device, since the withstand voltage of the input circuit of the low-voltage side device is usually lower. Furthermore, when a signal from a low-voltage side device is input to a high-voltage side device, if a voltage signal close to the voltage threshold representing logic "1" is received on the high-voltage side device, the high-voltage side device may be unable to recognize logic "1," leading to a communication system malfunction.

[0027] To address the issue of frequent malfunctions in communication systems, this invention provides a synchronous communication system. The system includes: a first communication device with a first communication port and a first timing port; a second communication device with a second communication port and a second timing port; a communication synchronization module including a first field-effect transistor (FET) and a first resistor, wherein the source of the FET is connected to the first communication port, the gate of the FET is connected to a first power supply, the drain of the FET is connected to the second communication port, one end of the first resistor is connected to the first power supply, the other end of the first resistor is connected to the first communication port, and the second communication port is connected to a second power supply; and a timing synchronization module, one end of which is connected to the first timing port, and the other end of which is connected to the second timing port. Specifically, when the output voltage of the first communication port is greater than a preset first voltage, the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than a first threshold voltage of the first FET; or, when the output voltage of the first communication port is less than a preset second voltage, the difference between the supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage, and the second voltage is less than the first voltage. The synchronous communication system proposed in this invention can ensure that the first and second communication ports receive stable voltage values, thereby obtaining accurate logic levels.

[0028] The embodiments of this utility model will be further described below with reference to the accompanying drawings.

[0029] Reference Figure 1 and Figure 2 This utility model proposes a synchronous communication system, comprising:

[0030] The first communication device 100 is equipped with a first communication port SDA1 and a first timing port SCK1;

[0031] The second communication device 200 is equipped with a second communication port SDA2 and a second timing port SCK2;

[0032] The communication synchronization module 300 includes a first field-effect transistor DT1 and a first resistor R1. The source of the first field-effect transistor DT1 is connected to the first communication port SDA1, the gate of the first field-effect transistor DT1 is connected to the first power supply VCC1, and the drain of the first field-effect transistor DT1 is connected to the second communication port SDA2. One end of the first resistor R1 is connected to the first power supply VCC1, and the other end of the first resistor R1 is connected to the first communication port. The second communication port SDA2 is connected to the second power supply VCC2.

[0033] The timing synchronization module 400 has one end connected to the first timing port SCK1 and the other end connected to the second timing port SCK2.

[0034] Specifically, when the output voltage of the first communication port SDA1 is greater than a preset first voltage, the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is less than the first threshold voltage of the first field-effect transistor DT1; or, when the output voltage of the first communication port SDA1 is less than a preset second voltage, the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is less than the first threshold voltage, and the second voltage is less than the first voltage.

[0035] Understandably, when the first communication device 100 performs synchronous communication with the second communication device 200, if the output voltage of the first communication port SDA1 is greater than a first voltage (i.e., the first communication port SDA1 outputs logic "1"), and the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is less than the first threshold voltage of the first field-effect transistor DT1 (i.e., the voltage difference between the gate and source of the first field-effect transistor DT1 is less than the first threshold voltage), the first field-effect transistor DT1 is not conducting. At this time, the input voltage of the second communication port SDA2 is equal to the voltage of the second power supply VCC2, and the second communication port SDA2 receives logic "1". When the first communication port... When the output voltage of the first communication port SDA1 is less than the first voltage, i.e., when the first communication port SDA1 outputs logic "0", the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is greater than the first threshold voltage of the first field-effect transistor DT1, and the first field-effect transistor DT1 is turned on. At this time, the voltage value of the second communication port SDA2 is equal to the output voltage of the first communication port SDA1, i.e., the second communication port SDA2 receives logic "0". When the second communication device 200 performs synchronous communication with the first communication device 100, when the output voltage of the second communication port SDA2 outputs logic "1", and the supply voltage of the first power supply VCC1 is greater than the first threshold voltage of the first communication port SDA1, the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is greater than the first threshold voltage of the first field-effect transistor DT1, the first field-effect transistor DT1 is turned on. When the difference between the output voltages of DA1 and SDA1 is less than the first threshold voltage of the first field-effect transistor DT1, DT1 is not turned on, and the voltage value of the first communication port SDA1 is equal to the supply voltage of the first power supply VCC1, so the first communication port SDA1 receives a logic "1". When the output voltage of the second communication port SDA2 outputs a logic "1", and the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is greater than the first threshold voltage of DT1, DT1 is turned on. At this time, the voltage of the first communication port will be equal to the output voltage of the second communication port SDA2, so the first communication port SDA1 receives a logic "1". When the second communication port SDA2 outputs logic "0", and the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is less than the first threshold voltage of the first field-effect transistor DT1, the first field-effect transistor DT1 is not turned on. At this time, due to the parasitic diode of the first field-effect transistor DT1, the voltage value of the first communication port SDA1 is equal to the output voltage of the second communication port SDA2. At this time, when the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is greater than the first threshold voltage of the first field-effect transistor DT1, the first field-effect transistor DT1 is turned on, and the first communication port SDA1 obtains logic "0".When the second communication port SDA2 outputs logic "0", and the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is greater than the first threshold voltage of the first field-effect transistor DT1, the first field-effect transistor DT1 is turned on, and the first communication port SDA1 receives logic "0".

[0036] Based on this, when the first communication port SDA1 outputs a logic "1" to the second communication port SDA2, the voltage value of the second communication port SDA2 is equal to the supply voltage of the second power supply VCC2, and the second communication port SDA2 obtains a logic "1". When the second communication port SDA2 outputs a logic "1", the voltage value of the first communication control is equal to the supply voltage in the first power supply VCC1, and the first communication port SDA1 obtains a logic "1". Therefore, by selecting appropriate first power supply VCC1 and second power supply VCC2, it can be ensured that the first communication port SDA1 and the second communication port SDA2 receive stable voltage values, thereby obtaining accurate logic levels. It can also prevent the output voltage of the first communication port SDA1 or the second communication port SDA2 from exceeding the withstand voltage value of the second communication port SDA2 or the first communication port SDA1, thereby protecting the first communication port SDA1 and the second communication port SDA2.

[0037] Reference Figure 1 and Figure 2 In some embodiments of this utility model, the timing synchronization module 400 includes a second field-effect transistor DT2 and a second resistor R2. The source of the second field-effect transistor DT2 is connected to a first timing port SCK1, and the gate of the second field-effect transistor DT2 is connected to the second timing port SCK2. One end of the second resistor R2 is connected to a first power supply VCC1, and the other end of the second resistor R2 is connected to the first timing port SCK1. The second timing port SCK2 is connected to the second power supply VCC2. When the output voltage of the first timing port SCK1 is greater than a preset third voltage, the difference between the supply voltage of the first power supply VCC1 and the output voltage of the first communication port SDA1 is less than the second threshold voltage of the second field-effect transistor DT2; or, when the output voltage of the first timing port SCK1 is less than a preset fourth voltage, the difference between the supply voltage of the second power supply VCC2 and the output voltage of the first timing port SCK1 is less than the second threshold voltage, and the fourth voltage is less than the third voltage.

[0038] It is understandable that the structure of the timing synchronization module 400 is similar to that of the communication synchronization module 300. Therefore, the timing synchronization module 400 and the communication synchronization module 300 have similar control logic and beneficial effects, which will not be elaborated here.

[0039] Reference Figure 1In some embodiments of this utility model, the communication synchronization module 300 further includes a first diode D1, the anode of the first diode D1 is connected to the second power supply VCC2, and the cathode of the first diode D1 is connected to the second communication port SDA2.

[0040] It is understandable that by setting a first diode D1 between the second power supply VCC2 and the second communication port SDA2, when the first communication device 100 and the second communication device 200 are not communicating and the power supply voltage of the second power supply VCC2 is equal to 0, the second communication port SDA2 can be prevented from outputting voltage to the second power supply VCC2, thereby ensuring the safety of the synchronous communication system.

[0041] Reference Figure 1 In some embodiments of this utility model, the communication synchronization module 300 further includes a third resistor R3, one end of which is connected to the second power supply VCC2, and the other end of which is connected to the second communication port SDA2.

[0042] It is understandable that by setting a third resistor R3 on the second power supply VCC2 and the second communication port SDA2, the impedance between the second power supply VCC2 and the second communication port SDA2 can be increased, thereby making the communication of the second communication port SDA2 more stable.

[0043] Reference Figure 1 In some embodiments of this utility model, the communication synchronization module 300 further includes a fourth resistor R4, one end of which is connected to the first power supply VCC1, and the other end of which is connected to the gate of the first field-effect transistor DT1.

[0044] It is understandable that by setting a fourth resistor R4 between the first power supply VCC1 and the gate of the first field-effect transistor DT1, the voltage at the gate of the first field-effect transistor DT1 can be effectively reduced, thereby preventing the first power supply VCC1 from being damaged due to excessive power supply voltage, thus improving the stability of the communication synchronization module 300.

[0045] Reference Figure 1 In some embodiments of this utility model, the communication synchronization module 300 further includes a capacitor C1, one end of which is connected to the gate of the first field-effect transistor DT1, and the other end of which is connected to the source of the first field-effect transistor DT1.

[0046] It is understandable that by setting capacitor C1 between the gate of the first field-effect transistor DT1 and the first communication port SDA1, the impedance between the first power supply VCC1 and the first communication port SDA1 can be effectively increased, thereby improving the stability of the communication synchronization module 300 and making the communication of the first communication port SDA1 more stable.

[0047] Reference Figure 1 In some embodiments of this utility model, the timing synchronization module 400 further includes a second diode D2, the anode of the second diode D2 is connected to the second power supply VCC2, and the cathode of the second diode D2 is connected to the second timing port SCK2.

[0048] It is understandable that by setting a second diode D2 between the second power supply VCC2 and the second timing port SCK2, when the first communication device 100 and the second communication device 200 are not communicating and the power supply voltage of the second power supply VCC2 is equal to 0, the second timing port SCK2 can also be prevented from outputting voltage to the second power supply VCC2, thus ensuring the safety of the synchronous communication system.

[0049] Reference Figure 1 In some embodiments of this utility model, the timing synchronization module 400 further includes a fifth resistor R5, one end of which is connected to the second power supply VCC2, and the other end of which is connected to the second timing port SCK2.

[0050] It is understandable that by setting a fifth resistor R5 in the second power supply VCC2 and the second timing port SCK2, the impedance between the second power supply VCC2 and the second timing port SCK2 can be increased, thereby making the communication of the second timing port SCK2 more stable.

[0051] In some embodiments of this utility model, the first communication device 100 includes a first control chip and a first transistor (not shown in the figure), and the second communication device 200 includes a second control chip and a second transistor (not shown in the figure). The collector of the first transistor is connected to a third power supply, the base of the first transistor is connected to the first control chip, the emitter of the first transistor is grounded, and the collector of the first transistor is also connected to the source of the first field-effect transistor DT1. The collector of the second transistor is connected to a fourth power supply, the base of the second transistor is connected to the drain of the first field-effect transistor DT1, the emitter of the second transistor is grounded, and the collector of the second transistor is also connected to the second control chip.

[0052] Understandably, when the output voltage from the first control chip to the base of the first transistor is greater than the turn-on voltage of the first transistor, the first transistor turns on. When the difference between the supply voltage of the second power supply VCC2 and the output voltage of the first communication port SDA1 is greater than the first threshold voltage, the voltage at the base of the second transistor is less than the turn-on voltage of the second transistor, the second transistor does not turn on, and the fourth power supply and the second control chip turn on.

[0053] In one specific embodiment, the first communication device 100 further includes a third transistor, and the second communication device 200 further includes a fourth transistor. The collector of the third transistor is connected to a fifth power supply, the base of the third transistor is connected to the source of the first field-effect transistor DT1, the emitter of the third transistor is grounded, and the collector of the third transistor is also connected to a first control chip. The collector of the fourth transistor is connected to a sixth power supply, the base of the fourth transistor is connected to a second control chip, the emitter of the fourth transistor is grounded, and the collector of the fourth transistor is also connected to the drain of the first field-effect transistor DT1.

[0054] In one specific embodiment, the first communication device 100 further includes a fifth transistor, and the second communication device 200 further includes a sixth transistor. The collector of the fifth transistor is connected to a seventh power supply, the base of the fifth transistor is connected to a first control chip, the emitter of the fifth transistor is grounded, and the collector of the fifth transistor is also connected to the source of the second field-effect transistor DT2. The collector of the sixth transistor is connected to an eighth power supply, the base of the sixth transistor is connected to the drain of the second field-effect transistor DT2, the emitter of the sixth transistor is grounded, and the collector of the sixth transistor is also connected to the second control chip.

[0055] In one specific embodiment, the first communication device 100 further includes a seventh transistor, and the second communication device 200 further includes an eighth transistor. The collector of the seventh transistor is connected to a ninth power supply, the base of the seventh transistor is connected to the source of the second field-effect transistor DT2, the emitter of the seventh transistor is grounded, and the collector of the seventh transistor is also connected to a first control chip. The collector of the eighth transistor is connected to a tenth power supply, the base of the eighth transistor is connected to the second control chip, the emitter of the eighth transistor is grounded, and the collector of the eighth transistor is also connected to the drain of the second field-effect transistor DT2.

[0056] In addition, this utility model also proposes an embedded system, including the synchronous communication system in the above embodiments.

[0057] It is understood that an embedded system may include multiple communication devices, and any two communication devices are equipped with a communication synchronization module 300 and a timing synchronization module 400.

[0058] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present utility model.

Claims

1. A synchronous communication system, characterized by The application relates to a communication synchronization device, which comprises the following parts: a first communication device provided with a first communication port and a first time sequence port; a second communication device provided with a second communication port and a second time sequence port; a communication synchronization module comprising a first field effect transistor and a first resistor, wherein the source electrode of the first field effect transistor is connected with the first communication port, the gate electrode of the first field effect transistor is connected with a first power supply, the drain electrode of the first field effect transistor is connected with the second communication port, one end of the first resistor is connected with the first power supply, the other end of the first resistor is connected with the first communication port, and the second communication port is connected with a second power supply; a time sequence synchronization module, one end of which is connected with the first time sequence port, and the other end of which is connected with the second time sequence port; when the output voltage of the first communication port is greater than a preset first voltage, the difference between the power supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage of the first field effect transistor; or when the output voltage of the first communication port is less than a preset second voltage, the difference between the power supply voltage of the first power supply and the output voltage of the first communication port is less than the first threshold voltage, and the second voltage is less than the first voltage.

2. The synchronous communication system of claim 1, wherein, The time sequence synchronization module comprises a second field effect transistor and a second resistor, wherein the source electrode of the second field effect transistor is connected with the first time sequence port, the gate electrode of the second field effect transistor is connected with the second time sequence port, one end of the second resistor is connected with the first power supply, the other end of the second resistor is connected with the first time sequence port, and the second time sequence port is connected with the second power supply; when the output voltage of the first time sequence port is greater than a preset third voltage, the difference between the power supply voltage of the first power supply and the output voltage of the first time sequence port is less than the second threshold voltage of the second field effect transistor; or when the output voltage of the first time sequence port is less than a preset fourth voltage, the difference between the power supply voltage of the first power supply and the output voltage of the first time sequence port is less than the second threshold voltage, and the fourth voltage is less than the third voltage.

3. The synchronous communication system of claim 1, wherein, The communication synchronization module further comprises a first diode, the anode of the first diode is connected with the second power supply, and the cathode of the first diode is connected with the second communication port.

4. The synchronous communication system of claim 1, wherein, The communication synchronization module further comprises a third resistor, one end of the third resistor is connected with the second power supply, and the other end of the third resistor is connected with the second communication port.

5. The system of claim 1, wherein, The communication synchronization module further comprises a fourth resistor, one end of the fourth resistor is connected with the first power supply, and the other end of the fourth resistor is connected with the gate electrode of the first field effect transistor.

6. The synchronous communication system of claim 1, wherein, The communication synchronization module further comprises a capacitor, one end of the capacitor is connected with the gate electrode of the first field effect transistor, and the other end of the capacitor is connected with the source electrode of the first field effect transistor.

7. The synchronous communication system of claim 2, wherein, The timing synchronization module further comprises a second diode, an anode of the second diode being connected with the second power supply, and a cathode of the second diode being connected with the second timing port.

8. The synchronous communication system of claim 2, wherein, The timing synchronization module further comprises a fifth resistor, one end of the fifth resistor being connected with the second power supply, and the other end of the fifth resistor being connected with the second timing port.

9. The system of claim 1, wherein, The first communication device comprises a first control chip and a first transistor, and the second communication device comprises a second control chip and a second transistor, a collector of the first transistor being connected with a third power supply, a base of the first transistor being connected with the first control chip, an emitter of the first transistor being grounded, the collector of the first transistor being further connected with a source of the first field effect transistor, a collector of the second transistor being connected with a fourth power supply, a base of the second transistor being connected with a drain of the first field effect transistor, an emitter of the second transistor being grounded, and the collector of the second transistor being further connected with the second control chip.

10. An embedded system, characterized by The synchronization communication system comprises the timing synchronization module as claimed in any one of claims 1 to 9.

Images