Power management device for computer CPU

Abstract

The utility model discloses a power supply management device for a computer CPU (Central Processing Unit), which comprises a DC (Direct Current) power supply module for converting an external power supply voltage into a working voltage of the power supply management device; the buffer module is used for temporarily storing the working signal of the CPU; the voltage acquisition module is used for acquiring the voltage corresponding to the temporarily stored working signal and outputting the working voltage of the CPU; and the power supply management module outputs a pulse modulation signal according to the working voltage of the CPU so as to control the duty ratio of an MOS (Metal Oxide Semiconductor) tube connected with the CPU in the output module and output stable load voltage. The buffer module designed by the utility model adopts a differential push-pull structure to temporarily store working signals of a CPU (Central Processing Unit) so as to improve the utilization rate and bandwidth of the working signals and buffer full-band working signals, so that electrical interference existing among the modules is filtered, the working signals including working voltage are accurately obtained, and the working efficiency of the CPU is improved. Therefore, the power management module can perform power supply management on the CPU more accurately.

Description

Technical Field

[0001] This utility model belongs to the field of power supply design, specifically relating to a power management device for a computer CPU. Background Technology

[0002] Currently, the Central Processing Unit (CPU) has become the most widely used hardware system architecture in the computer field. Due to its absolute market share, CPUs developed based on it can be adapted to almost all hardware and software in the personal computer and server fields. However, due to the lack of unified standards across different fields and insufficient development investment, the integration of the power management system that powers the CPU in current hardware systems is very low. Furthermore, because there are too many modules on the motherboard used to house the CPU, electrical interference between these modules is inevitable. This makes it difficult for the CPU's power management module to accurately obtain the CPU's operating current and voltage, thus affecting the power supply management of the CPU. Utility Model Content

[0003] To address the aforementioned problems in the prior art, this utility model provides a power management device for a computer CPU. The technical problem to be solved by this utility model is achieved through the following technical solution:

[0004] This utility model embodiment provides a power management device for a computer CPU, comprising:

[0005] The system comprises a DC power supply module, a buffer module, a voltage acquisition module, a power management module, and an output module; among which,

[0006] The DC power module is connected to both the external power supply and the power management module; the buffer module is connected to both the DC power module and the CPU; the voltage acquisition module is connected to the buffer module; the power management module is connected to both the voltage acquisition module and the output module; and the output module is connected to both the DC power module and the CPU.

[0007] The DC power module is used to convert the external power supply voltage into the operating voltage of the power management device;

[0008] The buffer module adopts a differential push-pull structure for temporarily storing the CPU's working signals;

[0009] The voltage acquisition module is used to acquire the voltage corresponding to the CPU operating signal temporarily stored in the buffer module and output the CPU operating voltage.

[0010] The power management module is used to output a pulse modulation signal according to the CPU operating voltage and control the duty cycle of the MOS transistor in the output module to output a stable load voltage to the CPU.

[0011] In one embodiment of this utility model, the buffer module includes:

[0012] Buffer circuit and filter circuit.

[0013] In one embodiment of this utility model, the buffer circuit includes:

[0014] The first and second buffer sub-circuits are symmetrically arranged with respect to the filter circuit.

[0015] In one embodiment of this utility model, the first buffer sub-circuit includes:

[0016] MOSFETs M1, M3, M5, M7, M9, and M11; capacitors C2 and C3; resistors R3 and R4; among which,

[0017] The source of the MOSFET M1 is connected to the operating voltage of the power management device, the gate is connected to the external bias voltage VB1, and the drain is connected to the first end of the resistor R3.

[0018] The source of the MOS transistor M3 is connected to the drain of the MOS transistor M5, the gate is connected to the first terminal of the capacitor C2, and the drain is connected to the source of the MOS transistor M1.

[0019] The source of the MOS transistor M5 is connected to the source of the MOS transistor M7, serving as the output terminal of the first buffer sub-circuit, and the gate is connected to the first terminal of the resistor R3.

[0020] The gate of the MOS transistor M7 is connected to the second terminal of the resistor R4, and the drain is connected to the source of the MOS transistor M9.

[0021] The gate of the MOS transistor M9 is connected to the drain of the MOS transistor M11, and the drain is grounded.

[0022] The source of the MOS transistor M11 is connected to the drain of the MOS transistor M9, and the gate is connected to a bias voltage VB3.

[0023] The first end of capacitor C2 is connected to the first end of resistor R3, and the second end is connected to the first end of capacitor C3 as the input end of the first buffer sub-circuit.

[0024] The first terminal of capacitor C3 is connected to the second terminal of resistor R3, and the second terminal is connected to the drain of MOSFET M11.

[0025] The first end of resistor R4 is connected to the second end of resistor R3, and the second end is connected to the second end of capacitor C3.

[0026] In one embodiment of this utility model, the filter circuit includes:

[0027] Resistors R1, R2, R7, R8, capacitors C1 and C6; among them,

[0028] The first end of the resistor R1 is connected to the first buffer sub-circuit, and the second end is connected to the first end of the capacitor C1.

[0029] The first end of the resistor R2 is connected to the first end of the capacitor C1, and the second end is connected to the second buffer sub-circuit.

[0030] The second terminal of capacitor C1 is grounded;

[0031] The first end of the resistor R7 is connected to the first buffer sub-circuit, and the second end is connected to the first end of the capacitor C6.

[0032] The first end of the resistor R8 is connected to the first end of the capacitor C6, and the second end is connected to the second buffer sub-circuit.

[0033] The second terminal of capacitor C6 is grounded.

[0034] In one embodiment of this utility model, the voltage acquisition module includes:

[0035] Sample-and-hold circuit and analog-to-digital converter.

[0036] In one embodiment of this utility model, the power management module is a PWM pulse width modulation chip.

[0037] In one embodiment of this utility model, the PWM pulse width modulation chip includes:

[0038] LMG3410R050, UCC12050, BQ25790, HIP6301, IS6537 or RT9237.

[0039] In one embodiment of this utility model, the output module includes:

[0040] Inductor L1, inductor L2, capacitor C7, capacitor C8, first output MOSFET M01, and second output MOSFET M02; among which,

[0041] The first end of the inductor L1 is connected to the output end of the DC power module, and the second end is connected to the first end of the capacitor C7.

[0042] The first end of the inductor L2 is connected to the drain of the first output MOSFET M01, and the second end is connected to the first end of the capacitor C8.

[0043] The first terminal of the capacitor C7 is connected to the source of the first output MOSFET M01, and the second terminal is grounded.

[0044] The first terminal of capacitor C8 is connected to the CPU and serves as the output terminal of the output module, while the second terminal is grounded.

[0045] The gate of the first output MOSFET M01 is connected to the first output terminal of the power management module, and the drain is connected to the source of the second output MOSFET M02.

[0046] The gate of the second output MOSFET M02 is connected to the second output terminal of the power management module, and the drain is grounded.

[0047] The beneficial effects of this utility model are:

[0048] In the solution provided by this utility model, the designed buffer module adopts a differential push-pull structure to temporarily store the CPU's working signals, thereby improving the utilization rate and bandwidth of the working signals and realizing the buffering of the full-band working signals. This filters out the electrical interference between the various modules and accurately obtains the working signals containing the working voltage and working current, enabling the power management module to more accurately manage the power supply to the CPU. Attached Figure Description

[0049] Figure 1 A schematic diagram of a power management device for a computer CPU provided in an embodiment of this utility model;

[0050] Figure 2 A schematic diagram of the structure of a buffer module of a power management device provided in an embodiment of this utility model;

[0051] Figure 3 This is a schematic diagram of the output module of a power management device provided in an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0053] To accurately obtain the CPU's operating voltage and current, this invention provides a power management device for a computer CPU, such as... Figure 1 As shown, it may include:

[0054] The system comprises a DC power supply module, a buffer module, a voltage acquisition module, a power management module, and an output module; among which,

[0055] The DC power module is connected to the external power supply and the power management module respectively; the buffer module is connected to the DC power module and the CPU respectively; the voltage acquisition module is connected to the buffer module; the power management module is connected to the voltage acquisition module and the output module respectively; and the output module is connected to the DC power module and the CPU respectively.

[0056] DC power module, used to convert external power supply voltage into the operating voltage of power management device;

[0057] The buffer module adopts a differential push-pull structure to temporarily store the CPU's working signals;

[0058] The voltage acquisition module is used to acquire the voltage corresponding to the CPU's working signal temporarily stored in the buffer module and output the CPU's working voltage.

[0059] The power management module is used to output pulse modulation signals according to the CPU operating voltage, and control the duty cycle of the MOSFETs in the output module to output a stable load voltage to the CPU.

[0060] The power management device proposed in this invention utilizes a differential push-pull structure buffer module to temporarily store the CPU's working signals, thereby improving the utilization rate and bandwidth of the working signals. This allows for the accurate acquisition of working signals containing working voltage and current, enabling the power management module to more precisely manage the power supply to the CPU.

[0061] For ease of understanding, the various modules in the power management device proposed in this utility model will be described separately below.

[0062] DC power module

[0063] The input terminal of the DC power module is connected to an external power source, and the output terminals are connected to the power management module and the output module, respectively. The DC power module can output the operating voltage required by the power management device according to the input external power supply voltage. This module is a common existing device; for details, please refer to the prior art, which will not be elaborated here.

[0064] Buffer module

[0065] The input terminal of the buffer module is connected to the CPU, and the output terminal is connected to the voltage acquisition module. The DC power supply module supplies power to the buffer module.

[0066] Specifically, buffer modules, such as Figure 2 As shown, it may include:

[0067] Buffer circuit and filter circuit.

[0068] The buffer module can adopt a differential push-pull structure to temporarily store the CPU's working signals. The differential push-pull structure is specifically reflected in the design of the buffer circuit.

[0069] from Figure 2 As can be seen from this, a buffer circuit may include:

[0070] The first and second buffer sub-circuits are symmetrically arranged regarding the filter circuit.

[0071] The first buffer sub-circuit may include:

[0072] MOSFETs M1, M3, M5, M7, M9, and M11; capacitors C2 and C3; resistors R3 and R4; among which,

[0073] The source of MOSFET M1 is connected to the operating voltage of the power management device, the gate is connected to the external bias voltage VB1, and the drain is connected to the first end of resistor R3.

[0074] The source of MOSFET M3 is connected to the drain of MOSFET M5, the gate is connected to the first terminal of capacitor C2, and the drain is connected to the source of MOSFET M1.

[0075] The source of MOSFET M5 is connected to the source of MOSFET M7, serving as the output terminal of the first buffer sub-circuit, and the gate is connected to the first terminal of resistor R3.

[0076] The gate of MOSFET M7 is connected to the second terminal of resistor R4, and the drain is connected to the source of MOSFET M9.

[0077] The gate of MOSFET M9 is connected to the drain of MOSFET M11, and the drain is grounded.

[0078] The source of MOSFET M11 is connected to the drain of MOSFET M9, and the gate is connected to the bias voltage VB3.

[0079] The first terminal of capacitor C2 is connected to the first terminal of resistor R3, and the second terminal is connected to the first terminal of capacitor C3 as the input terminal of the first buffer sub-circuit.

[0080] The first terminal of capacitor C3 is connected to the second terminal of resistor R3, and the second terminal is connected to the drain of MOSFET M11.

[0081] The first end of resistor R4 is connected to the second end of resistor R3, and the second end of R4 is connected to the second end of capacitor C3.

[0082] The second buffer sub-circuit may include:

[0083] MOSFETs M2, M4, M6, M8, M10, and M12; capacitors C4 and C5; resistors R5 and R6; among which,

[0084] The source of MOSFET M2 is connected to the operating voltage of the power management device, the gate is connected to the external bias voltage VB2, and the drain is connected to the first end of resistor R5.

[0085] The source of MOSFET M4 is connected to the drain of MOSFET M6, the gate is connected to the first terminal of capacitor C4, and the drain is connected to the source of MOSFET M2.

[0086] The source of MOSFET M6 is connected to the source of MOSFET M8, serving as the output terminal of the second buffer sub-circuit, and the gate is connected to the first terminal of resistor R5.

[0087] The gate of MOSFET M8 is connected to the second terminal of resistor R6, and the drain is connected to the source of MOSFET M10.

[0088] The gate of MOSFET M10 is connected to the drain of MOSFET M12, and the drain is grounded.

[0089] The source of MOSFET M12 is connected to the drain of MOSFET M10, and the gate is connected to the bias voltage VB4.

[0090] The first terminal of capacitor C4 is connected to the first terminal of resistor R5, and the second terminal is connected to the first terminal of capacitor C5 as the input terminal of the second buffer sub-circuit.

[0091] The first terminal of capacitor C5 is connected to the second terminal of resistor R5, and the second terminal is connected to the drain of MOSFET M12.

[0092] The first end of resistor R6 is connected to the second end of resistor R5, and the second end of R6 is connected to the second end of capacitor C5.

[0093] Understandably, by using the first and second buffer sub-circuits to form a differential push-pull buffer circuit, this buffer circuit can output a stable differential output voltage signal based on the CPU's working signal received at the input terminal under the control of an external bias voltage.

[0094] Filtering circuit

[0095] Filtering circuits, such as Figure 2 As shown, it may include:

[0096] Resistors R1, R2, R7, R8, capacitors C1 and C6; among them,

[0097] The first end of resistor R1 is connected to the first buffer sub-circuit, and the second end is connected to the first end of capacitor C1.

[0098] The first end of resistor R2 is connected to the first end of capacitor C1, and the second end is connected to the second buffer sub-circuit.

[0099] The second terminal of capacitor C1 is grounded;

[0100] The first end of resistor R7 is connected to the first buffer sub-circuit, and the second end is connected to the first end of capacitor C6.

[0101] The first end of resistor R8 is connected to the first end of capacitor C6, and the second end is connected to the second buffer sub-circuit.

[0102] The second terminal of capacitor C6 is grounded.

[0103] The buffer module in the power management device proposed in this embodiment uses a filter circuit to filter the output signals corresponding to MOS transistors M3, M4, M9 and M10 in the buffer circuit, and outputs signals V01 and V02 at the output terminal of the buffer circuit to filter out interference signals, thereby completing the temporary storage of the CPU's working signals.

[0104] Voltage acquisition module

[0105] The voltage acquisition module may include:

[0106] Sample-and-hold circuit and analog-to-digital converter.

[0107] The voltage acquisition module acquires the voltage corresponding to the CPU's operating signal temporarily stored in the buffer module and outputs the CPU operating voltage.

[0108] Understandably, the voltage acquisition module uses a sample-and-hold circuit to acquire the CPU's operating signals temporarily stored in the buffer module, obtaining the corresponding analog voltage signal. An analog-to-digital converter (ADC) is then used to perform analog-to-digital conversion on the obtained analog voltage signal, resulting in the corresponding digital voltage signal used as the CPU's operating voltage. Both the sample-and-hold circuit and the ADC used are conventional circuit structures; please refer to existing technologies for details.

[0109] Power Management Module

[0110] The power management module is a PWM pulse width modulation chip; the PWM pulse width modulation chip may include:

[0111] LMG3410R050, UCC12050, BQ25790, HIP6301, IS6537 or RT9237.

[0112] The power management module outputs a pulse modulation signal based on the CPU's operating voltage, controlling the duty cycle of the MOSFET connected to the CPU in the output module to output a stable load voltage to the CPU.

[0113] Specifically, PWM, or Pulse Width Modulation, is a technique that uses digital output to control analog circuits, enabling digital encoding of analog signal levels. It controls the output voltage by changing the pulse width and the output frequency by changing the pulse modulation period. The choice of PWM chip is closely related to the number of phases in the power supply circuit; the number of power phases a product has corresponds to the number of control capabilities the PWM chip needs. This chip is already very mature in existing technology; please refer to existing technology for details.

[0114] Output module

[0115] Output modules, such as Figure 3 As shown, it may include:

[0116] Inductor L1, inductor L2, capacitor C7, capacitor C8, first output MOSFET M01, and second output MOSFET M02; among which,

[0117] The first end of inductor L1 is connected to the output terminal of the DC power module, and the second end is connected to the first end of capacitor C7.

[0118] The first end of inductor L2 is connected to the drain of the first output MOSFET M01, and the second end is connected to the first end of capacitor C8;

[0119] The first terminal of capacitor C7 is connected to the source of the first output MOSFET M01, and the second terminal is grounded.

[0120] The first terminal of capacitor C8 is connected to the CPU as the output terminal of the output module, and the second terminal is grounded.

[0121] The gate of the first output MOSFET M01 is connected to the first output terminal of the power management module, and the drain is connected to the source of the second output MOSFET M02.

[0122] The gate of the second output MOSFET M02 is connected to the second output terminal of the power management module, and its drain is grounded.

[0123] Understandably, in the output module, capacitors and inductors are used together. The capacitors stabilize the supply voltage and filter out noise in the current, while the inductors stabilize the current by storing and releasing energy.

[0124] Specifically, capacitors are the most commonly used and fundamental electronic components. In the power supply circuits of CPUs and GPUs, they are mainly used for "DC blocking and AC passing" and filtering. Since capacitors are generally connected in parallel in the power supply circuit, the AC component of the current is conducted to ground by the capacitor, while the DC component continues to flow into the load. At the same time, because capacitors can maintain a constant circuit voltage through charging and discharging, they can not only filter out high-frequency noise in the current but also reduce voltage fluctuations in the circuit.

[0125] The function of an inductor is to maintain the stability of the current in the circuit. When the current through the inductor increases, the self-induced electromotive force generated by the inductor is opposite to the direction of the current, which prevents the current from increasing. At the same time, it converts some electrical energy into magnetic field energy and stores it in the inductor. When the current through the inductor decreases, the self-induced electromotive force is in the same direction as the current, which prevents the current from decreasing. At the same time, it releases the stored energy to compensate for the decrease in current.

[0126] The first output MOSFET M01 and the second output MOSFET M02 can both be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), abbreviated as MOS. In the output module, they can be considered as switches controlling current. By controlling the voltage on their gates, the MOSFETs can achieve saturation conduction. The power management module controls the duty cycle of the MOSFETs in the output module to achieve voltage regulation. In the specific circuit structure, the first output MOSFET M01 and the second output MOSFET M02 are used as the first path and the second path, respectively. These two paths need to be turned on separately during operation. Since the first path formed by MOSFET M01 can handle the external input voltage, and the second path formed by MOSFET M02 can handle the CPU's operating voltage, a MOSFET with stronger conduction capability can be selected as the second output MOSFET M02 to enhance circuit lifespan.

[0127] Understandably, in the output module, the capacitor's role is to stabilize the supply voltage while filtering out noise in the current; the inductor's role is to stabilize the current through its own energy storage and release characteristics; the duty cycles of the first output MOSFET M01 and the second output MOSFET M02 are controlled by the power management module to output a stable load voltage to the CPU.

[0128] For power management devices, load voltage adjustment is achieved by the power management module controlling the MOSFETs in the output module.

[0129] When the system starts working, the current output by the DC power module is stabilized, regulated, and filtered through capacitor C7 and inductor L1. The power management module, which consists of a PWM pulse width modulation chip, outputs a pulse modulation signal based on the CPU's operating voltage, turning on the first output MOSFET M01, which serves as the first path, to charge the subsequent circuit until the voltage across it reaches a preset value. Then, the first path is turned off, and the second output MOSFET M02, which serves as the second path, is turned on, allowing the subsequent circuit to release energy. The voltage across it then begins to drop, turning off the second path and turning on the first path again. This cycle repeats to control the duty cycle of the MOSFET connected to the CPU in the output module, thereby outputting a stable load voltage to the CPU.

[0130] The buffer module of the power management device proposed in this embodiment adopts a differential push-pull structure to temporarily store the CPU's working signals, thereby improving the utilization rate and bandwidth of the working signals and realizing the buffering of the full-band working signals. This filters out the electrical interference between the modules and accurately obtains the working signals containing the working voltage and current, enabling the power management module to more accurately manage the power supply to the CPU.

[0131] It should be noted that, in the description of this utility model, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0132] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.

Claims

1. A power management apparatus for a computer CPU, characterized by comprising: The application relates to a power supply management device, which comprises a DC power module, a buffer module, a voltage acquisition module, a power supply management module and an output module. The DC power module is connected with an external power supply and the power supply management module, the buffer module is connected with the DC power module and a CPU, the voltage acquisition module is connected with the buffer module, the power supply management module is connected with the voltage acquisition module and the output module, and the output module is connected with the DC power module and the CPU. The DC power module is used for converting an external power supply voltage into a working voltage of the power supply management device. The buffer module adopts a differential push-pull structure and is used for temporarily storing working signals of the CPU. The voltage acquisition module is used for acquiring a voltage corresponding to the working signals of the CPU temporarily stored in the buffer module and outputting a CPU working voltage. The power supply management module is used for outputting a pulse modulation signal according to the CPU working voltage, controlling a duty cycle of a MOS tube in the output module, and outputting a stable load voltage to the CPU. The buffer module comprises a buffer circuit and a filter circuit.

2. The power management device for a computer CPU according to claim 1, wherein The buffer circuit comprises a first buffer sub-circuit and a second buffer sub-circuit symmetrically arranged relative to the filter circuit. The first buffer sub-circuit comprises a MOS tube M1, a MOS tube M3, a MOS tube M5, a MOS tube M7, a MOS tube M9, a MOS tube M11, a capacitor C2, a capacitor C3, a resistor R3 and a resistor R4.

3. The power management device for a computer CPU according to claim 2, wherein The source of the MOS tube M1 is connected with the working voltage of the power supply management device, the gate is connected with an external bias voltage VB1, and the drain is connected with a first end of the resistor R3. The source of the MOS tube M3 is connected with the drain of the MOS tube M5, the gate is connected with a first end of the capacitor C2, and the drain is connected with the source of the MOS tube M1.

4. The power management device for a computer CPU according to claim 3, wherein The source of the MOS tube M5 is connected with the source of the MOS tube M7, the gate is connected with the first end of the resistor R3, and the MOS tube M5 is used as an output end of the first buffer sub-circuit. The gate of the MOS tube M7 is connected with a second end of the resistor R4, and the drain is connected with the source of the MOS tube M9. The gate of the MOS tube M9 is connected with the drain of the MOS tube M11, and the drain is grounded. The source of the MOS tube M11 is connected with the drain of the MOS tube M9, and the gate is connected with the bias voltage VB3. The first end of the capacitor C2 is connected with the first end of the resistor R3, the second end is connected with a first end of the capacitor C3, and the capacitor C2 is used as an input end of the first buffer sub-circuit. The first end of the capacitor C3 is connected with a second end of the resistor R3, and the second end is connected with the drain of the MOS tube M11. The first end of the resistor R4 is connected with the second end of the resistor R3, and the second end is connected with the second end of the capacitor C3. The filter circuit comprises a resistor R1, a resistor R2, a resistor R7, a resistor R8, a capacitor C1 and a capacitor C6. The first end of the resistor R1 is connected with the first buffer sub-circuit, and the second end is connected with a first end of the capacitor C1. ​ ​ 5. The power management device for a computer CPU according to claim 3, wherein ​ ​ ​ A first end of the resistor R2 is connected with a first end of the capacitor C1, and a second end is connected with the second buffer sub-circuit correspondingly; A second end of the capacitor C1 is grounded; A first end of the resistor R7 is connected with the first buffer sub-circuit correspondingly, and a second end is connected with a first end of the capacitor C6; A first end of the resistor R8 is connected with the first end of the capacitor C6, and a second end is connected with the second buffer sub-circuit correspondingly; A second end of the capacitor C6 is grounded.

6. The power management device for a computer CPU according to claim 1, wherein The voltage acquisition module comprises: A sample and hold circuit and an analog-to-digital converter.

7. The power management device for a computer CPU according to claim 1, wherein The power management module is a PWM pulse width modulation chip.

8. The power management device for a computer CPU according to claim 7, wherein The PWM pulse width modulation chip comprises: LMG3410R050, UCC12050, BQ25790, HIP6301, IS6537 or RT9237.

9. The power management device for a computer CPU according to claim 1, wherein, The output module comprises: An inductor L1, an inductor L2, a capacitor C7, a capacitor C8, a first output MOS tube M01 and a second output MOS tube M02; wherein, A first end of the inductor L1 is connected with an output end of the DC power supply module, and a second end is connected with a first end of the capacitor C7; A first end of the inductor L2 is connected with a drain of the first output MOS tube M01, and a second end is connected with a first end of the capacitor C8; A first end of the capacitor C7 is connected with a source of the first output MOS tube M01, and a second end is grounded; A first end of the capacitor C8 is connected with a CPU as an output end of the output module, and a second end is grounded; A gate of the first output MOS tube M01 is connected with a first output end of the power management module, and a drain is connected with a source of the second output MOS tube M02; A gate of the second output MOS tube M02 is connected with a second output end of the power management module, and a drain is grounded.

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