Novel low-temperature drift relaxation oscillator

Abstract

The utility model provides a low temperature drift relaxation oscillator, which comprises a reference voltage circuit (1), a PTAT current circuit (2) and an OSC oscillation core circuit (3), and is characterized in that the reference voltage circuit (1) is used for generating reference voltage of a comparator; the PTAT current circuit (2) is used for generating charging current of the capacitor; the OSC oscillation core circuit (3) is used for generating oscillation periodic square waves; the output end of the reference voltage circuit (1) and the output end of the PTAT current circuit (2) are connected with the input end of the OSC oscillation core circuit (3). The resistance factor is counteracted when the oscillator is designed, so that the resistance variation influence is reduced, and the resistance is the main factor of the output frequency of the oscillator influenced by the temperature, so that the temperature drift can be effectively reduced.

Description

Technical Field

[0001] This utility model belongs to the field of chips, specifically, to the field of display driver chips, and in particular to an oscillator used to provide a stable clock signal to the display driver chip, especially a relaxation oscillator with low temperature drift function. Background Technology

[0002] A relaxation oscillator is an oscillator that generates non-sinusoidal output signals, such as square waves, sawtooth waves, or triangular waves. It typically contains non-linear components such as transistors, which periodically release energy stored in capacitors or inductors to instantaneously change the output signal waveform.

[0003] Relaxation oscillators are widely used to provide clock signals for display driver chips or to generate pulses. In existing technology, relaxation oscillators include capacitors. The current charging the capacitor in the relaxation oscillator structure is generated by a resistor. The characteristics of the resistor change significantly with temperature, causing this current to also change significantly with temperature, resulting in high-temperature drift of the oscillator output frequency.

[0004] In the existing technology, there is no technical solution for a relaxation oscillator with a simple structure and low temperature drift function. Utility Model Content

[0005] To address the technical deficiencies of existing technologies, the purpose of this utility model is to provide a low-temperature drift relaxation oscillator for processing call data from a touchscreen. The oscillator is characterized by comprising a reference voltage circuit 1, a PTAT current circuit 2, and an OSC oscillation core circuit 3. The reference voltage circuit 1 generates a reference voltage for the comparator; the PTAT current circuit 2 generates a charging current for the capacitor; and the OSC oscillation core circuit 3 generates a periodic square wave. The outputs of the reference voltage circuit 1 and the PTAT current circuit 2 are connected to the input of the OSC oscillation core circuit 3.

[0006] Preferably, the reference voltage circuit 1 includes at least a startup circuit 4, a self-biased current reference circuit 5, a first resistor (6), and a second resistor (7). The startup circuit (4) includes a fifth inverter 8 and a bias circuit 9, with the output terminal of the fifth inverter 8 connected to the input terminal of the bias circuit 9. The output terminal of the bias circuit 9 is connected to the input terminal of the self-biased current reference circuit 5. The output terminal of the self-biased current reference circuit 5 is connected to the second resistor 7, and the first resistor 6 is connected to the source of the M2 transistor 10.

[0007] Preferably, the PTAT current circuit 2 includes at least an operational amplifier 11, a first bipolar transistor 12, a second bipolar transistor 13, and a third resistor 14. The base and collector of the first bipolar transistor 12 are connected to the negative input terminal of the operational amplifier 11, the base and collector of the second bipolar transistor 13 are connected to one end of the third resistor 14, the other end of the third resistor 14 is connected to the positive input terminal of the operational amplifier 11, and the emitter area of ​​the second bipolar transistor 13 is n times the emitter area of ​​the first bipolar transistor 12.

[0008] Preferably, the OSC oscillation core circuit 3 includes at least a first inverter 15, a second inverter 16, a third inverter 17, a fourth inverter 18, a first strong inversion region PMOS capacitor 19, a second strong inversion region PMOS capacitor 20, an RS flip-flop 21, a first non-overlapping signal feedback control comparator 22, and a second non-overlapping signal feedback control comparator 23. The upper plates of the first strong inversion region PMOS capacitor 19 and the second strong inversion region PMOS capacitor 20 are respectively connected to the first non-overlapping signal feedback control comparator 22 and the second non-overlapping signal feedback comparator 23. The positive input terminal of the control comparator 23, the output terminals of the first non-overlapping signal feedback control comparator 22 and the second non-overlapping signal feedback control comparator 23 are connected to the input terminal of the RS flip-flop 21. The two output terminals of the RS flip-flop 21 are connected to the input terminals of the first inverter 15 and the second inverter 16, respectively. The output terminals of the first inverter 15 and the second inverter 16 are connected to the upper plates of the first strong inversion region PMOS capacitor 19 and the second strong inversion region PMOS capacitor 20. One output of the RS flip-flop 21 is then output as a square wave through the third inverter 17 and the fourth inverter 18.

[0009] Preferably, the second non-overlapping signal feedback control comparator circuit 23 includes at least a latching circuit composed of a fourth resistor 24 and a transistor M7, and also includes a second transistor M8, wherein the drain of the transistor M7 is connected to the gate of the transistor M8, and the gate is connected to the output of the second non-overlapping signal feedback control comparator 23.

[0010] The relaxation oscillator circuit structure provided by this invention eliminates the resistance factor during oscillator design, thereby reducing the impact of resistance variation. Since resistance is a major factor affecting the oscillator's output frequency by temperature, this invention effectively reduces temperature drift. The relaxation oscillator structure provided by this invention is simple and efficient, and compared with existing technologies, it has low implementation cost, is easy to apply, and can be readily and effectively promoted. Attached Figure Description

[0011] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0012] Figure 1 A schematic diagram of the structure of a low-temperature drift relaxation oscillator according to the first embodiment of the present invention is shown;

[0013] Figure 2 The diagram shows a schematic of the specific circuit structure of the reference voltage circuit 1 in a low-temperature drift relaxation oscillator according to the first embodiment of the present invention.

[0014] Figure 3 The diagram shows a schematic of the specific circuit structure of the IPTAT current generating circuit 2 in a low-temperature drift relaxation oscillator according to a preferred embodiment of the present invention.

[0015] Figure 4 The diagram shows a schematic diagram of the specific circuit structure of the OSC core oscillation circuit 3 in a low-temperature drift relaxation oscillator according to a preferred embodiment of the present invention; and

[0016] Figure 5 The diagram shows a specific circuit structure of a comparator circuit in a low-temperature drift relaxation oscillator according to a preferred embodiment of the present invention. Detailed Implementation

[0017] To better illustrate the technical solution of this utility model, the following description, in conjunction with the accompanying drawings, will further explain this utility model.

[0018] Those skilled in the art will understand that this utility model provides a low-temperature drift oscillator structure design, mainly solving the problem of high-temperature drift in the output frequency caused by large temperature variations in the resistance of the RC oscillator structure. More specifically, in conjunction with Figure 1 The following describes the specific circuit implementation of this utility model: The circuit structure of the low-temperature drift relaxation oscillator includes: a reference voltage circuit 1, a PTAT current circuit 2, and an OSC oscillation core circuit 3.

[0019] Among them, the reference voltage circuit 1 generates the reference voltage of the comparator, which determines the charging and discharging time of RC; the PTAT current circuit 2 is used to generate the charging current of the capacitor; and the OSC oscillation core circuit 3 is used to generate the oscillating periodic square wave.

[0020] This invention reduces the impact of resistance variation by eliminating the resistance factor during oscillator design. Since resistance is the main factor affecting the output frequency of a relaxation oscillator due to temperature, reducing the resistance factor effectively minimizes temperature drift.

[0021] More specifically, combined Figures 2 to 5 The illustrated embodiment further explains the specific structure of each module circuit of the low-temperature drift oscillator provided by this utility model, and describes in detail how to reduce temperature drift and realize a low-temperature drift relaxation oscillator.

[0022] like Figure 2 The diagram illustrates the specific circuit structure of the reference voltage circuit 1 according to a preferred embodiment of the present invention. Specifically, the reference voltage circuit 1 consists of a startup circuit 4, a self-biased current mirror 5, and resistors. The startup circuit enable signal EN = VCI, after passing through two inverters, pulls VP1 and VP2 low. The self-biasing circuit provides bias for the current mirror. The function of the reference voltage circuit 1 is to generate a bias current I independent of the power supply using the clamping resistor of the cascode current mirror. OUT Then, a reference voltage VREF is generated through the second resistor R2. The principle of the power supply-independent reference current is based on the voltage difference generated at the source terminal of the self-biased current mirror NMOS transistor by the first resistor R1, that is, the voltage across the first resistor R1 is:

[0023] V R1 =I2·R1 (1)

[0024] In this context, "#(1)" represents "Formula (1)" or "Equation (1)", and the same applies below.

[0025] Correspondingly, the voltage from the gate of transistors M1 and M2 to ground can be written as follows:

[0026] V GS1 =V GS2 +I2·R1 (2)

[0027] Among them, V GS1 This represents the voltage from the gate to ground of transistor M1, V. GS2 This represents the voltage from the gate of transistor M2 to ground.

[0028] Let the width-to-length ratio of M1 be... The aspect ratio of M2 is Since the currents in the two branches containing transistors M1 and M2 are equal, we can conclude that I1 = I2 = I OUT Furthermore, we can obtain:

[0029]

[0030] Where, μ n C ox Represents the process constant μ n Electron mobility, C OX It is the gate oxide capacitance per unit area.

[0031] Furthermore, if the volume effect is ignored, the above equation (3) can be further evolved into:

[0032]

[0033] Therefore, the reference current is calculated as follows:

[0034]

[0035] Therefore, according to Figure 2 In the preferred embodiment shown, the reference current magnitude and temperature characteristics are only related to the resistance magnitude and MOS process, and are not affected by the power supply voltage.

[0036] Furthermore, since the reference voltage VREF flows through the current I... OUT The resistor R2 generates the current, so from equation (5), we can obtain:

[0037]

[0038] Furthermore, Figure 3 A detailed circuit diagram of the PTAT current circuit 2 of a cryogenic drift relaxation oscillator according to a preferred embodiment of the present invention is shown. Specifically, as Figure 3 In the circuit shown, the voltages at the two input terminals of the operational amplifier are approximately equal, so we can write:

[0039] V A =V nA +I R3 ·R3 (7)

[0040] Given that the emitter area of ​​transistor nA is n times that of transistor A, then based on the characteristics of a forward-biased diode, we can obtain:

[0041]

[0042] Where V T For thermal voltage, I S This is the reverse saturation current. Figure 2 The M3 and M4 sizes are completely symmetrical, i.e., I A =I nA Therefore, from equations (7), (8), and (9), the voltage across resistor R3 can be written as:

[0043] ΔV R3 =V A -V nA =V T ln n (10)

[0044] so:

[0045]

[0046] so:

[0047]

[0048] Figure 3The diagram shows a specific circuit diagram of the OSC core oscillation circuit 3 of the low-temperature drift relaxation oscillator according to a preferred embodiment of the present invention. The OSC charging capacitor is a PMOS capacitor operating in the strong inversion region, C1 = C2. The capacitor is charged by a constant current IPTAT and compared with the voltage VREF provided by the reference voltage circuit 1. The output is then fed back through a non-overlapping signal control comparator and used to achieve a square wave output via an RS flip-flop. The delay module consists of an even number of inverters.

[0049] Furthermore, those skilled in the art will understand that in the initial state, EN=1, L13=0, L14=0, the bias current for comparator and capacitor charging is not working, then Q=0, QB=0, and the capacitor remains unchanged until it is enabled.

[0050] When the enable pin is active, EN = 0, and the bias current for charging the comparator and capacitors is active, C = 0, D = 0. According to the characteristics of the RS latch formed by NOR, the latch is released, Q = 0, QB = 1. At this time, capacitor C1 is charged through a constant bias current until the voltage on the capacitor is higher than the reference voltage VREF of the comparator. Then capacitor C2 discharges. After the comparator's settling time, the comparator outputs CMPAO = 1, CMPBO = 0, C = 1, D = 0, L13 = 1, L14 = 1, DNA = DNB = 0, and outputs Q = 1, QB = 0.

[0051] After the latch state flips, capacitor C1 discharges, and capacitor C2 is charged by a constant bias current until the voltage on the capacitor is higher than the comparator's reference voltage VREF. After the comparator's setup time, the comparator outputs CMPBO=1 and D=1. Since the comparator has a latching function, CMPAO=1 and DNA=1. The feedback control comparator outputs CMPAO=0, and C=0, outputs Q=0 and QB=1, which flips the state. This avoids the large dynamic current generated by the inverter in the next stage during the comparator's flipping process, effectively reducing the average power consumption, while ensuring that the outputs Q and QB do not overlap, and that the duty cycle and frequency are stable. Thus, a square wave signal of one cycle is output, and the next cycle is the same.

[0052] The charging time of the capacitor determines the duration of the high-level output. When Q=0 and QB=1, C1 charges; when Q=1 and QB=0, C2 charges. Therefore, the high-level duration of the output pulse is determined by the charging time of C1, the low-level duration is determined by the charging time of C2, and the duty cycle is determined by C1 / (C1+C2).

[0053] Figure 5 A detailed circuit diagram of the comparator circuit for a low-temperature drift relaxation oscillator according to a preferred embodiment of the present invention is shown. Figure 5In the comparator circuit shown, the resistor and M7 act as latches. When the comparator output is high (VP>VN), the output controls M7 to close, turning off the load transistor M8. When the comparator input VP≤VN, the output remains high, and the output value is latched at a high potential until the feedback signal DNA pulls the CMPAO terminal low.

[0054] The time it takes for capacitors C1 and C2 to charge once each constitutes a complete OSC cycle, i.e., T. OSC =T C1 +T C2 From the relationship between period and frequency, we can write:

[0055]

[0056] Substituting equations (6) and (13) into equation (14) yields:

[0057]

[0058] From the above formula, it can be seen that if the resistors that generate IPTAT and VREF are of the same type, and:

[0059] R1:R2:R3=1:a:b (16)

[0060] Substituting equation (16) into equation (15), we get:

[0061]

[0062] The above derivation and analysis show that by using the same type of resistor, the influence of temperature-dependent resistance on frequency can be completely ignored in the frequency expression, thus ensuring the temperature drift characteristics of the OSC, which can effectively provide a relaxation oscillator with low temperature drift.

[0063] The low-temperature drift relaxation oscillator provided by this invention can be effectively applied to the following fields:

[0064] 1. Provide a stable clock signal for the display driver chip, specifically including:

[0065] (1) Synchronous data transmission: The clock signal provides a precise time reference for the transmission of display data, ensuring that the data can be transmitted in the correct order and rhythm at the sending and receiving ends, thereby avoiding data confusion and errors.

[0066] (2) Control data rate: It determines the data transmission speed, enabling the display driver chip to send image data to the display screen at an appropriate frequency to achieve smooth and stable image display.

[0067] (3) Coordinate display operation: The clock signal helps coordinate the work of various modules inside the display driver chip, such as data processing, cache management and control logic, to ensure that they can work together and improve the overall performance of the display system.

[0068] (4) Determine the pixel refresh rate: This determines the refresh rate of the display pixels, which directly affects the clarity and stability of the image. A higher refresh rate can reduce image flicker and provide a clearer and more comfortable visual experience.

[0069] (5) Timing control: For display technologies such as liquid crystal displays (LCDs) that require precise timing control, clock signals are used to control the on and off times of pixels and the timing of voltage conversion, thereby achieving correct image display.

[0070] It can also provide the following applications:

[0071] 2. Pulse generation: It can generate non-sinusoidal waveforms such as square waves, triangular waves or pulse waves, which can be used as clock signals, trigger signals or timing control in digital circuits; for example, to provide timing pulses in digital logic circuits such as counters, flip-flops, and timers.

[0072] 3. Signal modulation: Its output signal can be used to modulate other signals, such as amplitude modulation and frequency modulation, and has certain applications in communication systems.

[0073] 4. Power Management: For example, in a switching power supply, a relaxation oscillator can control the switching frequency of the switch to achieve efficient power conversion.

[0074] 5. Test and measurement equipment: generates specific test signals, such as those used to test the frequency response of amplifiers and the characteristics of filters.

[0075] 6. Audio and sound effects: Create special sound effects or audio effects in audio devices.

[0076] 7. Sensor Applications: Combined with certain sensors, changes in physical quantities are converted into changes in oscillation frequency or pulse width, thereby achieving measurement or detection functions. For example, it is used to measure changes in physical quantities such as temperature, pressure, and light intensity. These changes are converted into frequency or pulse width changes in electrical signals through a relaxation oscillator, and then measured or monitored.

[0077] The specific embodiments of this utility model have been described above. It should be understood that this utility model is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the substantive content of this utility model.

Claims

1. A novel low temperature drift relaxation oscillator for processing touch screen hit data, characterized by, The application relates to an oscillator circuit, which comprises a reference voltage circuit (1), a PTAT current circuit (2) and an OSC oscillation core circuit (3), wherein the reference voltage circuit (1) is used for generating a reference voltage of a comparator; the PTAT current circuit (2) is used for generating a charging current of a capacitor; and the OSC oscillation core circuit (3) is used for generating an oscillation periodic square wave; and the output ends of the reference voltage circuit (1) and the PTAT current circuit (2) are connected to the input end of the OSC oscillation core circuit (3).

2. The relaxation oscillator of claim 1, wherein, The reference voltage circuit (1) at least comprises a starting circuit (4), a self-bias current reference circuit (5), a first resistor (6) and a second resistor (7), the starting circuit (4) comprises a fifth inverter (8) and a bias circuit (9), the output end of the fifth inverter (8) is connected to the input end of the bias circuit (9), the output end of the bias circuit (9) is connected to the input end of the self-bias current reference circuit (5), the output end of the self-bias current reference circuit (5) is connected to the second resistor (7), and the first resistor (6) is connected to the source electrode of an M2 tube (10).

3. The relaxation oscillator according to claim 1 or 2, characterized in that The PTAT current circuit (2) at least comprises an operational amplifier (11), a first bipolar transistor (12), a second bipolar transistor (13) and a third resistor (14), the base electrode and the collector electrode of the first bipolar transistor (12) are connected to the negative input end of the operational amplifier (11), the base electrode and the collector electrode of the second bipolar transistor (13) are connected to one end of the third resistor (14), the other end of the third resistor (14) is connected to the positive input end of the operational amplifier (11), and the emitter area of the second bipolar transistor (13) is n times of the emitter area of the first bipolar transistor (12).

4. The relaxation oscillator of claim 3, wherein, The OSC oscillation core circuit (3) at least comprises a first inverter (15), a second inverter (16), a third inverter (17), a fourth inverter (18), a first strong reverse type PMOS capacitor (19), a second strong reverse type PMOS capacitor (20), an RS flip-flop (21), a first non-overlapping signal feedback control comparator (22) and a second non-overlapping signal feedback control comparator (23), the upper plate of the first strong reverse type PMOS capacitor (19) and the second strong reverse type PMOS capacitor (20) is respectively connected to the positive input end of the first non-overlapping signal feedback control comparator (22) and the second non-overlapping signal feedback control comparator (23), the output ends of the first non-overlapping signal feedback control comparator (22) and the second non-overlapping signal feedback control comparator (23) are connected to the input end of the RS flip-flop (21), the two output ends of the RS flip-flop (21) are respectively connected to the input ends of the first inverter (15) and the second inverter (16), the output ends of the first inverter (15) and the second inverter (16) are connected to the upper plates of the first strong reverse type PMOS capacitor (19) and the second strong reverse type PMOS capacitor (20), and one output end of the RS flip-flop (21) outputs a square wave through the third inverter (17) and the fourth inverter (18).

5. The relaxation oscillator of claim 4, wherein, The second non-overlapping signal feedback control comparator (23) comprises at least a latch circuit composed of a fourth resistor (24) and a transistor M7 (25), and a second transistor M8 (26), the drain of the transistor M7 (25) is connected to the gate of the transistor M8 (26), and the gate is connected to the output of the second non-overlapping signal feedback control comparator (23).

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