Amplification circuit for high-speed comparison in MIPI high-speed interface
By designing an amplifier circuit within the MIPI high-speed interface and building a current mirror circuit using MOSFETs and transistors, the problem of MOSFETs not working properly under low power supply voltage was solved, thus enabling the normal operation of the MIPI high-speed interface and reducing noise.
Patent Information
- Application Number
- CN202423186183.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2034-12-23
AI Technical Summary
The MOSFETs in traditional MIPI high-speed interfaces are affected by process, voltage and temperature, and cannot work normally at low power supply voltages, which makes it impossible to use bipolar transistors.
An amplifier circuit design including a first amplification module and a second amplification module is adopted. A current mirror circuit is built using MOSFETs and transistors. By shorting the gate and drain of the MOSFET, the voltage is increased, and the current mirror circuit is used to reduce noise and image error.
This enables the bipolar transistor to function normally under low power supply voltage, reduces system noise and image error, and ensures the normal operation of the MIPI high-speed interface.
Smart Images
Figure CN223772022U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of MIPI high-speed interface technology, specifically to an amplifier circuit for high-speed comparison within a MIPI high-speed interface. Background Technology
[0002] The Mobile Industry Processor Interface (MIPI) is a common data interface type, operating in two modes: High-Speed (HS) and Low-Power (LP). In the MIPI protocol, the high-speed mode output common-mode voltage Vcm ranges from 150mV to 250mV, and the high-speed differential signal output voltage difference Vod ranges from 140mV to 270mV, with a maximum voltage not exceeding 360mV.
[0003] Traditional MIPI circuits used in high-speed mode do not use bipolar transistors inside the MIPI high-speed interface because the MOSFETs are affected by process, voltage and temperature. This is because bipolar transistors have a large voltage drop, and if they were used, it would not be possible to guarantee the normal operation of other transistors in the circuit. Utility Model Content
[0004] In view of this, the problem to be solved by this utility model is to provide an amplifier circuit for high-speed comparison in a MIPI high-speed interface, which enables the MIPI high-speed interface to use bipolar transistors under low power supply voltage.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:
[0006] An amplifier circuit for high-speed comparison within a MIPI high-speed interface includes a first amplification module. The first amplification module includes an inverting amplifier circuit, which includes a MOSFET M1 and a MOSFET M3. The source of the MOSFET M1 is connected to a first current source I1. The gate of the MOSFET M1 receives an inverted input signal. A resistor R1 is connected in series between the drain of the MOSFET M1 and the drain of the MOSFET M3. The base of the MOSFET M3 is grounded. The source of the MOSFET M1 outputs a first inverted signal.
[0007] Furthermore, the drain and gate of the MOS transistor M3 are shorted.
[0008] Furthermore, the first amplification module includes a non-inverting amplifier circuit, which includes MOSFETs M2 and M3 and a resistor R2. The non-inverting amplifier circuit has the same circuit structure as the inverting amplifier circuit. The gate of MOSFET M2 receives a non-inverting input signal, and the drain of MOSFET M2 outputs a first non-inverting signal.
[0009] Furthermore, the output of the first amplification module is connected to the second amplification module. The second amplification module includes an inverting current mirror circuit, which includes a MOSFET M7, a transistor Q3, and a transistor Q2. The gate of the MOSFET M7 receives a first inverted signal, the source of the MOSFET M7 is connected to a second current source I2, the drain of the MOSFET M7 is connected to the collector of the transistor Q3, the emitter of the transistor Q3 is grounded, the base of the transistor Q3 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is grounded, and the collector of the transistor Q2 outputs a second inverted signal.
[0010] Furthermore, the inverting current mirror circuit includes a MOSFET M9, the gate of which is connected to the drain of a MOSFET M7, the source of which is connected to the base of a transistor Q3, and the drain of which is connected to the power supply VDD.
[0011] Furthermore, the base of transistor Q3 is connected to the base of transistor Q1, the emitter of transistor Q1 is grounded, and the collector of transistor Q1 outputs a third inverted signal.
[0012] Furthermore, the second amplification module includes a non-inverting current mirror circuit, which includes MOSFET M8, MOSFET M10, transistor Q4, and transistor Q5. The non-inverting current mirror circuit has the same connection structure as the inverting current mirror circuit. The gate of MOSFET M8 receives a first inverting signal, and the collector of transistor Q5 outputs a second inverting signal.
[0013] Furthermore, the in-phase current mirror circuit includes a transistor Q6 with the same connection structure as transistor Q1, and the collector of transistor Q6 outputs a third in-phase signal.
[0014] The advantages and positive effects of this utility model are:
[0015] (1) By shorting the gate and drain of MOS transistors M3 and M4 in the first amplifier circuit, the voltage of the first inverted signal and the first non-inverted signal is increased (the gate voltage of MOS transistors M7 and M8 is increased), so that the second amplifier module can operate normally and the MIPI high-speed interface can use bipolar transistors under low power supply voltage.
[0016] (2) By building a current mirror circuit with two transistors connected at their bases, the system noise can be reduced based on the circuit's own performance. By adding MOSFETs M9 and M10 connected to the power supply VDD in the current mirror circuit, the current at the bases of transistors Q3 and Q4 can be reduced, thus reducing the mirror error when there are single or multiple mirrors. Attached Figure Description
[0017] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:
[0018] Figure 1 This is an overall circuit diagram of an amplifier circuit for high-speed comparison within a MIPI high-speed interface according to this utility model.
[0019] Figure 2 This is a current mirror circuit diagram built using transistors. Detailed Implementation
[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0022] This utility model provides an amplifier circuit for high-speed comparison within a MIPI high-speed interface, such as... Figure 1 As shown, it includes a first amplification module and a second amplification module. The positive and negative signals are amplified by the first amplification module and then input into the second amplification module. The second amplification module amplifies the positive and negative signals a second time and then outputs them through a current mirror circuit. The comparison module compares the magnitudes of the positive and negative signals based on the output of the second amplification module and outputs the comparison result.
[0023] The first amplification module contains bipolar transistors to avoid excessive use of resistors, thus reducing the size of the MIPI high-speed interface. The first amplification module includes an inverting amplifier circuit, which comprises MOSFETs M1 and M3. The source of MOSFET M1 is connected to a first current source I1, and the gate of MOSFET M1 receives the inverted input signal. A resistor R1 is connected in series between the drains of MOSFET M1 and M3. The base of MOSFET M3 is grounded, and the source of MOSFET M1 outputs the first inverted signal.
[0024] The inverted input signal is amplified by MOSFET M1 and the first current source I1, and the voltage is adjusted by resistor R1 and MOSFET M3 to achieve the technical effect of amplifying the inverted input signal.
[0025] To avoid excessive voltage drop generated by MOSFET M3, which could prevent the second power generation module from starting normally (due to insufficient voltage to turn on MOSFET M7 in the second power generation module), shorting the gate and drain of MOSFET M3 can increase the gate voltage of MOSFET M7.
[0026] The first amplification module includes a non-inverting amplifier circuit, which includes MOSFETs M2 and M4 and a resistor R2. The connection structure of the non-inverting amplifier circuit is the same as that of the inverting amplifier circuit. MOSFET M2 corresponds to MOSFET M1, and MOSFET M4 corresponds to MOSFET M3. Therefore, the gate of MOSFET M2 receives the non-inverting input signal, and the drain of MOSFET M2 outputs the amplified first non-inverting signal.
[0027] The second amplification module includes an inverting signal mirror amplification circuit, which includes a MOSFET M7, a transistor Q3, and a transistor Q2. The gate of the MOSFET M7 receives the first inverted signal output from the low-voltage amplification module. The source of the MOSFET M7 is connected to the second current source I2. The drain of the MOSFET M7 is connected to the collector of the transistor Q3. The emitter of the transistor Q3 is grounded. The base of the transistor Q3 is connected to the base of the transistor Q2. The emitter of the transistor Q2 is grounded. The collector of the transistor Q2 outputs the mirrored second inverted signal.
[0028] The second current source I2 and MOSFET M7 amplify the first inverted signal. Transistors Q2 and Q3 form a current mirror circuit to amplify the first inverted signal and then mirror it into a second inverted signal before outputting it.
[0029] Current mirror circuits are typically multi-stage current mirrors used to achieve multiple outputs. One embodiment of this application is as follows: the inverting signal mirror amplifier circuit is a two-stage current mirror circuit, including transistor Q1. The base of transistor Q1 is connected to the base of transistor Q3, and the emitter of transistor Q1 is grounded. It mirrors the first inverted signal to output a third inverted signal, which is then output from the collector of transistor Q1.
[0030] Traditional current mirrors built with transistors suffer from increased image error as the number of stages increases, especially in complex circuits with multiple stages of mirroring due to the presence of current at the transistor's base. For example... Figure 2 As shown: Assuming that the amplification factor of transistors Qa and Qb is β, and IB1 = IB2, and the collector current of Qa is IC, then IB1 = IB2 = IC / β, I2 = IC + 2IC / β = (1 + 2 / β)IC. When β approaches infinity, I1 can be equal to I2. Therefore, the existence of the base current is the main reason for the error of the current mirror.
[0031] To reduce the impact of base current on current mirror error, the inverting current mirror circuit includes a MOSFET M9. The gate of MOSFET M9 is connected to the drain of MOSFET M7, the source of MOSFET M9 is connected to the base of transistor Q3, and the drain of MOSFET M9 is connected to the power supply VDD.
[0032] The current flowing through MOSFET M9 is Vgs is the voltage difference between the collector and base of the transistor, μ n C represents the average mobility of electrons in the channel. ox Vth is the oxide layer capacitance of the MOSFET, and Vth is the threshold voltage of the MOSFET M9. By changing the width-to-length ratio of the MOSFET M9, the current magnitude can be changed, reducing the influence of the base current of the transistor on the mirror current, thereby reducing the error.
[0033] The second amplification module includes a non-inverting current mirror circuit, which comprises MOSFETs M8 and M10, transistor Q4, and transistor Q5. Its connection structure is the same as that of the inverting current mirror circuit, corresponding sequentially to MOSFETs M7, M9, Q3, and Q2. The gate of MOSFET M8 receives the first in-phase signal, and the collector of transistor Q5 outputs the second in-phase signal.
[0034] One embodiment of this application is as follows: when the in-phase current mirror circuit is a two-stage output, the in-phase current mirror circuit includes a transistor Q6 with the same connection structure as transistor Q1, and the collector of transistor Q6 outputs a third in-phase signal.
[0035] The comparison module receives and compares the second in-phase signal and the second out-of-phase signal, and outputs the comparison result; the comparison module receives and compares the third in-phase signal and the third out-of-phase signal, and outputs the comparison result.
[0036] The embodiments of this utility model have been described in detail above, but the content described is only a preferred embodiment of this utility model and should not be considered as limiting the scope of implementation of this utility model. All equivalent changes and improvements made within the scope of this utility model should still fall within the scope of this patent.
Claims
1. An amplification circuit for high speed comparison in a MIPI high speed interface, characterized by, The first amplification module comprises an inverting amplification circuit, the inverting amplification circuit comprises MOS tubes M1 and M3, the source of the MOS tube M1 is connected with a first current source I1, the gate of the MOS tube M1 receives an inverting input signal, the drain of the MOS tube M1 and the drain of the MOS tube M3 are connected in series with a resistor R1, the base of the MOS tube M3 is grounded, and the source of the MOS tube M1 outputs a first inverting signal.
2. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 1, characterized in that, The drain of the MOS tube M3 is short-circuited with the gate.
3. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 2, characterized in that, The first amplification module comprises a non-inverting amplification circuit, the non-inverting amplification circuit comprises MOS tubes M2, M3 and a resistor R2, the circuit structure of the non-inverting amplification circuit is the same as that of the inverting amplification circuit, the gate of the MOS tube M2 receives a non-inverting input signal, and the drain of the MOS tube M2 outputs a first non-inverting signal.
4. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 1, characterized in that, The output end of the first amplification module is connected with a second amplification module, the second amplification module comprises an inverting current mirror circuit, the inverting current mirror circuit comprises MOS tubes M7, a transistor Q3 and a transistor Q2, the gate of the MOS tube M7 receives the first inverting signal, the source of the MOS tube M7 is connected with a second current source I2, the drain of the MOS tube M7 is connected with the collector of the transistor Q3, the emitter of the transistor Q3 is grounded, the base of the transistor Q3 is connected with the base of the transistor Q2, the emitter of the transistor Q2 is grounded, and the collector of the transistor Q2 outputs a second inverting signal.
5. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 4, characterized in that, The inverting current mirror circuit comprises a MOS tube M9, the gate of the MOS tube M9 is connected with the drain of the MOS tube M7, the source of the MOS tube M9 is connected with the base of the transistor Q3, and the drain of the MOS tube M9 is connected with a power supply VDD.
6. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 5, characterized in that, The base of the transistor Q3 is connected with the base of a transistor Q1, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 outputs a third inverting signal.
7. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 4, characterized in that, The second amplification module comprises a non-inverting current mirror circuit, the non-inverting current mirror circuit comprises MOS tubes M8, M10, a transistor Q4 and a transistor Q5, the connection structure of the non-inverting current mirror circuit is the same as that of the inverting current mirror circuit, the gate of the MOS tube M8 receives the first non-inverting signal, and the collector of the transistor Q5 outputs a second non-inverting signal.
8. The amplification circuit for high-speed comparison in a MIPI high-speed interface according to claim 7, characterized in that, The non-inverting current mirror circuit comprises a transistor Q6 which has the same connection structure as the transistor Q1, and the collector of the transistor Q6 outputs a third non-inverting signal.