Clock bias test circuit and device
By designing a clock bias test circuit, the clock bias test operation is simplified by using a control unit and an Ethernet interface unit, solving the problem of cumbersome operation in traditional methods, and realizing efficient clock signal tolerance and fault tolerance testing.
Patent Information
- Application Number
- CN202520122890.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2035-01-17
AI Technical Summary
Traditional clock deflection testing is cumbersome, requiring the original working clock to be disconnected and the deflected clock to be connected, making the process complex.
Design a clock pull-off test circuit. The control unit controls the clock signal generation unit to generate clock signals of different frequencies, and transmits them to the board through the Ethernet interface unit to realize pull-off test and simplify operation.
It simplifies the clock bias test operation, improves test efficiency, and enables convenient testing of the board's tolerance and fault tolerance to clock signals.
Smart Images
Figure CN223772060U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of clock circuit technology, and in particular to a clock bias test circuit and device. Background Technology
[0002] With the continuous development of networks, the testing of network communication quality and reliability during the R&D process has become particularly important. During product testing, a specific device is used to perform a clock bias test on the network interface's operating clock to simulate working conditions under fault conditions and harsh scenarios, testing the product's reliability and fault tolerance. A clock bias tester is a tool used to test clock stress. Typically, the clock of a crystal oscillator on a single board is disconnected and input to the clock bias tester. Then, the clock signal is configured via a host computer to bias the frequency positively or negatively. The biased clock is then sent to the original operating point on the single board to test the board's clock tolerance and fault tolerance. While this testing method can achieve the clock bias function, it requires disconnecting the original operating clock and then connecting the biased clock, making the operation cumbersome. Utility Model Content
[0003] This application aims to propose a clock bias test circuit and device that can solve the problem of cumbersome operation of traditional clock bias technology.
[0004] In a first aspect, embodiments of this application provide a clock bias test circuit, including:
[0005] Control unit;
[0006] An Ethernet interface unit, wherein the control unit is connected to the Ethernet interface unit;
[0007] A clock signal generating unit is included; the control unit is connected to the clock signal generating unit; and the clock signal generating unit is connected to the Ethernet interface unit.
[0008] The control unit is used to control the clock signal generating unit to generate clock signals of different frequencies and output them to the Ethernet interface unit.
[0009] According to some embodiments of this application, the control unit includes:
[0010] The FPGA is connected to the Ethernet interface unit and the clock signal generation unit.
[0011] According to some embodiments of this application, the control unit includes:
[0012] The MCU is connected to the Ethernet interface unit and the clock signal generation unit.
[0013] According to some embodiments of this application, the control unit includes:
[0014] The system-on-chip (SOC) is connected to the Ethernet interface unit and the clock signal generation unit.
[0015] According to some embodiments of this application, the Ethernet interface unit includes:
[0016] An Ethernet PHY chip is provided, the control unit is connected to the Ethernet PHY chip, and the clock signal generation unit is connected to the Ethernet PHY chip.
[0017] According to some embodiments of this application, the Ethernet PHY chip is model RTL9010.
[0018] According to some embodiments of this application, the clock signal generating unit includes:
[0019] Crystal oscillator;
[0020] The PLL chip is connected to the crystal oscillator, the control unit is connected to the PLL chip, and the PLL chip is connected to the Ethernet interface unit.
[0021] According to some embodiments of this application, the PLL chip is model Au5325.
[0022] According to some embodiments of this application, the clock signal generating unit includes:
[0023] A voltage-controlled crystal oscillator (VCO) is provided, the control unit is connected to the VCO, and the VCO is connected to the Ethernet interface unit.
[0024] Secondly, embodiments of this application provide a clock bias test device, including the clock bias test circuit as described above.
[0025] In this embodiment, the clock signal generating unit is controlled by the control unit to generate clock signals of different frequencies and output to the Ethernet interface unit. The signals are then transmitted to the single board through the Ethernet interface unit, thereby testing the single board's tolerance and fault tolerance to clock signals and realizing pull-off testing. The operation is simple and convenient.
[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0027] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein:
[0028] Figure 1A schematic diagram of an embodiment of the clock bias test circuit provided in this application;
[0029] Figure 2 A circuit diagram of the Ethernet PHY chip in an embodiment of the clock bias test circuit provided in this application;
[0030] Figure 3 A circuit diagram of the PLL chip in an embodiment of the clock bias test circuit provided in this application.
[0031] Figure label:
[0032] Control unit 100, Ethernet interface unit 200, crystal oscillator 300, Ethernet interface unit 400. Detailed Implementation
[0033] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0034] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0035] In the description of this application, "multiple" refers to two or more. The use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or the order in which the technical features are indicated.
[0036] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.
[0037] The following reference Figures 1 to 3 This application describes a clock bias test circuit and apparatus according to an embodiment of the present application.
[0038] This application provides a clock bias test circuit, such as... Figure 1 As shown, it includes:
[0039] Control unit 100;
[0040] Ethernet interface unit 200, control unit 100 is connected to Ethernet interface unit 200;
[0041] A clock signal generating unit is connected to the control unit 100, and the clock signal generating unit is connected to the Ethernet interface unit 200.
[0042] The control unit 100 is used to control the clock signal generating unit to generate clock signals of different frequencies and output them to the Ethernet interface unit 200.
[0043] In this embodiment, the control unit 100 is connected to the Ethernet interface unit 200 for data transmission. The control unit 100 controls the clock signal generating unit to generate clock signals of different frequencies and outputs them to the Ethernet interface unit 200 as the working clock. The Ethernet interface unit 200 is connected to the board under test through the network interface to test the board's tolerance and fault tolerance to clock signals, thereby realizing the pull-off test. The operation is simple and convenient.
[0044] In some embodiments of this application, the frequency of the clock signal output by the clock signal generating unit can be set according to the requirements of the pull test. For example, the output clock signal can be based on 48MHz and vary in frequency within the range of -500PPM to 500PPM.
[0045] In some embodiments of this application, the control unit 100 includes:
[0046] The MCU is connected to the Ethernet interface unit 200 and the clock signal generator unit.
[0047] In this embodiment, the MCU can control the clock signal generating unit to generate clock signals of different frequencies. The clock signal generating unit outputs the clock signal to the Ethernet interface unit 200, and the Ethernet interface unit 200 outputs the clock signal to the single board for pull-off test.
[0048] In some embodiments of this application, the control unit 100 includes:
[0049] SOC, SOC connects to Ethernet interface unit 200, SOC connects to clock signal generation unit.
[0050] In this embodiment, the SOC can control the clock signal generating unit to generate clock signals of different frequencies. The clock signal generating unit outputs the clock signal to the Ethernet interface unit 200, and the Ethernet interface unit 200 outputs the clock signal to the board for pull-off testing.
[0051] In some embodiments of this application, the control unit 100 includes:
[0052] FPGA, FPGA connected to Ethernet interface unit 200, FPGA connected to clock signal generation unit.
[0053] In this embodiment, the FPGA can control the clock signal generating unit to generate clock signals of different frequencies. The clock signal generating unit outputs the clock signal to the Ethernet interface unit 200, and the Ethernet interface unit 200 outputs the clock signal to the single board for pull-off test.
[0054] In some embodiments of this application, the Ethernet interface unit 200 includes:
[0055] The Ethernet PHY chip is connected to the control unit 100, and the clock signal generation unit is also connected to the Ethernet PHY chip.
[0056] In this embodiment, the Ethernet interface unit 200 uses an Ethernet PHY chip, such as... Figure 2 As shown, Figure 2 This is a circuit diagram of an Ethernet PHY chip. The control unit 100 is connected to the Ethernet PHY chip for data transmission, and the clock signal generation unit outputs a clock signal to the Ethernet PHY chip.
[0057] In some embodiments of this application, the Ethernet PHY chip is model RTL9010. Other models of Ethernet PHY chips may also be selected depending on the application scenario.
[0058] In some embodiments of this application, such as Figure 1 As shown, the clock signal generation unit includes:
[0059] 300MHz crystal oscillator;
[0060] PLL chip 400, crystal oscillator 300 are connected to PLL chip 400, control unit 100 is connected to PLL chip 400, and PLL chip 400 is connected to Ethernet interface unit 200.
[0061] In this embodiment, such as Figure 2 As shown, Figure 3 The circuit diagram shows the PLL chip 400. The initial clock signal is generated by the crystal oscillator 300 and output to the PLL chip 400. The control unit 100 controls the PLL chip 400 to change the frequency of the initial clock signal, thereby outputting clock signals of different frequencies.
[0062] In some embodiments of this application, the control unit 100 generates pulse signals to control the FDEC pin signal and the FINC pin signal of the PLL chip 400 respectively, thereby realizing the negative bias and positive bias of the initial clock signal. The change of the pulse signal from low to high on the FDEC pin or the FINC pin triggers a frequency change. The control unit 100 controls the number of rising edges of the pulse signal to achieve the biasing of the initial clock signal. The biasing amplitude is the product of the number of rising edges and the step, thereby realizing the biasing function of the initial clock signal.
[0063] In some embodiments of this application, the PLL chip 400 is model number Au5325.
[0064] In this embodiment, the PLL chip 400 used is model Au5325, but other models of PLL chip 400 can also be selected.
[0065] In some embodiments of this application, the clock signal generating unit includes:
[0066] A voltage-controlled crystal oscillator (VCO) is connected to a control unit 100, and the VCO is connected to an Ethernet interface unit 200.
[0067] In this embodiment, the control unit 100 can adjust the frequency of the clock signal output by the voltage-controlled crystal oscillator by adjusting the control voltage of the voltage-controlled crystal oscillator, thereby outputting clock signals of different frequencies for bias testing.
[0068] In addition, this application provides a clock bias test device, including the clock bias test circuit as described above.
[0069] In this embodiment, the clock signal generating unit is controlled by the control unit to generate clock signals of different frequencies and output to the Ethernet interface unit. The signals are then transmitted to the single board through the Ethernet interface unit, thereby testing the single board's tolerance and fault tolerance to clock signals and realizing pull-off testing. The operation is simple and convenient.
[0070] In this embodiment, the control unit 100 is connected to the Ethernet interface unit 200 for data transmission. The control unit 100 controls the clock signal generating unit to generate clock signals of different frequencies and outputs them to the Ethernet interface unit 200 as the working clock. The clock signals are then transmitted to the single board through the Ethernet interface unit 200 to test the single board's tolerance and fault tolerance to clock signals, thereby realizing the pull-off test. The operation is simple and convenient.
[0071] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.
Claims
1. A clock deskewing test circuit, characterized by, The clock pull-off test circuit comprises: a control unit; an Ethernet interface unit, the control unit being connected to the Ethernet interface unit; a clock signal generation unit, the control unit being connected to the clock signal generation unit, the clock signal generation unit being connected to the Ethernet interface unit, wherein the control unit is configured to control the clock signal generation unit to generate clock signals with different frequencies and output to the Ethernet interface unit.
2. The clock pull-pedestal test circuit of claim 1, wherein, The control unit comprises: an FPGA, the FPGA being connected to the Ethernet interface unit, the FPGA being connected to the clock signal generation unit.
3. The clock pull-pd test circuit of claim 1, wherein, The control unit comprises: an MCU, the MCU being connected to the Ethernet interface unit, the MCU being connected to the clock signal generation unit.
4. The clock pull-pd test circuit of claim 1, wherein, The control unit comprises: an SOC, the SOC being connected to the Ethernet interface unit, the SOC being connected to the clock signal generation unit.
5. The clock pull-pd test circuit of claim 1, wherein, The Ethernet interface unit comprises: an Ethernet PHY chip, the control unit being connected to the Ethernet PHY chip, the clock signal generation unit being connected to the Ethernet PHY chip.
6. The clock pull-off test circuit according to claim 5, wherein: the Ethernet PHY chip is of RTL9010 type.
7. The clock pull-pd test circuit of claim 1, wherein, The clock signal generation unit comprises: a crystal oscillator; a PLL chip, the crystal oscillator being connected to the PLL chip, the control unit being connected to the PLL chip, the PLL chip being connected to the Ethernet interface unit.
8. The clock pull-off test circuit according to claim 7, wherein: the PLL chip is of Au5325 type.
9. The clock pullout test circuit of claim 1, wherein, The clock signal generation unit comprises: a voltage-controlled crystal oscillator, the control unit being connected to the voltage-controlled crystal oscillator, the voltage-controlled crystal oscillator being connected to the Ethernet interface unit.
10. A clock deskewing test apparatus, characterized by, The clock pull-off test circuit comprises the clock pull-off test circuit according to any one of claims 1 to 9.