Low-loss power MOS device
By introducing a second trench and gate design into the MOS device, the electric field distribution is optimized, which solves the high loss problem of the MOS device in the high frequency turn-on and turn-off switching states, and achieves the effect of low loss and low resistance.
Patent Information
- Application Number
- CN202423227952.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2034-12-26
AI Technical Summary
Existing MOS devices have significant power losses during high-frequency switching between turn-on and turn-off, and also have high resistance during forward conduction.
Introducing specific structural designs into MOS devices, including setting a second trench in the upper part of the P-type base region and in the N-type epitaxial region, and filling the trench with a metal layer, combined with the design of the gate portion and the gate oxide layer, to optimize the electric field distribution.
It effectively reduces the power loss of MOS devices in high-frequency turn-on and turn-off switching states, and significantly reduces the resistance during forward conduction, thereby reducing the normal operation loss of the devices.
Smart Images
Figure CN223772420U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of MOS device technology, and in particular to a low-loss power MOS device. Background Technology
[0002] MOS devices are indispensable electronic components in electronic systems, primarily used in various power supplies and drive loads. With the continuous upgrading of power semiconductor devices, new power semiconductor devices are increasingly developing towards achieving energy savings, material conservation, environmental friendliness, and miniaturization. Existing MOS devices exhibit significant power losses during high-frequency switching between on and off states, and improving this has become a focus of research for those skilled in the art. Summary of the Invention
[0003] The purpose of this invention is to provide a low-loss power MOS device that reduces the power loss of the MOS device during high-frequency switching between turn-on and turn-off, and also significantly reduces the resistance of the MOS device during forward conduction, thereby reducing the loss during normal operation.
[0004] To achieve the above objectives, the technical solution adopted by this utility model is: a low-loss power MOS device, comprising: a P-type base region located on the upper part of a silicon wafer and a heavily doped N-type drain region located on the lower part of a silicon wafer, wherein an N-type epitaxial region is disposed between the P-type base region and the heavily doped N-type drain region;
[0005] A first trench located in the P-type base region extends from the upper surface of the P-type base region to the N-type epitaxial region. An insulating dielectric layer covers the upper surface of the first trench and extends to the surrounding area of the first trench. An upper metal layer covers the P-type base region and the upper surface of the insulating dielectric layer. A lower metal layer is located on the surface of the heavily doped N-type drain region opposite to the N-type epitaxial region.
[0006] The upper part of the P-type base region and the periphery of the first trench have a heavily doped N-type source region. The first trench has a gate portion, and the gate portion and the first trench are filled with a gate oxide layer.
[0007] The gate portion has a protrusion in the middle. In the vertical direction, the upper end face of the protrusion is located between the lower surface of the heavily doped N-type source region and the lower surface of the P-type base region, and the lower end face of the protrusion is located below the P-type base region. The heavily doped N-type source region has a second trench on the side away from the first trench. This second trench extends from the upper surface of the P-type base region into the N-type epitaxial region, and the upper metal layer is filled in the second trench.
[0008] The following are further improvements to the above technical solution:
[0009] 1. In the above scheme, the lower end face of the second groove is higher than the lower end face of the first groove in the vertical direction.
[0010] 2. In the above scheme, both the upper metal layer and the lower metal layer are copper layers or aluminum layers.
[0011] 3. In the above scheme, the depth of the first trench is 2 to 4 times the depth of the P-type base region.
[0012] 4. In the above scheme, the second trench is isolated from the heavily doped N-type source region through the P-type base region.
[0013] Due to the application of the above technical solution, this utility model has the following advantages compared with the prior art:
[0014] 1. The present invention relates to a low-loss power MOS device, wherein the heavily doped N-type source region has a second trench on the side away from the first trench. The second trench extends from the upper surface of the P-type base region to the N-type epitaxial region. The second trench is filled with the upper metal layer, which effectively reduces the turn-on voltage of the MOS device and reduces the power loss of the MOS device in the high-frequency turn-on and turn-off switching state.
[0015] 2. The present invention relates to a low-loss power MOS device, wherein a gate portion is provided in a trench, and a gate oxide layer is filled between the gate portion and the trench. The middle part of the gate portion has an outward protrusion. In the vertical direction, the upper end face of the outward protrusion is located between the lower surface of the heavily doped N-type source region and the lower surface of the P-type base region, and the lower end face of the outward protrusion is located below the P-type base region. This improves the electric field at the junction of the heavily doped N-type source region and the P-type base region, which is beneficial to significantly reduce the resistance of the MOS device during forward conduction, thereby reducing the loss of the device during normal operation. Attached Figure Description
[0016] Appendix Figure 1 This is a schematic diagram of the structure of the low-loss power MOS device of this utility model.
[0017] In the above figures: 1. Silicon wafer; 2. P-type base region; 3. Heavily doped N-type drain region; 4. N-type epitaxial region; 5. First trench; 6. Insulating dielectric layer; 7. Upper metal layer; 8. Lower metal layer; 9. Gate portion; 10. Gate oxide layer; 11. Outward protrusion; 12. Heavily doped N-type source region; 13. Second trench. Detailed Implementation
[0018] The present patent can be further understood through the specific embodiments given below, but they are not intended to limit the present patent.
[0019] Example 1: A low-loss power MOS device, comprising: a P-type base region 2 located on the upper part of a silicon wafer 1 and a heavily doped N-type drain region 3 located on the lower part of the silicon wafer 1, wherein an N-type epitaxial region 4 is disposed between the P-type base region 2 and the heavily doped N-type drain region 3;
[0020] A first trench 5 located in the P-type base region 2 extends from the upper surface of the P-type base region 2 into the N-type epitaxial region 4. An insulating dielectric layer 6 covers the upper surface of the first trench 5 and extends to the peripheral area of the first trench 5. An upper metal layer 7 covers the upper surface of the P-type base region 2 and the upper surface of the insulating dielectric layer 6. A lower metal layer 8 is located on the surface of the heavily doped N-type drain region 3 opposite to the N-type epitaxial region 4.
[0021] The upper part of the P-type base region 2 and the periphery of the first trench 5 have a heavily doped N-type source region 12. The first trench 5 has a gate portion 9, and the gate portion 9 and the first trench 5 are filled with a gate oxide layer 10.
[0022] The gate portion 9 has a protrusion 11 in the middle. In the vertical direction, the upper end face of the protrusion 11 is located between the lower surface of the heavily doped N-type source region 12 and the lower surface of the P-type base region 2. The lower end face of the protrusion 11 is located below the P-type base region 2. The heavily doped N-type source region 12 has a second trench 13 on the side away from the first trench 5. This second trench 13 extends from the upper surface of the P-type base region 2 into the N-type epitaxial region 4. The upper metal layer 7 is filled in the second trench 13.
[0023] The lower end face of the second groove 13 is higher than the lower end face of the first groove 5 in the vertical direction.
[0024] Both the upper metal layer 7 and the lower metal layer 8 mentioned above are aluminum layers.
[0025] The depth of the first trench 5 is three times the depth of the P-type base region 2.
[0026] The second trench 13 is isolated from the heavily doped N-type source region 12 by the P-type base region 2.
[0027] Example 2: A low-loss power MOS device, comprising: a P-type base region 2 located on the upper part of a silicon wafer 1 and a heavily doped N-type drain region 3 located on the lower part of the silicon wafer 1, wherein an N-type epitaxial region 4 is disposed between the P-type base region 2 and the heavily doped N-type drain region 3;
[0028] A first trench 5 located in the P-type base region 2 extends from the upper surface of the P-type base region 2 into the N-type epitaxial region 4. An insulating dielectric layer 6 covers the upper surface of the first trench 5 and extends to the peripheral area of the first trench 5. An upper metal layer 7 covers the upper surface of the P-type base region 2 and the upper surface of the insulating dielectric layer 6. A lower metal layer 8 is located on the surface of the heavily doped N-type drain region 3 opposite to the N-type epitaxial region 4.
[0029] The upper part of the P-type base region 2 and the periphery of the first trench 5 have a heavily doped N-type source region 12. The first trench 5 has a gate portion 9, and the gate portion 9 and the first trench 5 are filled with a gate oxide layer 10.
[0030] The gate portion 9 has a protrusion 11 in the middle. In the vertical direction, the upper end face of the protrusion 11 is located between the lower surface of the heavily doped N-type source region 12 and the lower surface of the P-type base region 2. The lower end face of the protrusion 11 is located below the P-type base region 2. The heavily doped N-type source region 12 has a second trench 13 on the side away from the first trench 5. This second trench 13 extends from the upper surface of the P-type base region 2 into the N-type epitaxial region 4. The upper metal layer 7 is filled in the second trench 13.
[0031] The lower end face of the second groove 13 is higher than the lower end face of the first groove 5 in the vertical direction.
[0032] Both the upper metal layer 7 and the lower metal layer 8 mentioned above are copper layers.
[0033] The depth of the first trench 5 is 3.6 times the depth of the P-type base region 2.
[0034] The second trench 13 is isolated from the heavily doped N-type source region 12 by the P-type base region 2.
[0035] When the aforementioned low-loss power MOS device is used, it effectively reduces the turn-on voltage of the MOS device and reduces the power loss of the MOS device in the high-frequency turn-on and turn-off switching state. In addition, it improves the electric field at the junction of the heavily doped N-type source region and P-type base region, which is beneficial to significantly reduce the resistance of the MOS device during forward conduction, thereby reducing the loss when the device is operating normally.
[0036] The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to understand the content of this utility model and implement it accordingly. They should not be construed as limiting the scope of protection of this utility model. All equivalent changes or modifications made in accordance with the spirit and essence of this utility model should be included within the scope of protection of this utility model.
Claims
1. A low-loss power MOS device characterized by: The application relates to a silicon chip, which comprises: a P-type base region (2) on the upper part of a silicon chip (1) and a heavily doped N-type drain region (3) on the lower part of the silicon chip (1), wherein an N-type epitaxial region (4) is arranged between the P-type base region (2) and the heavily doped N-type drain region (3); a first groove (5) is arranged in the P-type base region (2) and extends from the upper surface of the P-type base region (2) into the N-type epitaxial region (4), an insulating dielectric layer (6) covers the upper surface of the first groove (5) and extends to the peripheral region of the first groove (5), an upper metal layer (7) covers the upper surface of the P-type base region (2) and the insulating dielectric layer (6), and a lower metal layer (8) is arranged on the surface of the heavily doped N-type drain region (3) which is opposite to the N-type epitaxial region (4); a heavily doped N-type source region (12) is arranged in the upper part of the P-type base region (2) and at the periphery of the first groove (5), a gate part (9) is arranged in the first groove (5), and a gate oxide layer (10) is filled between the gate part (9) and the first groove (5); the middle part of the gate part (9) is provided with a convex part (11), the upper end surface of the convex part (11) is located between the lower surface of the heavily doped N-type source region (12) and the lower surface of the P-type base region (2) in the vertical direction, and the lower end surface of the convex part (11) is located below the P-type base region (2); the side of the heavily doped N-type source region (12) which is away from the first groove (5) is provided with a second groove (13), the second groove (13) extends from the upper surface of the P-type base region (2) into the N-type epitaxial region (4), and the second groove (13) is filled with the upper metal layer (7). The lower end surface of the second groove (13) is higher than the lower end surface of the first groove (5) in the vertical direction. The upper metal layer (7) and the lower metal layer (8) are copper layers or aluminum layers. The depth of the first groove (5) is 2-4 times the depth of the P-type base region (2). The second groove (13) and the heavily doped N-type source region (12) are isolated by the P-type base region (2).
2. The low-loss power MOS device of claim 1, wherein: 3. The low-loss power MOS device of claim 1, wherein: 4. The low-loss power MOS device of claim 1, wherein: 5. The low-loss power MOS device of claim 1, wherein: