Programmable logic device test experiment device
By designing a test experimental device for programmable logic devices, the problems of high cost and inflexible environment of traditional FPGA chip test equipment are solved, realizing portable and comprehensive testing, and ensuring the functional correctness and performance optimization of FPGA chips.
Patent Information
- Application Number
- CN202520296096.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2035-02-24
AI Technical Summary
Traditional FPGA chip testing methods require large-scale testing equipment, which is costly and inflexible in terms of testing environment, making it difficult to fully cover the chip's functions and advanced features.
Design a test experimental device for programmable logic devices, including a replaceable FPGA test circuit, a phase-locked loop test circuit, a pulse width modulation test circuit, a chip power supply circuit, a serial port test circuit, a bank area power supply test circuit, and a power generation circuit. Combined with an LCD display control circuit, it can realize multi-parameter testing and flexible configuration.
It enables portable and comprehensive FPGA chip testing, allowing for in-depth verification of advanced features and boundary conditions, improving product reliability and stability, and providing rich performance data support.
Smart Images
Figure CN223784447U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of testing experiments for logic devices, and in particular to a testing experimental device for programmable logic devices. Background Technology
[0002] FPGA (Field-Programmable Gate Array) is a product further developed from programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), solving the shortcomings of custom circuits while overcoming the limitation of the limited gate count of original programmable devices.
[0003] FPGA chips offer high programmability, allowing users to reconfigure their internal logic and I / O modules to meet diverse application requirements. This flexibility enables FPGAs to perform a wide range of tasks, from simple digital circuits to complex system-level designs. FPGA chips integrate a large number of logic gates, memory, and interconnect resources, enabling high-speed, parallel data processing and computation. This high-performance characteristic gives FPGAs a significant advantage in scenarios requiring high-speed data processing and computation.
[0004] Compared to traditional application-specific integrated circuit (ASIC) design flows, FPGA development cycles are shorter, enabling rapid response to market demands and reducing development costs. Due to their programmability, high performance, and short development cycles, FPGA chips are widely used in various fields, including but not limited to communications, data centers, automotive electronics, industrial control, and artificial intelligence.
[0005] Due to the widespread application of FPGA chips in many critical fields, their performance and reliability are crucial to the stability and security of the entire system. Therefore, comprehensive testing of FPGA chips is a necessary means to ensure their quality and reliability. Testing not only verifies whether the FPGA chip's functionality meets design requirements but also identifies potential defects and problems for timely repair and improvement.
[0006] However, traditional FPGA chip testing methods typically require large-scale testing equipment, which not only results in high testing costs and limited testing chip variety, but also restricts the flexibility of the testing environment.
[0007] Therefore, it is necessary to propose a test apparatus for programmable logic devices to solve the above problems. Utility Model Content
[0008] The main purpose of this invention is to provide a test apparatus for programmable logic devices, which can effectively solve the problems in the background art.
[0009] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0010] An experimental setup for testing programmable logic devices includes a replaceable FPGA test circuit, a phase-locked loop (PLL) test circuit, a pulse-width modulation (PWM) test circuit, a chip power supply circuit, a serial port test circuit, a Bank area power supply test circuit, a power generation circuit, and a liquid crystal display (LCD) control circuit. The replaceable FPGA test circuit is electrically connected to the PLL test circuit, the PWM test circuit, the chip power supply circuit, the serial port test circuit, and the Bank area power supply test circuit. The Bank area power supply test circuit is electrically connected to the power generation circuit and the LCD control circuit. The serial port test circuit is electrically connected to the LCD control circuit, and the LCD control circuit is electrically connected to the chip power supply circuit.
[0011] Preferably, the replaceable FPGA test circuit is the main part of the test device, and is connected to the main test circuit via a connector for replacing different FPGA chips.
[0012] Preferably, the phase-locked loop (PLL) of the phase-locked loop test circuit is used to verify the performance and stability of the PLL inside the FPGA, including the accuracy of the clock signal, frequency division, phase shift, duty cycle adjustment, and anti-interference capability. It includes input signal terminals, the input signal is provided by a signal generator, and the input signal is connected to the FPGA_FIN and FPGA_FOUT pins of the replaceable FPGA test circuit.
[0013] Preferably, the pulse width modulation test circuit is used to verify the control effect of frequency and duty cycle on pulse width modulation, and is used to perform pulse width modulation test by outputting PWM waveforms with different frequencies, different duty cycles and two complementary outputs.
[0014] Preferably, the chip power supply circuit is used to provide a stable and reliable power supply for the replaceable FPGA test circuit. The chip power supply circuit includes two different power input methods: one is to use a digital source meter for power supply, which is connected to the replaceable FPGA test circuit through terminals VIN+ and VIN-; the other is to use a linear voltage regulator circuit for power supply. The two power supply methods are switched using a relay K1.
[0015] Preferably, the serial port test circuit is used to verify the correctness of the FPGA serial port communication function, including data transmission rate, data format, error detection and correction. The serial port test circuit includes a relay K3 switch for switching data transmission and reception modes. The Bank area power supply test circuit is used to verify the effect of the Bank's power supply voltage on the output level of the IO port. The Bank area power supply test circuit includes second source meter input terminals GPIO1, GPIO2, VSS and a power supply relay K2, used to switch different voltages to provide power to different Bank areas.
[0016] Preferably, the power generation circuit is the power management system of the entire test experimental device, responsible for providing the required voltage and current to all test circuits and FPGA chips. The power generation circuit includes three different voltage regulation circuits: 1.2V, 2.5V, and 3.3V. The LCD display control circuit includes an LCD screen and an instruction conversion circuit. The LCD screen displays switching buttons for chip power supply, serial port circuit, and Bank area power supply. Different circuits are switched by touching different buttons. The instruction conversion circuit converts the button input on the LCD screen into electrical signals that can be recognized by relays, controlling relay switches K1, K2, and K3.
[0017] Compared with the prior art, the present invention has the following beneficial effects:
[0018] This programmable logic device (FPGA) testing experimental device combines an LCD screen with an FPGA functional test board, eliminating the need for large testing machines found in traditional testing equipment. This makes the testing system more portable. By writing multiple self-test programs, this solution can achieve comprehensive testing of the FPGA chip's functions. This means that not only can the basic logic functions of the FPGA be tested, but its advanced characteristics and boundary conditions can also be verified in depth, thereby more comprehensively ensuring the functional correctness of the FPGA chip. This comprehensive testing method helps to identify and resolve potential problems in advance, improving product reliability and stability.
[0019] This programmable logic device (FPGA) testing apparatus performs tests on various parameters of different FPGA chips, including but not limited to key parameters such as power consumption, clock frequency, and input / output latency. This multi-parameter testing capability allows engineers to fully understand the performance characteristics of FPGA chips, providing rich data support for chip selection, system design, and optimization. Furthermore, the test program and parameter settings can be flexibly adjusted for different models and specifications of FPGA chips to adapt to diverse testing needs. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the overall structure of this utility model;
[0021] Figure 2 This is the PCB diagram of this utility model;
[0022] Figure 3 This is a flowchart of the present invention;
[0023] Figure 4 This is the circuit diagram for PLL testing of this utility model;
[0024] Figure 5 This is the circuit diagram of the power supply and switch of this utility model;
[0025] Figure 6 This is a circuit diagram of the chip power supply for this utility model.
[0026] Figure 7 This is the circuit diagram of the connector of this utility model;
[0027] Figure 8 This is the circuit diagram for PWM testing of this utility model;
[0028] Figure 9 This is the circuit diagram for serial port testing of this utility model;
[0029] Figure 10 This is a circuit diagram illustrating the GPIO characteristics of this utility model;
[0030] Figure 11 This is a circuit diagram of the inter-board connection and power supply of this utility model;
[0031] Figure 12 This is the circuit diagram of the status light of this utility model;
[0032] Figure 13 This is the circuit diagram of the BNC lamp and LOGO lamp of this utility model.
[0033] In the diagram: 1. Replaceable FPGA test circuit; 2. Phase-locked loop test circuit; 3. Pulse width modulation test circuit; 4. Chip power supply circuit; 5. Serial port test circuit; 6. Bank area power supply test circuit; 7. Power generation circuit; 8. LCD display control circuit. Detailed Implementation
[0034] To make the technical means, creative features, objectives and effects of this utility model easier to understand, the present utility model will be further described below in conjunction with specific embodiments.
[0035] Example 1:
[0036] like Figures 1-13As shown, a test apparatus for programmable logic devices includes a replaceable FPGA test circuit 1, a phase-locked loop test circuit 2, a pulse width modulation test circuit 3, a chip power supply circuit 4, a serial port test circuit 5, a Bank area power supply test circuit 6, a power generation circuit 7, and a liquid crystal display control circuit 8. The replaceable FPGA test circuit 1 is electrically connected to the phase-locked loop test circuit 2, the pulse width modulation test circuit 3, the chip power supply circuit 4, the serial port test circuit 5, and the Bank area power supply test circuit 6. The Bank area power supply test circuit 6 is electrically connected to the power generation circuit 7 and the liquid crystal display control circuit 8. The serial port test circuit 5 is electrically connected to the liquid crystal display control circuit 8. The liquid crystal display control circuit 8 is electrically connected to the chip power supply circuit 4.
[0037] The replaceable FPGA test circuit 1 is the main part of the test device. It is connected to the main test circuit via a connector and is used to replace different FPGA chips.
[0038] The phase-locked loop (PLL) of the phase-locked loop test circuit 2 is used to verify the performance and stability of the PLL inside the FPGA, including the accuracy of the clock signal, frequency division, phase shift, duty cycle adjustment, and anti-interference capability. It includes input signal terminals, and the input signals are provided by a signal generator. The input signals are connected to the FPGA_FIN and FPGA_FOUT pins of the replaceable FPGA test circuit 1.
[0039] The pulse width modulation test circuit 3 is used to verify the control effect of frequency and duty cycle on pulse width modulation. It is used to perform pulse width modulation tests by outputting PWM waveforms with different frequencies, different duty cycles, and two complementary outputs.
[0040] The chip power supply circuit 4 is used to provide a stable and reliable power supply for the replaceable FPGA test circuit 1. The chip power supply circuit 4 includes two different power input methods. One is to use a digital source meter for power supply, which is connected to the replaceable FPGA test circuit 1 through the terminals VIN+ and VIN-. The other is to use a linear voltage regulator circuit for power supply. The two power supply methods are switched using a relay K1.
[0041] The serial port test circuit 5 is used to verify the correctness of the FPGA serial communication function, including data transmission rate, data format, error detection and correction. The serial port test circuit 5 includes a relay K3 switch for switching data transmission and reception modes. The Bank area power supply test circuit 6 is used to verify the effect of the Bank's power supply voltage on the output level of the IO port. The Bank area power supply test circuit 6 includes the second source meter input terminals GPIO1, GPIO2, VSS and the power supply relay K2, which is used to switch different voltages to provide power to different Bank areas.
[0042] The power generation circuit 7 is the power management system for the entire test experimental device, responsible for providing the required voltage and current to all test circuits and FPGA chips. The power generation circuit includes three different voltage regulator circuits: 1.2V, 2.5V, and 3.3V. The LCD display control circuit 8 includes an LCD screen and an instruction conversion circuit. The LCD screen displays switching buttons for chip power supply, serial port circuit, and Bank area power supply. Different circuits can be switched by touching different buttons. The instruction conversion circuit converts the button inputs on the LCD screen into electrical signals that can be recognized by the relays, controlling relay switches K1, K2, and K3.
[0043] It should be noted that this utility model is a test experimental device for programmable logic devices. When using it... Figure 3 As shown, connect the power supply of the programmable logic device test experimental device to the power socket of the test bench, and turn on the power switch of the programmable logic device test experimental device. At this time, the indicator light on the experimental circuit board will light up, the screen will light up, and it will enter the working state.
[0044] Connect the red terminal of FORCE_HI of the first digital source meter to VIN+ of the programmable logic device test experiment device, and the black terminal FORCE_LO to VIN- of the programmable logic device test experiment device. Set the source meter to voltage source and current detection mode, set the voltage to 5V, and limit the current to 500mA. At this time, the first digital source meter supplies power to the programmable logic device test experiment device.
[0045] Connect the red terminal FORCE_HI of the second digital source table to GPIO1 of the programmable logic device test experiment device, and the black terminal FORCE_LO to VSS of the programmable logic device test experiment device, and set the source table to Voltmeter mode.
[0046] Based on the selected FPGA chip, download the corresponding self-test program to the experimental board;
[0047] First, click the chip power-on button to power the chipset. Then, click the 3.3V or 2.5V button to power the Bank area. Select the chip Bank0 test experiment to start the test.
[0048] Specifically designed for testing the power supply and functionality of the Bank0 area of a programmable logic device (FPGA).
[0049] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection of this utility model is defined by the appended claims and their equivalents.
Claims
1. A test apparatus for programmable logic devices, comprising a replaceable FPGA test circuit (1), a phase-locked loop test circuit (2), a pulse width modulation test circuit (3), a chip power supply circuit (4), a serial port test circuit (5), a Bank area power supply test circuit (6), a power generation circuit (7), and a liquid crystal display control circuit (8), characterized in that: The replaceable FPGA test circuit (1) is electrically connected to the phase-locked loop test circuit (2), pulse width modulation test circuit (3), chip power supply circuit (4), serial port test circuit (5), and Bank area power supply test circuit (6). The Bank area power supply test circuit (6) is electrically connected to the power generation circuit (7) and the liquid crystal display control circuit (8). The serial port test circuit (5) is electrically connected to the liquid crystal display control circuit (8). The liquid crystal display control circuit (8) is electrically connected to the chip power supply circuit (4).
2. The experimental apparatus for testing programmable logic devices according to claim 1, characterized in that: The replaceable FPGA test circuit (1) is the main part of the test device. It is connected to the main test circuit via a connector and is used to replace different FPGA chips.
3. The experimental apparatus for testing programmable logic devices according to claim 1, characterized in that: The phase-locked loop test circuit (2) is used to verify the performance and stability of the PLL inside the FPGA, including the accuracy of the clock signal, frequency division, phase shift, duty cycle adjustment and anti-interference capability. It includes input signal terminals, the input signal is provided by the signal generator, and the input signal is connected to the FPGA_FIN and FPGA_FOUT pins of the replaceable FPGA test circuit (1).
4. The experimental apparatus for testing programmable logic devices according to claim 1, characterized in that: The pulse width modulation test circuit (3) is used to verify the control effect of frequency and duty cycle on pulse width modulation, and is used to perform pulse width modulation test by outputting PWM waveforms with different frequencies, different duty cycles and two complementary outputs.
5. The experimental apparatus for testing programmable logic devices according to claim 1, characterized in that: The chip power supply circuit (4) is used to provide a stable and reliable power supply for the replaceable FPGA test circuit (1). The chip power supply circuit (4) includes two different power input methods. One is to use a digital source meter for power supply. The digital source meter is connected to the replaceable FPGA test circuit (1) through the terminals VIN+ and VIN-. The other is to use a linear voltage regulator circuit for power supply. The two power supply methods are switched using a relay K1.
6. The experimental apparatus for testing programmable logic devices according to claim 1, characterized in that: The serial port test circuit (5) is used to verify the correctness of the FPGA serial port communication function, including data transmission rate, data format, error detection and correction. The serial port test circuit (5) includes a relay K3 switch for switching the data transmission and reception mode. The Bank area power supply test circuit (6) is used to verify the effect of the Bank's power supply voltage on the output level of the IO port. The Bank area power supply test circuit (6) includes the second source table input terminals GPIO1, GPIO2, VSS and the power supply connection relay K2, which is used to switch different voltages to provide power to different Bank areas.
7. The experimental apparatus for testing programmable logic devices according to claim 1, characterized in that: The power generation circuit (7) is the power management system for the entire test experimental device, responsible for providing the required voltage and current to all test circuits and FPGA chips. The power generation circuit includes three different voltage regulation circuits: 1.2V, 2.5V, 3.3V; The liquid crystal display control circuit (8) includes a liquid crystal display screen and an instruction conversion circuit; The liquid crystal display screen displays the switching buttons for chip power supply, serial port circuit, and Bank area power supply, and the corresponding circuit can be switched by touching different buttons; The instruction conversion circuit converts the button quality of the liquid crystal display screen into an electrical signal that can be recognized by the relay, and controls the relay switches K1, K2, and K3.