CANFD communication device and system

Abstract

The utility model discloses a CANFD communication device and a CANFD communication system. The CANFD communication device comprises a processor module, the processor module comprises a processing unit, a frequency register, a phase register and a CANFD controller, and the processing unit is used for writing a preset clock frequency into the frequency register, writing a preset clock phase into the clock register and outputting the value of the frequency register and the value of the phase register; the programmable logic module comprises a conversion unit and a clock generation unit, and the conversion unit is used for receiving the value of the frequency register and converting the value into a frequency adjusting signal, and receiving the value of the phase register and converting the value into a phase adjusting signal; and the clock generation unit is used for generating a clock signal with a preset clock frequency and a clock phase according to the frequency adjustment signal and the phase adjustment signal and sending the clock signal to the CANFD controller, so that the CANFD controller communicates with at least one CANFD node. The CANFD clock is generated by using the programmable logic module and does not depend on a transmission delay compensation mechanism, so that the operation efficiency of the processor module is effectively improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a CANFD communication device and system. Background Technology

[0002] CANFD (CAN with Flexible Data-Rate) is an interface technology that significantly enhances the classic CAN (Controller Area Network) protocol. When applied to a CPU (Central Processing Unit), CANFD offers significant advantages over traditional CAN. Its single-frame data length can be extended from 8 bytes to 64 bytes, and the data segment transmission rate can reach up to 8 Mbps (megabits per second), greatly improving data transmission efficiency and flexibility. While traditional CAN's maximum baud rate is only 1 Mbps, CANFD's data segment baud rate can be much higher, such as 2 Mbps, 4 Mbps, or 8 Mbps. Due to the increased baud rate of the CANFD data segment, the bit time of the CANFD data segment is correspondingly shortened, which places more stringent requirements on clock accuracy.

[0003] In traditional implementations, the CPU clock is typically divided to generate the CANFD clock. For example, an 8-division operation might be performed initially. However, after this 8-division, further division may be necessary depending on the actual load, often resulting in a remainder and inaccurate clock frequency, which can easily lead to communication failures. Previously, this problem was typically solved by adding a transmit delay compensation (TDC) mechanism. However, the TDC mechanism is complex and cannot be precisely adjusted using mathematical algorithms; therefore, even with TDC, errors are still difficult to avoid. Utility Model Content

[0004] In view of the above problems, this application provides a CANFD communication device and system to solve the above technical problems.

[0005] In a first aspect, this application provides a CANFD communication device, including a processor module and a programmable logic module;

[0006] The processor module includes a processing unit, a frequency register, a phase register, and a CANFD controller.

[0007] The processing unit is communicatively connected to the phase register, the frequency register, and the programmable logic module, respectively, to write a preset clock frequency to the frequency register, write a preset clock phase to the clock register, and output the values ​​of the frequency register and the phase register to the programmable logic module.

[0008] The programmable logic module includes a conversion unit and a clock generation unit.

[0009] The conversion unit is communicatively connected to the processor module and the clock generation unit respectively, to receive the value of the frequency register and convert it into a frequency adjustment signal, and to receive the value of the phase register and convert it into a phase adjustment signal;

[0010] The clock generation unit is also communicatively connected to the CANFD controller to generate a clock signal with a preset clock frequency and a preset clock phase according to the frequency adjustment signal and the phase adjustment signal, and send it to the CANFD controller for communication between the CANFD controller and at least one CANFD node.

[0011] In a second aspect, this application provides a CANFD communication system, including at least one CANFD node of the CANFD communication device described in the first aspect above, wherein the at least one CANFD node is connected to the CANFD controller via a CANFD bus.

[0012] The CANFD communication device and system provided in this application, wherein the CANFD communication device writes a preset clock frequency and a preset clock phase to its frequency register through the processing unit of the processor module, and then outputs the values ​​of the frequency register and the phase register to the programmable logic module. The conversion unit of the programmable logic module converts the value of the frequency register into a frequency adjustment signal and the value of the phase register into a phase adjustment signal. The clock generation unit of the programmable logic module generates a clock signal with the preset clock frequency and the preset clock phase according to the frequency adjustment signal and the phase adjustment signal, and sends it to the CANFD controller. Finally, the CANFD controller connects multiple... Each node communicates with the other node by generating a clock signal according to the clock generation module. The CANFD communication device provided in this application realizes the stepless continuous adjustment function of the CANFD clock by adjusting the values ​​of the frequency register and the phase register. The use of a programmable logic module to generate the CANFD clock for the processor module effectively solves the problem of inaccurate frequency caused by the remainder generated by the clock division in the traditional solution. Furthermore, the use of a programmable logic module to generate the CANFD clock for the processor module in this application eliminates the need to rely on the transmission delay compensation mechanism to perform delay compensation on the CANFD clock generated by the frequency division of the processor module. Therefore, the processor does not need to handle the complex logic of the transmission delay compensation mechanism, which improves the operating efficiency of the processor module.

[0013] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A schematic diagram of the CANFD communication device provided in an embodiment of this application is shown.

[0016] Figure 2 This paper shows another schematic diagram of a CANFD communication device provided in an embodiment of this application.

[0017] Figure 3 This illustration shows another module diagram of the CANFD communication device provided in an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0020] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0021] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0022] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0023] The CPU typically divides its clock to generate the CANFD clock. For example, it might first perform an 8-fold division. However, after this 8-fold division, the actual load may necessitate further division, often resulting in a remainder and inaccurate clock frequency, which can easily lead to communication failures. Previously, this problem was typically solved by adding a Transmit Delay Compensation (TDC) mechanism. However, the TDC mechanism is complex and cannot be precisely adjusted using mathematical algorithms. Therefore, even with TDC, errors are still difficult to prevent.

[0024] Taking a 125MHz input clock as an example, after being divided by 8 internally by the CPU, if the data domain frequency of the CANFD data frame needs to be further divided by 9, the calculated data domain frequency is 1.953MHz. In this case, to achieve sampling at integer multiples of the frequency, only a transmission delay compensation method can be used.

[0025] In view of the above-mentioned technical problems, embodiments of this application provide a CANFD communication device. Figure 1 A schematic diagram of the CANFD communication device provided in an embodiment of this application is shown, such as... Figure 1 As shown, the device includes a processor module and a programmable logic module.

[0026] The processor module includes a processing unit, a frequency register, a phase register, and a CANFD controller. The processing unit is communicatively connected to the phase register, the frequency register, and the programmable logic module, respectively. It is used to write a preset clock frequency to the frequency register and a preset clock phase to the clock register. Subsequently, the processing unit outputs the values ​​of the frequency register and the phase register to the programmable logic module. The frequency register and the phase register are used to store the clock frequency and the clock phase, respectively. Optionally, the preset clock frequency and clock phase are the CANFD clock signal required by the CANFD controller. In this embodiment, the clock frequency and clock phase required by the CANFD controller can be calculated in advance and written as preset values ​​by the processing unit into the frequency register and the phase register.

[0027] The programmable logic module (PLM) includes a conversion unit and a clock generation unit. The conversion unit is communicatively connected to both the processor module and the clock generation unit. It receives the value of a frequency register and converts it into a frequency adjustment signal, and receives the value of a phase register and converts it into a phase adjustment signal. The clock generation unit is communicatively connected to the conversion unit and the CANFD controller. It generates a clock signal with a preset clock frequency and a preset clock phase based on the frequency and phase adjustment signals, and sends it to the CANFD controller. The CANFD controller communicates with at least one external CANFD node (node ​​1 to node n) through this clock signal. Optionally, the conversion unit converts the signal sent by the processor module into a signal recognizable by the PLM so that the clock generation unit can recognize the signal.

[0028] It is understood that in this application embodiment, there are no restrictions on the specific devices / modules of the CANFD node, as long as the CANFD node conforms to the communication protocol for communicating with the CANFD controller. For example, the CANFD communication node can be an electronic control unit (ECU), sensor, MCU, etc. that has a communication protocol for communicating with the CANFD controller.

[0029] It is understood that the detailed circuit structures of the conversion unit and clock generation unit are not limited in this embodiment. This is because the specific circuit structures of the conversion unit and clock generation unit belong to the prior art, and within the scope of the prior art in this field, there are already a variety of mature and widely used circuit structure design schemes. These prior arts cover a variety of different implementation methods, based on different electronic components and circuit principles, and can meet the conversion and clock generation functions under different application scenarios and performance requirements. Whether using analog circuits, digital circuits, or hybrid circuits combining the two, those skilled in the art can select appropriate circuit structures from the existing technology reserves to implement the functions of the conversion unit and clock generation unit according to the actual situation and design requirements.

[0030] The CANFD communication device provided in this application embodiment can adjust the values ​​of the frequency register and the phase register in real time, thereby realizing the stepless continuous adjustment function of the CANFD clock. This CANFD communication device also uses a programmable logic module to generate the CANFD clock for the processor module, effectively solving the problem of inaccurate CANFD clock frequency caused by the remainder generated by clock division in traditional solutions. Furthermore, since this application uses a programmable logic module to generate the CANFD clock for the processor module, it does not need to rely on a transmission delay compensation mechanism to compensate for the delay of the CANFD clock generated by the processor module's frequency division. Therefore, the processor does not need to handle the complex logic of the transmission delay compensation mechanism, improving the operating efficiency of the processor module.

[0031] In some embodiments, Figure 2 This illustration shows another module diagram of the CANFD communication device provided in this application embodiment. In the CANFD communication device provided in this application embodiment, the CANFD controller is communicatively connected to the processing unit and is used to output an error clock frequency when the clock signal is a non-integer clock frequency. The processing unit is also used to write a feedback clock frequency to the frequency register and a feedback clock phase to the clock register according to the error clock frequency. The clock generation unit is also used to generate a clock signal with a feedback clock frequency and a feedback clock phase according to the frequency adjustment signal and the phase adjustment signal, and send it to the CANFD controller.

[0032] The feedback clock frequency is an integer clock frequency close to the clock frequency of the clock signal, the feedback clock phase is the clock phase of this integer clock, and the error clock frequency is the frequency difference between the clock frequency of the clock signal and the feedback clock frequency. Optionally, the CANFD communication device provided in this application embodiment also includes a feedback mechanism, thereby correcting the CANFD clock signal to an integer when it is a decimal, further improving the design flexibility of the CANFD clock signal.

[0033] In some embodiments, the clock signal in the CANFD communication device provided in this application includes the clock of the data field in the CANFD data frame. Optionally, a CANFD data frame typically includes a Start of Frame (SOF), an Arbitration Field, a Control Field, a Data Field, a CRC Field, an Acknowledge Slot, and an End of Frame (EOF). While all parts of the CANFD data frame participate in the transmission process, it should be noted that the data field is the primary area for information transmission, requiring a precise and stable clock signal to ensure correct data transmission and reception. In contrast, the Start of Frame primarily identifies the beginning of the data frame, the Arbitration Field handles arbitration between nodes, the Control Field transmits control information, the CRC Field performs error checking, the Acknowledge Slot transmits confirmation information, and the End of Frame marks the termination of the data frame. The data field is the core of data transmission, carrying the actual data content to be transmitted in the network, and has a decisive impact on the performance and efficiency of data transmission. Therefore, equipping the data domain with a dedicated clock signal is to ensure that a large amount of data in the data domain can be transmitted at the appropriate timing to meet the system performance requirements, thereby ensuring the efficiency and reliability of data transmission and ensuring the normal operation of the entire CANFD communication device.

[0034] In some embodiments, the CANFD communication device provided in this application includes a clock signal for the data field and a clock signal for the arbitration field in the CANFD data frame. Optionally, the arbitration field is mainly used to resolve the competition problem when different nodes initiate communication simultaneously, determining which node can use the bus for communication first through a specific arbitration mechanism. In this process, the clock signal of the arbitration field plays a decisive role, ensuring that each node can operate within a unified time scale during arbitration, allowing the arbitration process to proceed in an orderly manner. Under the synchronization of the arbitration field clock, the arbitration signals of different nodes determine their priorities according to predetermined rules and signal levels to avoid communication conflicts and ensure the orderly operation of the entire CANFD communication device. Therefore, providing the clock signal simultaneously to the data field and the arbitration field helps ensure that information transmission and processing in these two important areas can be carried out within an orderly time frame, thereby ensuring the efficient, stable, and reliable operation of the entire CANFD communication device.

[0035] In some embodiments, Figure 3 This application provides another schematic diagram of a CANFD communication device module, as shown in the embodiment. Figure 3 As shown in the embodiment of this application, the CANFD communication device further includes a clock reset unit in the programmable logic module. This clock reset unit provides a preset operating clock for the conversion unit and the clock generation unit, and controls the reset of the conversion unit and the clock generation unit. Optionally, this operating clock is fundamental to the normal operation of the conversion unit and the clock generation unit, ensuring that they can operate at appropriate timing. The clock reset unit can also reset the conversion unit and the clock generation unit. When abnormal conditions occur in the system, such as data transmission errors, timing discrepancies, or module failures, the clock reset unit's reset function can reinitialize the conversion unit and the clock generation unit, ensuring the normal operation of the system and guaranteeing that the system can recover to a stable and reliable operating state under various complex working environments and possible abnormal conditions.

[0036] In some embodiments, the CANFD communication device provided in this application includes a processor module including a CPU, a programmable logic module including an FPGA (Field Programmable Gate Array), and a conversion unit and a clock generation unit, which are two functional modules within the FPGA.

[0037] In one implementation, the conversion unit and the clock generation unit are two functional modules within the FPGA, and they are soft-core IPs (Intellectual Property Cores) within the FPGA.

[0038] In one implementation, the conversion unit and the clock generation unit are two functional modules within the FPGA, and they are hard-core IPs within the FPGA.

[0039] In some embodiments, the processor module in the CANFD communication device provided in this application can also be configured as a processor such as an MCU (Microcontroller Unit) or a DSP (Digital Signal Processor).

[0040] In some embodiments, the programmable logic module in the CANFD communication device provided in this application can also be configured as a programmable logic device such as SOPC (System on a Programmable Chip) or CPLD (Complex Programmable Logic Device).

[0041] In some embodiments, in the CANFD communication device provided in this application, the processor module and the programmable logic module are connected via an AXI LITE bus to achieve signal transmission.

[0042] The following examples illustrate the CANFD communication device provided in this application, which is applied in the field of CANFD interface technology for chips.

[0043] Optionally, when the CANFD communication device is working, the processing unit first writes a preset clock frequency to the frequency register and a preset clock phase to the phase register, and then outputs the values ​​of the frequency register and the phase register to the conversion unit. Next, the conversion unit receives the value of the frequency register and converts it into a frequency adjustment signal, and receives the value of the phase register and converts it into a phase adjustment signal. Then, the clock generation unit generates a clock signal with a preset clock frequency and a preset clock phase based on the frequency adjustment signal and the phase adjustment signal, and sends it to the CANFD controller. Finally, the CANFD controller communicates with each node according to the clock signal, thereby providing clock signals to each node of the CANFD controller. After receiving the clock signal, the CANFD controller determines whether the clock signal is an integer clock frequency. If the clock signal is a non-integer clock frequency, it outputs an error clock frequency. The processing unit then writes the feedback clock frequency and the feedback clock phase to the frequency register based on the error clock frequency. It also outputs the values ​​of the frequency register and the phase register to the conversion unit. The conversion unit receives the value of the frequency register and converts it into a frequency adjustment signal, and receives the value of the phase register and converts it into a phase adjustment signal. The clock generation unit then regenerates a clock signal with the feedback clock frequency and feedback clock phase based on the frequency adjustment signal and the phase adjustment signal, and sends it to the CANFD controller, enabling the CANFD controller to communicate with each node according to the adjusted clock signal.

[0044] This application also provides a CANFD communication system, which includes the CANFD communication device described above and at least one CANFD node, wherein the at least one CANFD node is connected to the CANFD controller via a CANFD bus.

[0045] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A CANFD communication device, characterized in that, Includes processor modules and programmable logic modules; The processor module includes a processing unit, a frequency register, a phase register, and a CANFD controller. The processing unit is communicatively connected to the phase register, the frequency register, and the programmable logic module, respectively, to write a preset clock frequency to the frequency register, write a preset clock phase to the clock register, and output the values ​​of the frequency register and the phase register to the programmable logic module. The programmable logic module includes a conversion unit and a clock generation unit. The conversion unit is communicatively connected to the processor module and the clock generation unit respectively, to receive the value of the frequency register and convert it into a frequency adjustment signal, and to receive the value of the phase register and convert it into a phase adjustment signal; The clock generation unit is also communicatively connected to the CANFD controller to generate a clock signal with a preset clock frequency and a preset clock phase according to the frequency adjustment signal and the phase adjustment signal, and send it to the CANFD controller for communication between the CANFD controller and at least one CANFD node.

2. The CANFD communication device as described in claim 1, characterized in that, The CANFD controller is also communicatively connected to the processing unit to output an error clock frequency when the clock signal is a non-integer clock frequency; The processing unit is used to write a feedback clock frequency to the frequency register according to the error clock frequency, and to write a feedback clock phase to the clock register; The clock generation unit is used to generate a clock signal having the feedback clock frequency and the feedback clock phase according to the frequency adjustment signal and the phase adjustment signal, and send it to the CANFD controller; Wherein, the feedback clock frequency is the clock frequency of an integer clock that is close to the clock frequency of the clock signal, the feedback clock phase is the clock phase of the integer clock, and the error clock frequency is the frequency difference between the clock frequency of the clock signal and the feedback clock frequency.

3. The CANFD communication device as described in claim 1, characterized in that, The clock signal includes the clock of the data field in the CANFD data frame.

4. The CANFD communication device as described in claim 1, characterized in that, The clock signal includes the clock of the data field and the clock of the arbitration field in the CANFD data frame.

5. The CANFD communication device as described in claim 1, characterized in that, The programmable logic module further includes: A clock reset unit is communicatively connected to both the conversion unit and the clock generation unit to provide a preset operating clock for the conversion unit and the clock generation unit, and to control the reset of the conversion unit and the clock generation unit.

6. The CANFD communication device as described in claim 1, characterized in that, The processor module includes a CPU, the programmable logic module includes an FPGA, and the conversion unit and the clock generation unit are two functional modules within the FPGA.

7. The CANFD communication device as described in claim 1, characterized in that, The processor module and the programmable logic module are connected via an AXI LITE bus.

8. A CANFD communication system, characterized in that, It includes the CANFD communication device according to any one of claims 1 to 7 and at least one CANFD node, wherein the at least one CANFD node is connected to the CANFD controller via a CANFD bus.

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