IO interface expansion control circuit

Abstract

The utility model discloses an IO (Input / Output) interface expansion control circuit, which belongs to the field of integrated circuit input / output interface expansion and comprises two groups of serial bus communication control units, two groups of interface expansion output units and an OR logic output unit, the serial bus communication control unit is provided with a chip selection signal interface, a first serial clock interface, a response signal feedback interface, a first serial data input interface, a serial data output interface, a write pulse output interface, a read pulse output interface and a first power supply interface; the interface expansion output unit is provided with a second serial data input interface, a second serial clock interface, a third serial clock interface, parallel data output interfaces, a first interrupt feedback interface, an enabling interface and a second power interface; and the OR logic output unit performs OR logic processing on data of the two groups of parallel data output interfaces. According to the utility model, through cooperation of the two groups of serial bus communication control units, the two groups of interface expansion output units and the logic output unit, a cold backup function is realized.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit input / output interface expansion technology, and in particular, to an IO interface expansion control circuit. Background Technology

[0002] The I / O interface of an integrated circuit (such as a CPU, MCU, DSP, FPGA, etc.) is a bridge for information transmission between it and peripherals or other information processing units. These I / O interfaces can use serial or parallel communication protocols for data transmission.

[0003] With the development of technology, integrated circuits need to connect to more and more external devices or communicate with other information processing units, such as sensors, actuators, and storage devices. However, the number of I / O interfaces on a single integrated circuit is limited and cannot meet the needs of a large number of external connections. Therefore, it is often necessary to expand the I / O interfaces. A common expansion method is to use serial interface expansion chips for parallel expansion, such as expanding to 8, 16, or 32 I / O channels.

[0004] However, when the serial interface expansion chip itself fails, the expansion function will be lost, making it unusable in some scenarios with high reliability requirements. Utility Model Content

[0005] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes an I / O interface expansion control circuit, designed to achieve cold backup of the expanded I / O interface to adapt to different circuit failure scenarios.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0007] An I / O interface expansion control circuit includes two sets of serial bus communication control units and two sets of interface expansion output units or logic output units. The serial bus communication control units are provided with a chip select signal interface, a first serial clock interface, an acknowledge signal feedback interface, a first serial data input interface, a serial data output interface, a write pulse output interface, a read pulse output interface, and a first power interface. The chip select signal interface, the first serial clock interface, the acknowledge signal feedback interface, and the first serial data input interface are used to connect to the corresponding I / O interface of the control chip. The interface expansion output units are provided with a second serial data input interface, a second serial clock interface, a third serial clock interface, a parallel data output interface, a first interrupt feedback interface, an enable interface, and a second power interface. The second serial data input interface is connected to the serial data output interface. The second serial clock interface is connected to the write pulse output interface, and the third serial clock interface is connected to the read pulse output interface. The first interrupt feedback interface and the enable interface are used to connect to the corresponding I / O interface of the control chip. The OR logic output unit is used to perform OR logic processing on the data of the two sets of parallel data output interfaces and output them in parallel. The first power interface and the second power interface are both used to connect to the first power supply. When the acknowledgment signal feedback interface does not generate an acknowledgment signal and the enable interface is in a disabled state, the parallel data output interface is set to zero. When the data of one set of the second serial data input interfaces is not equal to the data of the parallel data output interface, the corresponding first interrupt feedback interface triggers an interrupt feedback signal, and the control chip does not send an enable signal to the corresponding enable interface according to the interrupt feedback signal.

[0008] Furthermore, the interface expansion output unit includes a multi-bit shift register, a multi-bit latch register, and a comparator module. The input of the shift register is connected to the serial data output interface, and the clock of the shift register is connected to the write pulse output interface. The latch register has the same number of bits as the shift register, and its input is connected to the output of the shift register. The clock of the latch register is connected to the read pulse output interface. The enable interface is connected in series with the output of the latch register. The input of the comparator module is connected to the outputs of the shift register and the latch register, respectively. When at least one bit of data in the outputs of the shift register and the latch register is not equal, the comparator module outputs an interrupt feedback signal, and the control chip disables the enable interface based on the interrupt feedback signal.

[0009] Furthermore, the comparator module includes multiple one-bit comparators and an OR gate module. The number of one-bit comparators is the same as the number of bits in the shift register. Each one-bit comparator has two input terminals and one output terminal. The OR gate module has the same number of input terminals and one output terminal as the one-bit comparator. The output terminal of the one-bit comparator is used to connect to the corresponding I / O interface of the control chip, and the output terminal of the one-bit comparator is connected to the input terminal of the OR gate module. When the logic values ​​of the two input terminals of the one-bit comparator are the same, its output terminal outputs a logic value of zero; when the logic values ​​of the two input terminals of the one-bit comparator are different, its output terminal outputs a logic value of one.

[0010] Furthermore, the one-bit comparator includes an XOR gate module and an inverter. The XOR gate module has two input ports and one output port. The input port of the inverter is connected to the output port of the XOR gate module, and the output port of the inverter is connected to the input of the OR gate module.

[0011] Furthermore, the IO interface expansion control circuit also includes an optocoupler isolation unit. The input terminal of the optocoupler isolation unit is connected to the IO interface corresponding to the control chip, and the output terminal of the optocoupler isolation unit is connected to the first serial data input interface.

[0012] Furthermore, the optocoupler isolation unit includes a switching current module and an optocoupler. The input terminal of the switching current module is connected to the IO interface corresponding to the control chip, the input terminal of the optocoupler is connected to the output terminal of the switching current module, and the output terminal of the optocoupler is connected to the first serial data input interface.

[0013] Furthermore, the switching current module includes an NPN transistor, a diode, a first current-limiting resistor, a second current-limiting resistor, and a bias resistor. The collector of the NPN transistor is connected to the emitter of the photodetector of the optocoupler. The collector of the photodetector of the optocoupler is used to connect to a second power supply. The emitter of the NPN transistor is grounded. The diode is connected in series between the base of the NPN transistor and the corresponding IO interface of the control chip. The first current-limiting resistor is connected in series between the base of the NPN transistor and the diode. The second current-limiting resistor is connected in series between the collector of the photodetector of the optocoupler and the first power supply. The bias resistor is connected in series between the base of the NPN transistor and ground.

[0014] Furthermore, a second inverter with an enable terminal is provided between the input terminal of one group of the optocoupler isolation units and the IO interface corresponding to the control chip, and the enable terminal of the second inverter is connected to the IO interface corresponding to the control chip.

[0015] Furthermore, an overcurrent protection unit is connected in series between the first power supply and both the first power interface and the second power interface.

[0016] Furthermore, the overcurrent protection unit includes a fusible fuse.

[0017] This invention has the following advantages: By cooperating with two sets of serial bus communication control units, two sets of interface expansion output units, or logic output units, serial-to-parallel port expansion is achieved through serial bus communication, increasing the number of I / O interfaces of the control chip. At the same time, the OR logic output unit performs OR logic processing on the data of the two sets of parallel data output interfaces. When a circuit combination of one set of serial bus communication control units, interface expansion output units, or logic output units fails, such as synchronous serial communication failure, constant low output status, or constant high output status, a cold switch can be made to another circuit combination of serial bus communication control units, interface expansion output units, and OR logic output units, thereby improving the reliability of the entire control circuit.

[0018] In addition to the objectives, features, and advantages described above, this utility model has other objectives, features, and advantages. The present utility model will now be described in further detail with reference to the figures. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an undue limitation of the present invention. In the drawings:

[0020] Figure 1 This is a circuit diagram of the IO interface expansion control circuit in one embodiment of the present invention;

[0021] Figure 2 This is a circuit diagram of the interface expansion output unit in one embodiment of the present invention;

[0022] Figure 3 This is a circuit diagram of the interface expansion output unit in another embodiment of the present invention;

[0023] Figure 4 This is a circuit diagram of a comparator module in one embodiment of the present invention.

[0024] Figure 5 This is a circuit diagram of the optocoupler isolation unit in one embodiment of the present invention. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0027] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0028] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0029] refer to Figures 1 to 5 This is an IO interface expansion control circuit according to an embodiment of the present utility model, including two sets of serial bus communication control units U1, two sets of interface expansion output units U2, or logic output units U3.

[0030] Specifically, each serial bus communication control unit U1 is equipped with a chip select signal interface CS, a first serial clock interface CLK1, an acknowledge signal feedback interface RES, a first serial data input interface SI1, a serial data output interface SO, a write pulse output interface WPO, a read pulse output interface RPO, and a first power supply interface VCC1.

[0031] During circuit connection, the first power interface VCC1 is connected to an external DC power supply. The voltage of the DC power supply is set according to the actual situation, such as 3.3V, 5V, 12V, or 5V. Alternatively, the DC power supply can be obtained through AC conversion, for example, using an AC-DC converter chip. The chip select signal interface CS is connected to the corresponding GPIO port of the control chip. It determines the communication address of the serial bus communication control unit U1 by outputting the corresponding level, preparing for subsequent synchronous serial communication. The control chip sends a synchronous clock signal to the first serial clock interface CLK to input data bit by bit to the first serial data input interface SI. In the event of synchronous serial communication failure, the acknowledgment signal feedback interface RES cannot send an acknowledgment signal to the corresponding GPIO port of the control chip. Since the control chip does not detect the corresponding acknowledgment signal, it determines that the synchronous serial communication has failed. It should be noted that the control chip can be a CPU, MCU, DSP, FPGA, or other control chips.

[0032] Each set of interface expansion output units U2 is equipped with a second serial data input interface SI2, a second serial clock interface CLK2, a third serial clock interface CLK3, a parallel data output interface Q1 (Q1-1, Q1-2, ...), a first interrupt feedback interface INT, an enable interface EN, and a second power supply interface VCC2.

[0033] During circuit connection, the second power interface VCC2 is connected to an external DC power supply. The voltage of the DC power supply is set according to the actual situation, such as 3.3V, 5V, 12V, or 5V. Alternatively, the DC power supply can be obtained through AC conversion, for example, using an AC-DC converter chip. The second serial data input interface SI2 is connected to the serial data output interface SO, the second serial clock interface CLK2 is connected to the write pulse output interface WPO, and the third serial clock interface CLK3 is connected to the read pulse output interface RPO. Under the action of the synchronous clock signal sent by the write pulse output interface WPO, the input data received by the first serial data input interface SI is input bit by bit from the second serial data input interface SI2. Then, under the action of the synchronous clock signal sent by the read pulse output interface RPO, the interface expansion output unit U2 obtains the complete multi-bit data output by the control chip. This multi-bit data is then synchronously output to the load through the parallel data output interface Q1, such as synchronous output to an LED matrix or an LCD screen.

[0034] In the currently operating interface expansion output unit U2, if the data of the second serial data input interface SI2 is not equal to that of the parallel data output interface Q1, the currently operating interface expansion output unit U2 triggers an interrupt feedback signal to the control chip through the first interrupt feedback interface INT. After receiving the interrupt feedback signal, the control chip does not send an enable signal to the enable interface EN. At this time, the enable interface EN is in a disabled state, and the parallel data output interface Q1 is set to zero.

[0035] Furthermore, in this embodiment, when the control chip does not detect the corresponding response signal, it does not send an enable signal to the enable interface EN. At this time, the enable interface EN is in a disabled state, and the parallel data output interface Q1 is set to zero. Simultaneously, when the first power interface VCC1 fails, the synchronous serial communication between the control chip and the serial bus communication control unit U1 also fails. At this time, the enable interface EN is disabled, and the parallel data output interface Q1 is set to zero. When the second power interface VCC2 fails, the interface expansion output unit U2 is de-energized and cannot function properly. In this case, another combination of the serial bus communication control unit U1, the interface expansion output unit U2, and / or the logic output unit U3 can be used for data transmission. To prevent the parallel data output interface Q1 of the failed interface expansion output unit U2 from being in an uncertain level state, a switchable device, such as a transistor, can be installed at the interface expansion output unit U2. Through a transistor whose collector is connected to the power supply and whose emitter is connected to ground, the output level of the interface expansion output unit U2 is zero when the transistor is turned on.

[0036] In some alternative embodiments, such as Figure 2 As shown, the interface expansion output unit U2 includes a multi-bit shift register U21, a multi-bit latch register U22, and a comparator module U23. Specifically, the shift register U21 includes multiple cascaded D flip-flops U211. The number of D flip-flops U211 is consistent with the number of bits in the parallel data output interface Q1. The input of the first D flip-flop U211 is connected to the serial data output interface SO. The clock terminals of all D flip-flops U211 are connected to the write pulse output interface WPO. Optionally, the D flip-flops U211 can be either rising-edge triggered or falling-edge triggered. In addition, for easy reset, D flip-flops with reset functionality can also be selected.

[0037] For example, taking a rising edge triggered D flip-flop as an example, during operation, the write pulse output interface WPO outputs a clock signal, and at the rising edge of the clock, each D flip-flop U211 latches the corresponding bit in the data input to the serial data output interface SO.

[0038] The latch register U22 also includes multiple D flip-flops U221. The number of D flip-flops U221 is consistent with the number of bits in the parallel data output interface Q1. The input of each D flip-flop U221 is connected to the output of each D flip-flop U211. The clock terminals of all D flip-flops U221 are connected to the read pulse output interface RPO. Optionally, the D flip-flops U221 can be either rising-edge triggered or falling-edge triggered. In addition, for easy reset, D flip-flops with reset function can be selected.

[0039] For example, taking a rising edge triggered D flip-flop as an example, when each D flip-flop U221 latches the complete data input to the serial data output interface SO, the read pulse output interface RPO starts to output a clock signal. At the rising edge of the clock, each D flip-flop U221 latches the complete data input to the serial data output interface SO.

[0040] In addition, to enable the function, each D flip-flop U212 has an enable interface EN connected in series at its output. Optionally, the enable interface EN can be an inverter Y0 with an enable terminal. When the enable terminal of inverter Y0 is valid, inverter Y0 works normally and inverts the input signal. When the enable terminal of inverter Y0 is invalid, the output terminal of inverter Y0 is set to a fixed level of zero.

[0041] The input terminals of comparator module U23 are connected to the output terminals of D flip-flops U211 and U221, respectively, and the output terminal of comparator module U23 is connected to the interrupt interface of the control chip. During operation, when the output value of any D flip-flop U211 is not equal to the output value of the corresponding D flip-flop U221, comparator module U23 outputs an interrupt feedback signal. Upon receiving the interrupt feedback signal, the control chip disables the enable interface EN, thereby setting the output terminal of inverter Y0 to a fixed level of zero. At this time, data can be transmitted using a combination of another set of serial bus communication control unit U1, interface expansion output unit U2, and / or logic output unit U3, achieving a cold backup function.

[0042] In some alternative embodiments, such as Figure 3As shown, the comparator module U23 includes multiple one-bit comparators U231 and an OR gate module U232. Specifically, the number of one-bit comparators U231 is consistent with the number of bits in the parallel data output interface Q1. Each one-bit comparator U231 has two inputs and one output. The OR gate module U232 has the same number of inputs and one output as the one-bit comparator. In circuit connection, the two inputs of each one-bit comparator U231 are connected to the outputs of a corresponding D flip-flop U211 and a corresponding D flip-flop U221, respectively. The output of each one-bit comparator U231 is connected to one input of the corresponding OR gate module. During operation, when the logic values ​​of the two inputs of a one-bit comparator U231 are the same, its output Y2 outputs a logic value of one; when the logic values ​​of the two inputs of a one-bit comparator U231 are different, its output Y2 outputs a logic value of zero. At this time, the output of the OR gate module U232 triggers the interrupt function of the control chip.

[0043] Optionally, in order to prevent the comparator module U23 or the interface expansion output unit U2 from being in an uncertain level state when the power is off, the one-bit comparator U231 can be selected as a one-bit comparator with an enable terminal. When the enable terminal of the one-bit comparator is valid, the one-bit comparator works normally. When the enable terminal of the one-bit comparator is invalid, the output terminal of the one-bit comparator is set to a fixed level of zero.

[0044] In some alternative embodiments, such as Figure 4 As shown, a one-bit comparator U231 includes an XOR gate module U2311 and an inverter U2312. The XOR gate module U2311 has two input ports and one output port. The input port of the inverter U2312 is connected to the output port of the XOR gate module U2311, and the output port of the inverter U2312 is connected to the input of the OR gate module U232. During operation, when the logic values ​​of the two inputs of the XOR gate module U2311 are the same, its output is a logic value of zero, which is inverted by the inverter U2312 to become a logic value of one. Similarly, when the logic values ​​of the two inputs of the XOR gate module U2311 are different, its output is a logic value of one, which is inverted by the inverter U2312 to become a logic value of zero. This triggers an interrupt in the control chip.

[0045] In some alternative embodiments, such as Figure 1 and Figure 5 As shown, the IO interface expansion control circuit also includes an optocoupler isolation unit U4. The input terminal of the optocoupler isolation unit U4 is connected to the corresponding IO interface of the control chip, and the output terminal of the optocoupler isolation unit U4 is connected to the first serial data input SI interface. During operation, when the corresponding IO interface of the control chip outputs a high or low level, the output terminal of the optocoupler isolation unit U4 also synchronously outputs the corresponding high or low level.

[0046] In some alternative embodiments, such as Figure 5 As shown, the optocoupler isolation unit U4 includes a switching current module U41 and an optocoupler U42. Specifically, the four interfaces of the optocoupler U4 are pin 1 (LED anode), pin 2 (LED cathode), pin 3 (collector of the photodetector), and pin 4 (emitter of the photodetector). In circuit connection, pin 1 of the optocoupler isolation unit U4 is connected to the power supply, for example, a 15V power supply; pin 3 of the optocoupler isolation unit U4 is connected to the power supply, for example, a 5V power supply; and pin 4 of the optocoupler isolation unit U4 is connected to the first serial data input interface SI1.

[0047] In this embodiment, by incorporating an optocoupler U42, which is a current-driven, low-impedance component with strong common-mode rejection capability, the optocoupler U42 acts as a terminal isolation element in signal transmission, significantly improving the signal-to-noise ratio and reliability of the electronic system. Specifically, in this circuit, since there is no direct electrical relationship between the control chip and the serial bus communication control unit U1, their radio frequency radiation or conducted radiation cannot interfere with each other, thus achieving anti-interference and improving the reliability of the IO interface expansion control circuit.

[0048] In some optional embodiments, to avoid damage to the control chip's corresponding I / O interface due to excessive current flow, such as... Figure 5 As shown, the switching current module U41 includes an NPN transistor U411, a diode U412, a first current-limiting resistor U413, a second current-limiting resistor U414, and a bias resistor U415. In circuit connection, the collector of the NPN transistor U411 is connected to the emitter of the photodetector of the optocoupler U42. The collector of the photodetector of the optocoupler U42 is connected to the power supply. The emitter of the NPN transistor U411 is grounded. The diode U412 is connected in series between the base of the NPN transistor U411 and the corresponding IO interface of the control chip. The first current-limiting resistor U413 is connected in series between the base of the NPN transistor U411 and the diode U412. The second current-limiting resistor U414 is connected in series between the collector of the photodetector of the optocoupler U42 and the power supply. The bias resistor U415 is connected in series between the base of the NPN transistor U411 and ground.

[0049] In this embodiment, when the I / O interface corresponding to the control chip outputs a low level, the NPN transistor U411 is cut off, the LED of the optocoupler U42 does not conduct and does not emit light, and the phototransistor of the optocoupler U42 is not turned on. When the I / O interface corresponding to the control chip outputs a high level, the NPN transistor U411 is turned on, the LED of the optocoupler U42 is turned on and emits light, and the phototransistor of the optocoupler U42 is turned on. Since the base current of the NPN transistor U411 is small, the current flowing through the I / O interface corresponding to the control chip can be well controlled.

[0050] In some optional embodiments, when one set of serial bus communication control unit U1, interface expansion output unit U2, or logic output unit U3 and optocoupler isolation unit U4 are used for data transmission, a second inverter Y1 with an enable terminal (not shown in the figure) is provided between the input terminal of another set of corresponding optocoupler isolation unit U4 and the IO interface corresponding to the control chip. The enable terminal of the second inverter Y1 is connected to the IO interface corresponding to the control chip.

[0051] During operation, when one set of serial bus communication control unit U1, interface expansion output unit U2, or logic output unit U3, and optocoupler isolation unit U4 is transmitting data, the corresponding optocoupler isolation unit U4 needs to be in a non-working state. At this time, the control chip disables the enable pin of the second inverter Y1, and simultaneously sets the output of the second inverter Y1 to zero, thus deactivating the corresponding optocoupler isolation unit U4. Conversely, when backup switching is required, the control chip simply enables the enable pin of the second inverter Y1.

[0052] In some optional embodiments, to prevent damage to electronic components in case of overcurrent, an overcurrent protection unit FU (not shown in the figures) is connected in series between the first power interface VCC1 and the power supply it is connected to. Similarly, an overcurrent protection unit FU (not shown in the figures) is also connected in series between the second power interface VCC2 and the power supply it is connected to. Optionally, the overcurrent protection unit FU includes a fuse. A fuse is a safety device used to protect a circuit from overload and short circuit. It typically consists of a conductor with a suitable melting point. When the current in the circuit exceeds the rated current of the fuse, the conductor melts due to excessive heat, thereby breaking the circuit, preventing further current flow, and protecting other components in the circuit from damage.

[0053] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. An I / O interface expansion control circuit, characterized in that, The I / O interface expansion control circuit includes: Both sets of serial bus communication control units are equipped with a chip select signal interface, a first serial clock interface, an acknowledgment signal feedback interface, a first serial data input interface, a serial data output interface, a write pulse output interface, a read pulse output interface, and a first power interface. The chip select signal interface, the first serial clock interface, the acknowledgment signal feedback interface, and the first serial data input interface are used to connect to the corresponding IO interface of the control chip. Both sets of interface expansion output units are provided with a second serial data input interface, a second serial clock interface, a third serial clock interface, a parallel data output interface, a first interrupt feedback interface, an enable interface, and a second power interface. The second serial data input interface is connected to the serial data output interface, the second serial clock interface is connected to the write pulse output interface, and the third serial clock interface is connected to the read pulse output interface. The first interrupt feedback interface and the enable interface are used to connect to the corresponding IO interface of the control chip. OR logic output unit, used to perform OR logic processing on the data of the two sets of parallel data output interfaces and output them in parallel; Wherein, both the first power interface and the second power interface are used to connect to the first power supply. When the response signal feedback interface does not generate a response signal and the enable interface is in a disabled state, the parallel data output interface is set to zero. When the data of one of the second serial data input interfaces is not equal to that of the parallel data output interface, the corresponding first interrupt feedback interface triggers an interrupt feedback signal, and the control chip does not send an enable signal to the corresponding enable interface according to the interrupt feedback signal.

2. The IO interface expansion control circuit according to claim 1, characterized in that, The interface extension output unit includes: A multi-shift register, wherein the input terminal of the shift register is connected to the serial data output interface, and the clock terminal of the shift register is connected to the write pulse output interface; A multi-bit latch register, with the same number of bits as the shift register, has its input connected to the output of the shift register, and its clock terminal connected to the read pulse output interface. The enable interface is connected in series with the output of the latch register. The comparator module has its input terminals connected to the output terminals of the shift register and the latch register, respectively. Specifically, when at least one bit of data in the output of the shift register and the output of the latch register are not equal, the comparator module outputs the interrupt feedback signal, and the control chip disables the enable interface according to the interrupt feedback signal.

3. The IO interface expansion control circuit according to claim 2, characterized in that, The comparator module includes multiple one-bit comparators and an OR gate module. The number of one-bit comparators is the same as the number of bits in the shift register. Each one-bit comparator has two inputs and one output. Each OR gate module has the same number of inputs and one output as the one-bit comparator. The output of each one-bit comparator is connected to the input of the OR gate module. Specifically, when the logic values ​​of the two input terminals of the one-bit comparator are the same, its output terminal outputs a logic value of one; when the logic values ​​of the two input terminals of the one-bit comparator are different, its output terminal outputs a logic value of zero.

4. The IO interface expansion control circuit according to claim 3, characterized in that, The one-bit comparator includes an XOR gate module and a first inverter. The XOR gate module has two input ports and one output port. The input port of the first inverter is connected to the output port of the XOR gate module, and the output port of the first inverter is connected to the input of the OR gate module.

5. The IO interface expansion control circuit according to claim 1, characterized in that, The IO interface expansion control circuit also includes an optocoupler isolation unit. The input terminal of the optocoupler isolation unit is connected to the IO interface corresponding to the control chip, and the output terminal of the optocoupler isolation unit is connected to the first serial data input interface.

6. The IO interface expansion control circuit according to claim 5, characterized in that, The optocoupler isolation unit includes: The input terminal of the switching current module is connected to the corresponding IO interface of the control chip. An optocoupler is used, with its input end connected to the output end of the switching current module and its output end connected to the first serial data input interface.

7. The IO interface expansion control circuit according to claim 6, characterized in that, The switching current module includes: An NPN transistor, wherein the collector of the NPN transistor is connected to the emitter of the photodetector of the optocoupler, the collector of the photodetector of the optocoupler is used to connect to a second power supply, and the emitter of the NPN transistor is grounded. A diode is connected in series between the base of the NPN transistor and the corresponding I / O interface of the control chip; The first current-limiting resistor is connected in series between the base of the NPN transistor and the diode; The second current-limiting resistor is connected in series between the collector of the photodetector of the optocoupler and the first power supply; A bias resistor is connected in series between the base of the NPN transistor and ground.

8. The I / O interface expansion control circuit according to any one of claims 5 to 7, characterized in that, One of the sets of optical coupler isolation units has a second inverter with an enable terminal between its input terminal and the corresponding IO interface of the control chip. The enable terminal of the second inverter is connected to the corresponding IO interface of the control chip.

9. The IO interface expansion control circuit according to claim 1, characterized in that, An overcurrent protection unit is connected in series between the first power supply and both the first power interface and the second power interface.

10. The IO interface expansion control circuit according to claim 9, characterized in that, The overcurrent protection unit includes a fused fuse.

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