Programmable SiP-level chip

Abstract

The utility model discloses a programmable SiP-level chip, and relates to the technical field of integrated circuits. The device comprises an FPGA (Field Programmable Gate Array) A1, an FPGA A2, FLASH memories respectively corresponding to two FPGA chips, two CAN (Controller Area Network) transceivers and related decoupling capacitors, and adopts a ceramic packaging form as a BGA (Ball Grid Array); jTAG signals between the two FPGA chips are connected through a daisy chain, the two FPGA chips are connected through 11 paths of interconnected FIFO and a pair of MRCC differential lines, and each path is composed of 14 1.8 V level GPIO pins; the FPGA (Field Programmable Gate Array) A1 chip is connected to a 29L256NOR FLASH1 chip through a parallel interface, the FPGA A2 chip is connected to a JXCF128X serial FLASH2 chip through an SPI (Serial Peripheral Interface), and the FPGA A2 chip is also connected with two paths of CAN (Controller Area Network) transceiver chips.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and in particular relates to a programmable SiP-level chip. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are widely used in existing electronic system designs. However, the configuration files for these FPGAs are typically stored in external FLASH chips. This practice presents significant security risks: on the one hand, the configuration files are easily copied or tampered with; on the other hand, once all components on the circuit board (including the FPGA and its external FLASH) are copied as a whole, the entire design can be easily counterfeited.

[0003] Traditional FPGA chips often have a large package size, which is a significant drawback for products that require miniaturization and lightweight design. In addition, a large package may reduce the reliability and durability of the system, as they are more susceptible to physical damage or environmental factors. When using multiple independent FPGAs and other components, designers must deal with complex wiring and interconnection issues, increasing design difficulty and time costs. At the same time, compatibility and interface matching issues between different components may lead to additional debugging work, further extending the product launch cycle. For rapidly changing market demands and technological advancements, a long development cycle is clearly detrimental.

[0004] To address these issues, we provide a programmable SiP-level chip. Utility Model Content

[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0006] This utility model is a programmable SiP-level chip, including FPGA1 and FPGA2, FLASH memory corresponding to the two FPGA chips respectively, two CAN transceivers and related decoupling capacitors, and adopts ceramic packaging form as BGA ball grid array.

[0007] The JTAG signal between the two FPGA chips is daisy-chained, and the two FPGA chips are connected by an 11-way interconnected FIFO and a pair of MRCC differential lines, each consisting of 14 1.8V level GPIO pins.

[0008] The present invention is further configured such that the FPGA1 chip is connected to a 29L256 NORFLASH1 chip through a parallel interface, the FPGA2 chip is connected to a JXCF128X serial FLASH2 chip through an SPI interface, and the FPGA2 chip is also connected to two CAN transceiver chips.

[0009] The present invention is further configured such that the FPGA1 chip has 170 GPIO pins with a 3.3V level, and is equipped with 16 pairs of GTX high-speed differential signal pins and corresponding reference clock pins, which are suitable for high-speed serial communication protocols such as PCIe and SATA.

[0010] The present invention is further configured such that the FPGA2 chip has 10 serial ports, each using 3.3V VTTL level, and is also equipped with 16 3.3V LVCMOS GPIO interfaces and 4 sets of SERDES high-speed signals, each set containing multiple high-speed differential signal lines.

[0011] The present invention is further configured such that both the FPGA1 chip and the FPGA2 chip include an XADC analog input and a PROGRAM_B reset signal.

[0012] The present invention is further configured such that the FPGA1 chip and the FPGA2 chip are flip-chip soldered on the internal substrate, and the remaining chips are bonded to the PADs on the substrate by wire bonding.

[0013] The present invention is further configured such that the FPGA1 chip is a 7K325T die and the FPGA2 chip is a K50 die.

[0014] This utility model has the following beneficial effects:

[0015] 1. This utility model improves the system integration by integrating two FPGA chips, corresponding FLASH memory, CAN transceiver and other necessary components into one SiP, which not only reduces the size and weight of the entire module, but also reduces the required PCB area.

[0016] 2. This utility model reduces the number of external components, simplifies circuit design, and lowers bill of materials costs by integrating multiple functional modules into a single SiP. In addition, the reduced wiring and interconnection requirements also reduce manufacturing complexity and error rates in the production process, thereby reducing the total cost. This not only helps control R&D and production costs but also improves the market competitiveness of the product.

[0017] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a diagram showing the internal connection relationships of the SiP in this utility model.

[0020] Figure 2 This is a schematic diagram of the electrical connection of the SiP in this utility model. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0022] Example

[0023] Please see Figure 1 and Figure 2 This utility model is a programmable SiP-level chip, including FPGA1 and FPGA2, FLASH memory corresponding to the two FPGA chips respectively, two CAN transceivers and related decoupling capacitors, and adopts ceramic packaging form as BGA ball grid array.

[0024] The JTAG signal between the two FPGA chips is daisy-chained, and the two FPGA chips are connected by an 11-way interconnected FIFO and a pair of MRCC differential lines, each consisting of 14 1.8V level GPIO pins.

[0025] FPGA1 uses a 7K325T die, which is an FPGA chip with large logic resources and rich I / O features, suitable for complex logic processing tasks; FPGA2 uses a K50 die, which, compared to FPGA1, may be more suitable for specific applications or smaller-scale logic implementations.

[0026] To achieve efficient data exchange between the two FPGAs, an 11-channel FIFO interconnect is used. Each FIFO link consists of 14 GPIO pins at 1.8V level, and these signal lines are responsible for high-speed data transmission. A pair of MRCC differential lines are used for MRCC signals to support clock synchronization requirements at different rates. Furthermore, the JTAG interfaces of the two FPGAs are connected in a daisy chain, which simplifies the debugging process and exposes the JTAG signal lines to facilitate external programming and diagnostics.

[0027] FLASH1 uses a 29L256 configuration chip and is connected to FPGA1 via a parallel interface to provide non-volatile memory support for FPGA1; FLASH2 uses a JXCF128X configuration chip and is connected to FPGA2, also serving as a memory configuration.

[0028] FPGA1 provides a variety of interfaces, including but not limited to: 170 3.3V GPIO pins for general input / output operations; 16 pairs of GTX high-speed serial transceiver pins and their reference clock pins for high-speed applications such as fiber optic communication; 10 pairs of 1.8V LVDS pins (40 in total) to support low-voltage differential signal transmission; and XADC analog-to-digital converter signals and PROGRAM_B signals for internal monitoring and reconfiguration.

[0029] FPGA2 focuses on communication functions, specifically: it connects to two GLb3053-3 isolated CAN controllers, providing two isolated CAN interfaces to enhance the system's anti-interference capability; it exposes 10 serial ports, totaling 20 3.3V TTL level pins, facilitating serial communication with other devices; it has 16 3.3V LVCMOS GPIO interfaces, increasing general-purpose input / output capabilities; and it includes four sets of SerDes high-speed signals, as well as XADC and PROGRAM_B signals, further expanding its communication and control functions.

[0030] In addition, all power and ground pins of the chips are directly brought out to the outside, ensuring good electrical contact; decoupling capacitors are added to all internal power pins near power and ground, which effectively reduces noise interference and improves system stability.

[0031] All internal chip interconnects are electrically connected via ceramic or organic substrates, ensuring signal integrity and reliability; the FPGA chip is flip-chip bonded (FC) onto the internal substrate, while other chips are connected to the substrate's PADs via wire bonding (WB), achieving a compact and efficient layout; all SiP traces are located on the bottom surface of the substrate and are led out via BGA solder balls, which not only simplifies the assembly process but also improves the product's durability.

[0032] In summary, this programmable SiP chip integrates multiple key components to form a powerful and high-performance system-level solution suitable for various application scenarios requiring high efficiency and flexibility.

[0033] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0034] The preferred embodiments of this utility model disclosed above are merely illustrative of the present utility model. These preferred embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A programmable SiP-level chip, characterized in that, It includes FPGA1 and FPGA2, FLASH memory corresponding to the two FPGA chips respectively, two CAN transceivers and related decoupling capacitors, and adopts a ceramic package form as a BGA ball grid array; The JTAG signal between the two FPGA chips is daisy-chained, and the two FPGA chips are connected by an 11-way interconnected FIFO and a pair of MRCC differential lines, each consisting of 14 1.8V level GPIO pins.

2. The programmable SiP-level chip according to claim 1, characterized in that, The FPGA1 chip is connected to a 29L256 NOR FLASH1 chip via a parallel interface, and the FPGA2 chip is connected to a JXCF128X serial FLASH2 chip via an SPI interface. The FPGA2 chip is also connected to two CAN transceiver chips.

3. A programmable SiP-level chip according to claim 1, characterized in that, The FPGA1 chip has 170 GPIO pins with a 3.3V level, and is equipped with 16 pairs of GTX high-speed differential signal pins and corresponding reference clock pins, which are suitable for high-speed serial communication protocols such as PCIe and SATA.

4. A programmable SiP-level chip according to claim 1, characterized in that, The FPGA2 chip has 10 serial ports, each using 3.3V TTL level, and is also equipped with 16 3.3V LVCMOS GPIO interfaces and 4 sets of SERDES high-speed signals, each containing multiple high-speed differential signal lines.

5. A programmable SiP-level chip according to claim 1, characterized in that, Both the FPGA1 chip and the FPGA2 chip include an XADC analog input and a PROGRAM_B reset signal.

6. A programmable SiP-level chip according to claim 1, characterized in that, The FPGA1 and FPGA2 chips are flip-chip soldered onto the internal substrate, while the remaining chips are bonded to the PADs on the substrate by wire bonding.

7. A programmable SiP-level chip according to claim 1, characterized in that, The FPGA1 chip is a 7K325T die, and the FPGA2 chip is a K50 die.

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