Uboot start control module and control device

Abstract

The utility model discloses a Uboot start control module and a Uboot start control device, the control module comprises a control unit and a switching unit, the control unit outputs a first switching signal or a second switching signal through a first control end according to a success signal or a failure signal output by a state end of a processor; the switching unit is used for switching to a first mode or a second mode according to the first switching signal or the second switching signal, outputting an NOR signal through the output end when the switching unit is in the first mode, and outputting an NAND signal through the output end when the switching unit is in the second mode; the reading end of the processor is connected with the output end, and the processor controls the NOR memory or the NAND memory to start the Uboot through the communication end according to the NOR signal or the NAND signal received by the reading end. According to the Uboot start control module, online updating of the Uboot file of the system can be achieved through the NAND memory, and the system is started by switching to the NOR memory in time when updating fails, so that normal start and work of the system are guaranteed.

Description

Technical Field

[0001] This utility model relates to the field of Uboot boot technology, and in particular to a Uboot boot control module and control device. Background Technology

[0002] When booting an ARM architecture chip, since NOR flash and Nand flash share signal lines, Uboot can only be booted through NOR flash or NAND flash.

[0003] However, when using NOR Flash for U-boot booting, the signal lines are shared by NOR flash and Nand flash, and the signal lines are occupied by NOR flash. Therefore, it is impossible to update the U-boot file online through NAND flash. The U-boot file can only be updated by disassembling the device and using an offline programmer.

[0004] Using NAND Flash for U-Boot booting allows for online system updates via NAND Flash when the U-Boot file needs updating. However, online U-Boot file updates require a network connection. When updating the image file online, the network may suddenly become unavailable, leading to the loss of the U-Boot file during the update process. If online U-Boot file updates via NAND Flash fail, it is impossible to switch to NOR Flash backup for normal system booting. The only solution is to disassemble the hardware and switch to NOR Flash for U-Boot booting for the device to function properly.

[0005] Starting Uboot using either of the above two boot methods cannot simultaneously meet the requirements of updating the Uboot file online and ensuring normal system startup, thus presenting certain shortcomings. Utility Model Content

[0006] The purpose of this invention is to provide a Uboot boot control module and control device that can update the Uboot file online through NAND memory and switch to NOR memory to boot the system in time when the update fails, so as to ensure the normal startup and operation of the system and effectively prevent the system from failing to boot.

[0007] To achieve the above objectives, this utility model discloses a Uboot boot control module for controlling a processor to boot Uboot via NOR memory or NAND memory. The processor includes a status terminal, a read terminal, and a communication terminal. The communication terminal is communicatively connected to the NOR memory and the NAND memory. The control module includes:

[0008] The control unit includes a receiving end and a first control end. The receiving end is connected to the status end. The control unit is used to output a first switching signal or a second switching signal through the first control end according to the success signal or failure signal output by the status end.

[0009] A switching unit is provided with a first mode and a second mode. The switching unit includes a second control terminal and an output terminal. The second control terminal is connected to the first control terminal. The switching unit is used to switch to the first mode or the second mode according to the first switching signal or the second switching signal received by the second control terminal. When the switching unit is in the first mode, it outputs a NOR signal through the output terminal. When the switching unit is in the second mode, it outputs a NAND signal through the output terminal.

[0010] The read terminal is connected to the output terminal, and the processor controls the NOR memory or NAND memory to start Uboot through the communication terminal based on the NOR signal or NAND signal received by the read terminal.

[0011] Optionally, the control unit is equipped with a timer, which is used to calculate the time interval between the receiving end receiving the failure signal and receiving the success signal, and the control unit is used to control the first control end to output the first switching signal or the second switching signal according to the time interval.

[0012] Optionally, the first mode is an external configuration mode, and the switching unit is provided with an external input terminal. When the switching unit is in the first mode, it is used to output a NOR signal through the output terminal according to the external configuration signal received by the external input terminal.

[0013] Optionally, the switching unit includes a first switcher and a second switcher. The first switcher is provided with a plurality of first input pins and a first output pin, and the second switcher is provided with a plurality of second input pins and a second output pin. The first input pins and the second input pins are combined to form the external input terminal, and the first output pins and the second output pins are combined to form the output terminal.

[0014] Optionally, the second mode is an internal memory mode, the switching unit is provided with a register, the register records a stored value, and when the switching unit is in the second mode, it is used to output a NAND signal through the output terminal according to the stored value.

[0015] Optionally, the processor further includes multiple first write pins, and the switching unit includes a first switch and a second switch. The first switch is provided with a first register, and the second switch is provided with a second register. The first switch is provided with multiple second write pins and a first output pin, and the second switch is provided with multiple third write pins and a second output pin. The first write pins are connected to the second write pins and the third write pins, respectively. The processor writes a first stored value and a second stored value to the first register and the second register, respectively, through the second write pins and the third write pins. The first output pin and the second output pin are combined to form the output terminal.

[0016] To achieve the above objectives, this utility model discloses a control device, which includes: the Uboot boot control module as described above, a processor, a NOR memory, and a NAND memory.

[0017] This invention controls the processor to boot U-boot via NOR or NAND memory by setting up a control unit and a switching unit. The processor includes a status terminal, a read terminal, and a communication terminal. The control unit includes a receiver connected to the status terminal and a first control terminal. The switching unit includes a second control terminal connected to the first control terminal and an output terminal connected to the read terminal. The control unit outputs a first switching signal or a second switching signal to the switching unit via the first control terminal based on a success signal or a failure signal output by the status terminal. The switching unit is configured with a first mode and a second mode. The switching unit switches to the first mode or the second mode based on the first switching signal or the second switching signal. When in the first mode, it outputs a NOR signal via the output terminal, and when in the second mode, it outputs a NAND signal via the output terminal. The processor controls the NOR or NAND memory to boot U-boot via the communication terminal based on the NOR or NAND signal received by the read terminal. This enables the system to update the U-boot file online via NAND memory and switches to NOR memory to boot the system in time when the update fails, ensuring normal system startup and operation and effectively preventing system boot failure. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of the Uboot boot control module according to an embodiment of the present invention.

[0019] Figure 2This is a circuit diagram of the processor in the Uboot boot control module of this utility model embodiment.

[0020] Figure 3 This is a circuit diagram of the control unit in the Uboot boot control module of this utility model embodiment.

[0021] Figure 4 This is a circuit diagram of the first and second switches in the Uboot boot control module of this utility model embodiment.

[0022] Figure 5 This is a circuit diagram of the NOR memory in the Uboot boot control module of this utility model embodiment.

[0023] Figure 6 This is a circuit diagram of the NAND memory in the Uboot boot control module of this utility model embodiment. Detailed Implementation

[0024] To explain in detail the technical content, structural features, objectives and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0025] Please see Figures 1 to 6 This utility model discloses a Uboot boot control module for controlling a processor 101 to boot Uboot via a NOR memory 102 or a NAND memory 103. The processor 101 includes a status terminal 1011, a read terminal 1012, and a communication terminal 1013. The communication terminal 1013 is communicatively connected to the NOR memory 102 and the NAND memory 103. The control module includes:

[0026] Control unit 1 includes a receiving terminal 11 and a first control terminal 12. The receiving terminal 11 is connected to the status terminal 1011. The control unit 1 is used to output a first switching signal or a second switching signal through the first control terminal 12 according to the success signal or failure signal output by the status terminal 1011.

[0027] The switching unit 2 is configured with a first mode and a second mode. The switching unit 2 includes a second control terminal 21 and an output terminal 22. The second control terminal 21 is connected to the first control terminal 12. The switching unit 2 is used to switch to the first mode or the second mode according to the first switching signal or the second switching signal received by the second control terminal 21. When the switching unit 2 is in the first mode, it outputs a NOR signal through the output terminal 22. When the switching unit 2 is in the second mode, it outputs a NAND signal through the output terminal 22.

[0028] The read terminal 1012 is connected to the output terminal 22. The processor 101 controls the NOR memory 102 or the NAND memory 103 to start Uboot through the communication terminal 1013 based on the NOR signal or NAND signal received by the read terminal 1012.

[0029] This invention controls a processor 101 to boot U-boot via a NOR memory 102 or a NAND memory 103 by setting a control unit 1 and a switching unit 2. The processor 101 includes a status terminal 1011, a read terminal 1012, and a communication terminal 1013. The control unit 1 includes a receiver 11 connected to the status terminal 1011 and a first control terminal 12. The switching unit 2 includes a second control terminal 21 connected to the first control terminal 12 and an output terminal 22 connected to the read terminal 1012. The control unit 1 outputs a first switching signal or a second switching signal to the switching unit 2 via the first control terminal 12 based on a success signal or a failure signal output from the status terminal 1011. The switching unit 2 is configured with a first mode and a second mode. The switching unit 2 switches to the first mode or the second mode according to the first switching signal or the second switching signal. When in the first mode, it outputs a NOR signal through the output terminal 22, and when in the second mode, it outputs a NAND signal through the output terminal 22. The processor 101 controls the NOR memory 102 or the NAND memory 103 to start Uboot according to the NOR signal or NAND signal received by the reading terminal 1012 through the communication terminal 1013. In this way, the system can update the Uboot file online through the NAND memory 103, and switch to the NOR memory 102 to start the system in time when the update fails, so as to ensure the normal startup and operation of the system and effectively prevent the system from failing to start.

[0030] See Figures 1 to 6 The control unit 1 is equipped with a timer, which is used to calculate the time interval between the receiving end 11 receiving a failure signal and receiving a success signal. The control unit 1 is used to control the first control end 12 to output a first switching signal or a second switching signal according to the time interval.

[0031] Specifically, in this embodiment, the processor 101 is a CPU, the status terminal 1011 is the CP_MPP3 pin of the CPU, the control unit 1 is a CPLD, the receiving terminal 11 is the PROCHOT_CPU pin (PIN47) of the CPLD, and the first control terminal 12 is the UCD9090_ALERT_L pin (PIN24) of the CPLD.

[0032] For example, after the device is powered on, the CPU's CP_MPP3 pin outputs a high-level signal (failure signal) by default. If the system is running Uboot normally, the CPU will output a low-level signal (success signal) through the CP_MPP3 pin within about 6 seconds and maintain it. If the system fails to boot, the CPU cannot reconfigure the output signal of the CP_MPP3 pin, so it will maintain the default high-level signal.

[0033] Therefore, the time interval threshold is set to 6 seconds. CPLD's PIN24 outputs a low-level signal (second switching signal) by default. CPLD will change the output level of PIN24 according to the state of the input level of PIN47: within 6 seconds after the device is powered on, if CPLD recognizes that the signal received by PIN47 changes from a high-level signal (failure signal) to a low-level signal (success signal), it will maintain the low-level signal output by PIN24 (second switching signal). If the signal received by PIN47 is still a high-level signal (failure signal) after 6 seconds of device power-on, CPLD will modify the low-level signal output by PIN24 (second switching signal) to a high-level signal (first switching signal).

[0034] Specifically, in this embodiment, the switching unit 2 includes a first switcher 23 and a second switcher 24, both of which are PCA9560 (multiplexing switch chip with EEPROM function). The MUX_SELECT_0 pin and the MUX_SELECT_1 pin of the first switcher 23 and the second switcher 24 form the second control terminal 21 of the switching unit 2. The MUX_SELECT_1 pin is maintained at a high level by an external pull-up, and the MUX_SELECT_0 pin is connected to PIN24 of the CPLD to receive the low-level signal (second switching signal) and the high-level signal (first switching signal) output by PIN24.

[0035] Specifically, the first switcher 23 and the second switcher 24 determine whether the switching unit 2 switches to the first mode or the second mode based on the level state of the MUX_SELECT_0 / 1 pin. When PIN24 outputs a low-level signal, the switching unit 2 recognizes that the MUX_SELECT_0 / 1 pin is 01, and then switches to the second mode, i.e., the internal memory mode. When PIN24 outputs a high-level signal, the switching unit 2 recognizes that the MUX_SELECT_0 / 1 pin is 11, and then the switching unit 2 switches to the first mode, i.e., the external configuration mode.

[0036] See Figures 1 to 6 The first mode is the external configuration mode. The switching unit 2 is equipped with an external input terminal. When the switching unit 2 is in the first mode, it is used to output a NOR signal through the output terminal 22 according to the external configuration signal received by the external input terminal.

[0037] Furthermore, the switching unit 2 includes a first switch 23 and a second switch 24. The first switch 23 is provided with a plurality of first input pins 231 and a first output pin 232. The second switch 24 is provided with a plurality of second input pins 241 and a second output pin 242. The first input pins 231 and the second input pins 241 are combined to form an external input terminal, and the first output pins 232 and the second output pins 242 are combined to form an output terminal 22.

[0038] Specifically, in this embodiment, the MUX_IN_A-E pins (5 pins) of the first switch 23 serve as the first input pin 231, and the MUX_IN_A-E pins of the second switch 24 serve as the second input pin 241. An external circuit configures the MUX_IN_A-E pins of the first switch 23 to a low level, and configures the MUX_IN_A / D / E pins of the second switch 24 to a high level. The MUX_IN_B / C pins of the second switch 24 are also configured to a low level to input an external configuration signal to the switching unit 2. The MUX_OUT_A-E pins of the first switch 23 and the second switch 24 serve as the first output pin 232 and the second output pin 242, respectively, to form the output terminal 22. When the switching unit 2 is in external configuration mode, the first switch 23 and the second switch 24 output 0x32 (NOR signal) through the combination of the first output pin 232 and the second output pin 242 according to the aforementioned external configuration signal.

[0039] Specifically, in this embodiment, the CPU's CP_MPP[18-23] pins serve as the read terminal 1012 of the processor 101. The CPU uses the signals identified by the CP_MPP[18-23] pins to configure the boot mode of Uboot. When the first output pin 232 and the second output pin 242 of the first switch 23 and the second switch 24 are combined and output as 0x32 (NOR signal) through the CP_MPP[18-23] pins, the CPU determines that Uboot is booted through NOR memory, but is not limited to this.

[0040] See Figures 1 to 6 The second mode is the internal memory mode. The switching unit 2 is equipped with a register that records the stored value. When the switching unit 2 is in the second mode, it is used to output the NAND signal through the output terminal 22 according to the stored value.

[0041] Furthermore, the processor 101 also includes multiple first write pins 1014, and the switching unit 2 includes a first switch 23 and a second switch 24. The first switch 23 is provided with a first register, and the second switch 24 is provided with a second register. The first switch 23 is provided with multiple second write pins 233 and a first output pin 232, and the second switch 24 is provided with multiple third write pins 243 and a second output pin 242. The first write pins 1014 are connected to the second write pins 233 and the third write pins 243 respectively. The processor 101 writes a first stored value and a second stored value to the first register and the second register respectively through the second write pins 233 and the third write pins 243. The first output pins 232 and the second output pins 242 are combined to form an output terminal 22.

[0042] Specifically, in this embodiment, the CPU's CP_I2C0_SCL and CP_I2C0_SDA pins are configured as the first write pin 1014, and the SCL and SDA pins of the first switch 23 and the second switch 24 are configured as the second write pin 233 and the third write pin 243, respectively. This enables the processor 101 to establish a communication connection with the first switch 23 and the second switch 24 through the I2C0 interface. When the system boots up normally using Uboot, the CPU will send data to the 0x00 register (first...) of the EEPROM inside the first switch 23 at address 0x4C via the I2C0 interface. The first switch 23 writes 0x10 (first stored value) to the register and writes 0x07 (second stored value) to the 0x00 register (second register) of the internal EEPROM of the second switch 24 at address 0x4E. The MUX_OUT_A-E pins of the first switch 23 and the second switch 24 are respectively used as the first output pin 232 and the second output pin 242, and are combined to form the output terminal 22. When the switching unit 2 is in the internal memory mode, the first switch 23 and the second switch 24 output 0x0F (NAND signal) through the combination of the first output pin 232 and the second output pin 242 according to the first stored value and the second stored value.

[0043] Specifically, in this embodiment, the CPU's CP_MPP[18-23] pins serve as the read terminal 1012 of the processor 101. The CPU uses the signals identified by the CP_MPP[18-23] pins to configure the boot mode of Uboot. When the first output pin 232 and the second output pin 242 of the first switch 23 and the second switch 24 are combined and output 0x0F (NAND signal) through the CP_MPP[18-23] pins, the CPU determines that Uboot is booted through NAND memory, but is not limited to this.

[0044] Please see Figures 1 to 6The present invention discloses a control device, which includes: the Uboot boot control module as described above, a processor, a NOR memory and a NAND memory.

[0045] See Figures 1 to 6 In this embodiment, the specific process by which the Uboot boot control module controls the processor 101 to switch between NOR memory 102 and NAND memory 103 to boot Uboot is as follows:

[0046] After the system is powered on, the MUX_SELECT_0 and MUX_SELECT_1 pins of the first switch 23 and the second switch 24 are at the level state of 01 by default. The switching unit 2 is in the second mode by default, that is, the internal memory mode. However, when the system is powered on, the 0x00 register of the EEPROM inside the first switch 23 and the second switch 24 is not written with a storage value. Its contents are all 0x00. The first switch 23 and the second switch 24 cannot output 0x0F (NAND signal) through the combination of the first output pin 232 and the second output pin 242. This makes it impossible for the CPU to recognize 0x0F (NAND signal) through the CP_MPP[18-23] pin and call the NAND memory to start Uboot, which in turn causes the CPU to fail to start normally.

[0047] At this time, 6 seconds after the device is powered on, the CPU's CP_MPP3 pin will maintain the default high-level signal, causing the signal received by CPLD's PIN47 to still be a high-level signal (failure signal). Then, CPLD will modify the low-level signal (second switching signal) output by PIN24 to a high-level signal (first switching signal), causing the MUX_SELECT_0 and MUX_SELECT_1 pins of the first switcher 23 and the second switcher 24 to switch to 11. Switching unit 2 switches to the first mode, i.e., external configuration mode. The first switcher 23 and the second switcher 24 output 0x32 (NOR signal) through the combination of the first output pin 232 and the second output pin 242. The CPU recognizes 0x32 (NOR signal) through the CP_MPP[18-23] pin and calls the NOR memory 102 to start Uboot. Since the NOR memory 102 is a pre-burned Uboot, the CPU starts normally.

[0048] After the system boots up normally using Uboot, the CPU writes 0x10 (first stored value) to the 0x00 register (first register) of the EEPROM inside the first switch 23 at address 0x4C via the I2C0 interface, and writes 0x07 (second stored value) to the 0x00 register (second register) of the EEPROM inside the second switch 24 at address 0x4E, so that the registers of the switching unit 2 record the stored value.

[0049] When the system rewrites the EEPROM value, the system will reset and restart once. Since the MUX_SELECT_0 and MUX_SELECT_1 pins of the first switch 23 and the second switch 24 are 01 by default, the switching unit 2 is in the second mode by default, that is, the internal memory mode. At this time, the first switch 23 and the second switch 24 can output 0x0F (NAND signal) through the combination of the first output pin 232 and the second output pin 242 according to the first and second storage values ​​mentioned above. The CPU reads and recognizes the signal through the CP_MPP[18-23] pin to call the NAND memory 103 to start Uboot, and the system works normally.

[0050] When the system version needs to be updated, only the new U-boot version file needs to be updated to the NAND memory. If the online update fails due to network outages or other reasons, resulting in the loss of the U-boot file and the CPU failing to reboot normally, the CPU's CP_MPP3 pin will maintain a high-level output signal 6 seconds after the device powers on. The CPLD will then modify the low-level signal (second switching signal) output by PIN24 to a high-level signal (first switching signal) based on the high-level signal (failure signal) received by PIN47, thus enabling the M-mode of the first switcher 23 and the second switcher 24 to switch. The level states of the UX_SELECT_0 pin and the MUX_SELECT_1 pin are switched to 11, and the switching unit 2 is switched to the first mode, namely the external configuration mode. The first switcher 23 and the second switcher 24 output 0x32 (NOR signal) through the combination of the first output pin 232 and the second output pin 242. The CPU recognizes 0x32 (NOR signal) through the CP_MPP[18-23] pin and calls the NOR memory 102 to start Uboot, ensuring that the CPU can switch to start through the NOR memory 102 after failing to start through the NAND memory 103.

[0051] By using the first switch 23 and the second switch 24 in conjunction with the control unit 1, the Uboot loading mode can be switched online. This enables the system to update the Uboot file online via NAND memory. Furthermore, in the event of a Uboot malfunction, the system can be switched to NOR memory for booting, ensuring normal system startup and effectively avoiding the problem of system failure due to NAND memory update / upgrade failure.

[0052] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the scope of the present utility model application shall still fall within the scope of the present utility model.

Claims

1. A Uboot start control module, used for controlling a processor to start Uboot through a NOR memory or a NAND memory, the processor comprising a state terminal, a reading terminal and a communication terminal, the communication terminal being in communication connection with the NOR memory and the NAND memory, characterized in that, The control module comprises: a control unit, the control unit comprises a receiving end and a first control end, the receiving end is connected with the state end, and the control unit is used for outputting a first switching signal or a second switching signal through the first control end according to a success signal or a failure signal output by the state end; a switching unit, the switching unit is provided with a first mode and a second mode, the switching unit comprises a second control end and an output end, the second control end is connected with the first control end, and the switching unit is used for switching to the first mode or the second mode according to the first switching signal or the second switching signal received by the second control end, the switching unit outputs a NOR signal through the output end when the switching unit is in the first mode, and the switching unit outputs a NAND signal through the output end when the switching unit is in the second mode; the reading end is connected with the output end, and the processor controls the NOR memory or the NAND memory to start Uboot through the communication end according to a NOR signal or a NAND signal received by the reading end.

2. The Uboot boot control module of claim 1, wherein, The control unit is provided with a timer, the timer is used for calculating a time interval between the receiving end receiving the failure signal and receiving the success signal, and the control unit is used for controlling the first control end to output the first switching signal or the second switching signal according to the time interval.

3. The Uboot boot control module of claim 1, wherein, The first mode is an external configuration mode, the switching unit is provided with an external input end, and the switching unit is used for outputting a NOR signal through the output end according to an external configuration signal received by the external input end when the switching unit is in the first mode.

4. The Uboot boot control module of claim 3, wherein, The switching unit comprises a first switcher and a second switcher, the first switcher is provided with a plurality of first input pins and a first output pin, the second switcher is provided with a plurality of second input pins and a second output pin, the first input pins and the second input pins are combined to form the external input end, and the first output pin and the second output pin are combined to form the output end.

5. The Uboot boot control module of claim 1, wherein, The second mode is an internal memory mode, the switching unit is provided with a register, the register records a storage value, and the switching unit is used for outputting a NAND signal through the output end according to the storage value when the switching unit is in the second mode.

6. The Uboot boot control module of claim 5, wherein, The processor further comprises a plurality of first write pins, the switching unit comprises a first switcher and a second switcher, the first switcher is provided with a first register, the second switcher is provided with a second register, the first switcher is provided with a plurality of second write pins and a first output pin, the second switcher is provided with a plurality of third write pins and a second output pin, the first write pins are connected with the second write pins and the third write pins respectively, the processor writes a first storage value and a second storage value into the first register and the second register through the second write pins and the third write pins respectively, and the first output pin and the second output pin are combined to form the output end.

7. A control device characterized by comprising: Comprise: The Uboot startup control module, the processor, the NOR memory and the NAND memory according to any one of claims 1 to 6.

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