General protocol processing board and system

Abstract

The utility model relates to a universal protocol processing board and system. The universal protocol processing board comprises a carrier board and a plurality of core boards, the core board comprises a central processing unit, and the carrier board comprises a field programmable logic gate array and a plurality of inter-board communication components; the central processing unit of each core board is connected with the field programmable logic gate array through an inter-board communication assembly; the field programmable logic gate array is at least used for forwarding a preset number of to-be-processed signals to each central processing unit through the inter-board communication component; and the central processor is at least used for performing protocol conversion on the received to-be-processed signal. Thus, the central processing unit of each core board is connected with the field programmable logic gate array through the inter-board communication assembly, the field programmable logic gate array can be used for signal forwarding, it is guaranteed that the multiple central processing units process related tasks in parallel, and then the processing efficiency of the general protocol processing board is effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer engineering technology, and in particular to a general protocol processing board and system. Background Technology

[0002] In the field of computer engineering, a general-purpose protocol processing board is a hardware component used in communication systems to process data streams of various communication protocols, playing a key role in network infrastructure, data centers, communication equipment, and embedded systems.

[0003] Currently, existing general-purpose protocol processing boards are typically configured with a single processor, such as an x86 processor, which is used to perform protocol conversion on received signals or other tasks. However, the processing speed of such general-purpose protocol processing boards is limited, and their processing efficiency will be low when there are many tasks to process. Utility Model Content

[0004] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a general protocol processing board and system.

[0005] This disclosure provides a general protocol processing board, including: a carrier board and multiple core boards; the core boards include a central processing unit, and the carrier board includes a field-programmable gate array and multiple inter-board communication components;

[0006] The central processing unit of each core board is connected to the field-programmable gate array via an inter-board communication component.

[0007] The field-programmable gate array is used at least to forward a preset number of signals to be processed to each of the central processing units via the inter-board communication components; the central processing unit is used at least to perform protocol conversion on the received signals to be processed.

[0008] Optionally, the inter-board communication component includes: a first network interface card (NIC) chip and a first Ethernet transceiver;

[0009] One end of the first network interface card chip and the first Ethernet transceiver are both connected to the central processing unit, and the other end of the first network interface card chip and the first Ethernet transceiver are both connected to the field-programmable gate array.

[0010] Optionally, the carrier board further includes a plurality of carrier board memory chips;

[0011] Multiple carrier memory chips are respectively connected to the field-programmable gate array.

[0012] Optionally, the plurality of said carrier memory chips include DDR3 chips and SRAM chips.

[0013] Optionally, the core board further includes a second network card chip, multiple core board storage chips, and a power-on / off control module;

[0014] The second network interface card chip and the multiple core board storage chips are respectively connected to the central processing unit; the second network interface card chip, the central processing unit, and the multiple core board storage chips are all connected to the power-on / off control module.

[0015] Optionally, the multiple core board storage chips include EEPROM chips, DDR4 chips, SSD chips, and FLASH chips.

[0016] Optionally, the power-on / off control module includes a CPLD chip.

[0017] Optionally, the carrier board further includes a network management component;

[0018] Each of the core boards is connected to the network management component.

[0019] Optionally, the network management component includes a second Ethernet transceiver and an Ethernet switching chip;

[0020] The second Ethernet transceiver is connected to the central processing unit in sequence through the Ethernet switching chip and the second network interface card chip.

[0021] This disclosure also provides a general protocol processing board system, including a baseboard and any of the above-described general protocol processing boards;

[0022] The general protocol processing board is connected to the base plate.

[0023] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0024] The general protocol processing board provided in this embodiment includes a carrier board and multiple core boards. Each core board includes a central processing unit (CPU), and the carrier board includes a field-programmable gate array (FPGA) and multiple inter-board communication components. The CPU of each core board is connected to the FPGA via an inter-board communication component. The FPGA is used to forward a preset number of signals to be processed to each CPU via the inter-board communication components. The CPU is used to perform protocol conversion on the received signals to be processed. Thus, by configuring each core board's CPU to be connected to the FPGA via an inter-board communication component, the FPGA can be used for signal forwarding, ensuring that multiple CPUs process related tasks in parallel, thereby effectively improving the processing efficiency of the general protocol processing board. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a general protocol processing board provided in an embodiment of the present disclosure;

[0028] Figure 2 This is a schematic diagram of another general protocol processing board provided in an embodiment of the present disclosure;

[0029] Figure 3 This is a schematic diagram of the structure of a core board provided in an embodiment of the present disclosure;

[0030] Figure 4 A schematic diagram illustrating the principle structure of a second network interface card (NIC) chip provided in an embodiment of this disclosure;

[0031] Figure 5 This is a schematic diagram illustrating the principle structure of a network management component provided in an embodiment of this disclosure.

[0032] The components are as follows: 01. Power module; 02. Clock module; 03. Reset module; 04. Transformer; 05. Rear panel output terminals; 110. Carrier board; 111. Field-programmable gate array (FPGA); 1121. First network interface card (NIC) chip; 1122. First Ethernet transceiver; 112. Inter-board communication component; 113. Carrier board memory chip; 1131. DDR3 chip; 1132. SRAM chip; 114. Network management component; 1141. Second Ethernet transceiver; 1142. Ethernet switching chip. ; 115. Second connector; 1161. Optical module; 1162. Electrical module; 1163. Signal transmission line; 117. IPMI module; 120. Core board; 121. Central processing unit; 122. Second network card chip; 123. Core board storage chip; 1231. EEPROM chip; 1232. DDR4 chip; 1233. SSD chip; 1234. FLASH chip; 124. Power-on / off control module; 125. First connector; 126. Power supply chip. Detailed Implementation

[0033] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0034] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0035] The general protocol processing board and system provided in the embodiments of this disclosure will be described by way of example below with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of the structure of a general protocol processing board provided in an embodiment of the present disclosure, with reference to... Figure 1 The general protocol processing board includes a carrier board 110 and multiple core boards 120. Each core board 120 includes a central processing unit (CPU) 121, and the carrier board 110 includes a field-programmable gate array (FPGA) 111 and multiple inter-board communication components 112. Each CPU 121 of each core board 120 is connected to the FPGA 111 via an inter-board communication component 112. The FPGA 111 is used at least to forward a preset number of signals to be processed to each CPU 121 via the inter-board communication component 112. The CPU 121 is used at least to perform protocol conversion on the received signals to be processed.

[0037] Multiple core boards 120 are located on a carrier board 110, which carries the multiple core boards 120. For example, the number of core boards 120 can be two, three or other numbers, and the number of core boards 120 can be set according to actual processing requirements, which is not limited here.

[0038] The inter-board communication component 112 is used to realize network communication between the carrier board 110 and the core board 120. The field programmable gate array 111 (FPGA) uses a dedicated interface to transmit the signal to be processed to the central processing unit 121 (CPU). The dedicated interface may include PCIe, SPI, etc., and is not limited here.

[0039] The signals to be processed include data signals and control signals. Data signals require protocol conversion, while control signals do not. Specifically, after receiving the incoming signals to be processed, the field-programmable gate array (FPGA) 111 forwards a preset number of signals to be processed to each central processing unit (CPU) 121 through the inter-board communication component 112. This allows multiple CPUs 121 to process related tasks in parallel, achieving collaborative sharing of incoming signals. Simultaneously, the FPGA 111 can dynamically allocate tasks based on the availability of each CPU 121, such as forwarding the same number of signals to each CPU 121 or forwarding different numbers of signals. This maximizes the processing performance of a single CPU 121 and prevents one CPU 121 from being overloaded while others remain idle, thereby effectively improving the overall processing efficiency of the general-purpose protocol processing board.

[0040] Understandably, the field-programmable gate array 111 has hardware isolation capabilities. The field-programmable gate array 111 provides hardware-level isolation for different central processing units 121, ensuring that the signals (such as signals to be processed) or data received by each central processing unit 121 are not duplicated, that is, the tasks are independent of each other, which helps each central processing unit 121 to work efficiently.

[0041] Specifically, after receiving the signal to be processed, the central processing unit 121 first performs decoding and other operations on the signal, and then performs protocol conversion on the signal, converting the protocol corresponding to the signal to be processed into a general protocol to obtain a general protocol signal. The central processing unit 121 then sends the general protocol signal to the field-programmable gate array 111, which then transmits it outwards for external devices to receive and process. It should be noted that the general protocol signal is a signal that external devices can process; the general protocol may include network communication protocols such as UDP and TCP, but is not limited here.

[0042] The general protocol processing board provided in this embodiment includes: a carrier board 110 and multiple core boards 120; each core board 120 includes a central processing unit 121, and the carrier board 110 includes a field-programmable gate array (FPGA) 111 and multiple inter-board communication components 112; the FPGA 121 of each core board 120 is connected to the FPGA 111 through an inter-board communication component 112; the FPGA 111 is used at least to forward a preset number of signals to be processed to each FPGA 121 through the inter-board communication component 112; the FPGA 121 is used at least to perform protocol conversion on the received signals to be processed. Thus, by configuring each FPGA 121 of each core board 120 to be connected to the FPGA 111 through an inter-board communication component 112, the FPGA 111 can be used for signal forwarding, ensuring that multiple FPGAs 121 process related tasks in parallel, enhancing parallel processing capabilities, and thereby effectively improving the processing efficiency of the general protocol processing board.

[0043] In addition, based on the above architecture, this disclosure also provides a fully domestically produced design and selection scheme, providing a secure and independent general protocol processing board design for special national industries. The design will be described in detail below with reference to various embodiments.

[0044] In some embodiments, the central processing unit is selected from the FT-2000 / 4 chip.

[0045] The FT-2000 / 4 chip integrates four Phytium-developed next-generation high-performance processor cores, FTC663, employing an out-of-order four-issue superscalar pipeline. It is compatible with the 64-bit ARMV8 instruction set and supports both ARM64 and ARM32 execution modes. It supports single-precision and double-precision floating-point instructions and ASIMD processing instructions, as well as hardware virtualization. Furthermore, the FT-2000 / 4 chip enhances chip security at the hardware level, supporting Phytium's self-defined processor security architecture standard, PSPA, to meet the performance and security requirements of more complex application scenarios. In addition, all security-related modules in the FT-2000 / 4 chip are designed independently by Phytium, making it the first domestically produced CPU to effectively support the Trusted Computing 3.0 standard at the CPU level.

[0046] In some embodiments, the field-programmable gate array is selected from the Virtex-7 series FPGA.

[0047] The Virtex-7 series FPGAs boast industry-leading FPGA system performance and capacity, achieving a breakthrough capacity with up to 2 million logic cells. Furthermore, the Virtex-7 series supports 400G bridging and switching wired communication systems, making it a core component of global wired infrastructure. It also supports advanced radar systems and high-performance computer systems, meeting the requirements of single-chip multiply-accumulate operations per second (TeraMACC) signal processing capabilities, as well as the logic density, performance, and I / O bandwidth requirements of next-generation test and measurement equipment. It enables next-generation 100GB line cards, 300G bridges, terabit-level switch architectures, 100G OTN wavelength converters, radar, and ASIC emulation.

[0048] In other implementations, the field-programmable gate array can also use the JFM7VX690T chip from Shanghai Fudan Microelectronics. The JFM7VX690T chip is functionally compatible and pin-to-pin compatible with the Xilinx Virtex-7 series XC7VX690T chip.

[0049] The general protocol processing board provided in this disclosure uses a carrier board and a core board to achieve a multi-core heterogeneous circuit design. It can schedule different cores according to task processing requirements. For example, the central processing unit of the core board performs main control functions, including but not limited to protocol conversion of the signal to be processed. The carrier board uses a field-programmable gate array (FPGA) to forward signals. The FPGA forwards the signals to be processed to the core board, ensuring that different core boards do not process the same signal repeatedly. This improves the working efficiency of the general protocol processing board and optimizes its overall energy efficiency.

[0050] Furthermore, the general-purpose protocol processing board is equipped with multiple core boards. If one core board fails or malfunctions, other core boards can continue processing the current task, thus preventing a single point of failure from causing the entire general-purpose protocol processing board to crash. This ensures the continuous operation of the general-purpose protocol processing board and improves its operational reliability. Preferably, the general-purpose protocol processing board is equipped with two core boards, avoiding the resource waste and redundancy problems associated with having three or more core boards.

[0051] In some embodiments, Figure 2 This is a schematic diagram of another general protocol processing board provided in an embodiment of the present disclosure. Figure 1 Based on, refer to Figure 2The inter-board communication component 112 includes: a first network interface card (NIC) chip 1121 and a first Ethernet transceiver 1122; one end of the first NIC chip 1121 and the first Ethernet transceiver 1122 are both connected to the central processing unit 121, and the other end of the first NIC chip 1121 and the first Ethernet transceiver 1122 are both connected to the field programmable gate array 111.

[0052] The first network interface card chip 1121 and the first Ethernet transceiver 1122 are both used to realize Ethernet communication between the field programmable gate array 111 and the central processing unit 121. The first network interface card chip 1121 is mainly used to transmit data signals in the signal to be processed, and the first Ethernet transceiver 1122 is mainly used to transmit instructions.

[0053] It should be noted that the first network card chip 1121 and the first Ethernet transceiver 1122 can use different protocols (referring to communication protocols) to transmit the signal to be processed, and the specific type of communication protocol is related to the model selected by the two, which will be illustrated in the following text.

[0054] In some embodiments, refer to Figure 2 The first network card chip 1121 is a domestic WX1820AL chip, and the first Ethernet transceiver 1122 is a domestic YT8521SH chip from Yutai Chetong.

[0055] Among them, the WX1820AL chip is a 10 Gigabit Ethernet card chip. Compared with the YT8521SH chip, the WX1820AL chip supports higher bandwidth Ethernet communication, while the YT8521SH chip supports lower bandwidth Ethernet communication.

[0056] Specifically, during network communication between the Field Programmable Gate Array (FPGA) 111 and the Central Processing Unit (CPU) 121, different interfaces between the two have corresponding communication protocols. For example, the WX1820AL chip supports PCIe interface to 10GBASE-R interface conversion. The WX1820AL chip connects to the core board 120 via the PCIe interface, and the communication protocol corresponding to this interface path is PCIe. It also connects to the FPGA 111 via the 10GBASE-R interface, and the communication protocol corresponding to this interface path is 10GBASE-R. Similarly, the YT8521SH chip supports RGMII interface to SGMII interface conversion. The YT8521SH chip connects to the core board 120 via the RGMII interface, and the communication protocol corresponding to this interface path is RGMII. It also connects to the FPGA 111 via the SGMII interface, and the communication protocol corresponding to this interface path is SGMII.

[0057] For control signal transmission, the field-programmable gate array 111 is connected to the first Ethernet transceiver 1122 via the SGMII interface, and the first Ethernet transceiver 1122 is connected to the central processing unit 121 via the RGMII interface; for data signal transmission, the field-programmable gate array 111 is connected to the first network interface card chip 1121 via 10G-R, and the first network interface card chip 1121 is connected to the central processing unit 121 via the PCIe protocol.

[0058] In some embodiments, refer to Figure 2 The carrier board 110 also includes multiple carrier board memory chips 113; the multiple carrier board memory chips 113 are respectively connected to the field programmable gate array 111.

[0059] Among them, the carrier board storage chip 113 is a chip with storage function on the carrier board 110. Specifically, by setting multiple carrier board storage chips 113 to be connected to the field programmable gate array 111 respectively, data, programs and other data for the field programmable gate array 111 can be stored in a timely manner, thereby meeting the operating requirements of the field programmable gate array 111.

[0060] In some embodiments, Figure 1 Based on this, continue to refer to Figure 2 The multiple carrier board memory chips 113 include DDR3 chip 1131 and SRAM chip 1132.

[0061] Among them, the DDR3 (Double-Data-Rate Three) chip 1131, namely the third-generation double data rate synchronous dynamic random access memory, provides large-capacity storage and high-bandwidth transmission capabilities, making it suitable for applications that require processing large amounts of data, such as high-performance computing, image processing, and video streaming processing. For example, such as... Figure 2 As shown, the DDR3 chip 1131 can be a 16-bit wide DDR3 memory chip from Xi'an Ziguang Guoxin Co., Ltd., with the model number SCB13H8G162BF. It adopts a dual-channel 32-bit wide design, with each channel containing 2 chips, which can meet the requirement of no less than 1GB of single-channel memory.

[0062] Among them, the SRAM (Static Random Access Memory) chip 1132 provides low latency and fast access capabilities, making it suitable for applications requiring frequent, fast access to small blocks of data, such as caches, buffers, and state machine control. For example, such as... Figure 2 As shown, the SRAM chip 1132 can be the JFM25Q256 chip from Shanghai Fudan Microelectronics, which stores the FPGA firmware.

[0063] In some embodiments, Figure 3This is a schematic diagram of the structure of a core board provided in an embodiment of the present disclosure. Figure 2 Based on, refer to Figure 3 The core board 120 also includes a second network card chip 122, multiple core board storage chips 123, and a power-on / off control module 124; the second network card chip 122 and the multiple core board storage chips 123 are respectively connected to the central processing unit 121; the second network card chip 122, the central processing unit 121, and the multiple core board storage chips 123 are all connected to the power-on / off control module 124.

[0064] The second network interface card (NIC) chip 122 is used to enable network communication between the central processing unit (CPU) 121 and external devices. For example, the second NIC chip 122 can be a domestically produced WX1860AL chip. The WX1860AL chip has integrated hardware acceleration capabilities, can perform 1000BASE-T / 100BASE-T / 10BASE-T adaptive transmission, is compatible with network devices of different speeds, and also supports the RGMII interface. Figure 2 As shown, the central processing unit 121 can be connected to the second network card chip 122 via PCIe x4, and two Gigabit Ethernet 1000BASE-T ports can be brought out for network management and switching.

[0065] Among them, the core board storage chip 123 is a chip with storage function on the core board 120. Specifically, by setting multiple core board storage chips 123 to be connected to the central processing unit 121, data, programs, etc. for the central processing unit 121 can be stored in a timely manner, thereby meeting the operating requirements of the central processing unit 121.

[0066] The power-on / off control module 124 is mainly used to control the power-on / off sequence of relevant chips in the core board 120, and it is often connected to the power supply chip. Specifically, by setting the power-on / off control module 124 to connect to the second network card chip 122, the central processing unit 121 and multiple core board storage chips 123 via the power supply chip, the power-on / off control module 124 can control the enable sequence of the power supply chip, and then control the second network card chip 122, the central processing unit 121 and the multiple core board storage chips 123 to be powered on (or powered off) in a set order, so as to achieve precise control of the power-on (or power-off) sequence of the above-mentioned relevant chips and ensure the stability and reliability of the core board 120.

[0067] In addition, the power-on / off control module 124 also has a reset function. Specifically, the power-on / off control module 124 is connected to the central processing unit 121 and the second network card chip 122 to control the central processing unit 121 and the second network card chip 122 to reset.

[0068] In some embodiments, the WX1820AL chip is a Gigabit Ethernet controller, and the WX1860AL chip is a 10 Gigabit Ethernet controller.

[0069] In practical applications, Ethernet controllers are also known as network interface cards (NICs). The WX1820AL and WX1860AL chips each belong to Ethernet controllers that support different bandwidths.

[0070] In some embodiments, refer to Figure 3 The core board 120 also includes a power supply chip 126.

[0071] The power supply chip 126 provides power to the entire core board 120 to support its operation. For example, as shown... Figure 3 As shown, the power supply chip 126 can be represented as Power Supply, and the power supply chip 126 can be a domestic TX4644 chip, a domestic XSC74401 chip, or a domestic XSC51200 chip.

[0072] In some embodiments, Figure 4 This is a schematic diagram illustrating the principle structure of a second network interface card (NIC) chip provided in an embodiment of this disclosure. Figure 3 Based on, refer to Figure 4 The core board 120 also includes a power module 01, a clock module 02, a reset module 03, and a transformer 04; the power module 01, clock module 02, reset module 03, transformer 04, and at least one core board memory chip 123 are all connected to the second network card chip 122.

[0073] The power supply module 01 supplies power to the second network interface card (NIC) chip 122; the clock module 02 provides a clock signal to the second NIC chip 122 so that the second NIC chip 122 can control the data sampling and transmission rate based on the precise clock signal, ensuring the synchronization and reliability of data transmission. It can be selected from the XO32 / XO75L / XO32F series of Jingyuxing; the reset module 03 provides a reset signal to the second NIC chip 122 to ensure that it can be correctly initialized, restored to a known state, or recovered from an abnormal state; the transformer 04 provides electrical isolation and impedance matching for the second NIC chip 122 to ensure that the signal transmission or command transmission process between it and the subsequent chips is both safe and efficient.

[0074] For example, the second network interface card chip 122 can be connected to the FLASH chip 1234 so that the second network interface card chip 122 can be driven by the FLASH chip 1234.

[0075] In some embodiments, refer to Figure 2 and Figure 3The core board storage chips 123 include EEPROM chip 1231, DDR4 chip 1232, SSD chip 1233 and FLASH chip 1234.

[0076] Among them, the EEPROM (Electrically Erasable Programmable Read-Only Memory) chip 1231 is used to store the system log of the central processing unit 121, which is suitable for applications that require frequent updates but have a small amount of data. For example, the EEPROM can be a domestically produced BL24C02F chip.

[0077] The DDR4 (Double Data Rate Fourth) chip 1232, also known as fourth-generation double data rate synchronous dynamic random access memory, serves as the memory of the central processing unit 121. It stores programs and data currently running on the central processing unit 121 and provides fast read and write access capabilities. For example, the DDR4 chip 1232 can be an 8-bit DDR4 chip from Changxin, model CXDQ3A8AM-WG, with a single-chip capacity of 1GB and using one memory controller channel of the central processing unit 121.

[0078] The SSD (Solid State Disk) chip 1233 is a solid-state drive used for operating system and application storage. For example, the SSD chip 1233 can be an SSD chip packaged using Ball Grid Array (BGA) technology (abbreviated as BGASSD), specifically an Anxinda SSD storage chip, model AS689GEF, with a capacity of 512GB.

[0079] The FLASH chip 1234 is a flash memory chip used for firmware loading of the central processing unit 121. It does not lose data due to power failure and can quickly read data. For example, the FLASH chip 1234 can be a GD25LQ256 chip from GigaDevice, with a capacity of 256Mbit.

[0080] For example, with Figure 3Taking the illustrated structure as an example, the EEPROM chip 1231 is connected to the central processing unit 121 via an I2C interface, the DDR4 chip 1232 is connected to the central processing unit 121 via the MEM0 signal line, the SSD chip 1233 is connected to the central processing unit 121 via a PCIe x4 interface, and the FLASH chip 1234 is connected to the central processing unit 121 via a QSPI interface. It should be noted that the central processing unit 121 includes two memory controllers, one of which is typically represented by Memory0. Therefore, the MEM0 signal line represents the connection between the DDR4 chip 1232 and Memory0.

[0081] In some embodiments, refer to Figure 2 and Figure 3 The power-on / off control module 124 includes a CPLD chip.

[0082] Among them, CPLD (Complex Programmable Logic Device) chips are complex programmable logic chips. For example, the CPLD chip can be the Guowei SM2210 chip.

[0083] In some embodiments, refer to Figure 2 The carrier board 110 also includes a network management component 114; each core board 120 is connected to the network management component 114.

[0084] The network management component 114 is used to implement network management for multiple core boards 120 and to enable high-bandwidth network exchange between any two core boards 120. Specifically, in terms of network management, when an external device needs to manage a core board 120, it can send control commands to the network management component 114. The network management component 114 then forwards the control commands to the central processing unit 121 in each core board 120, and the central processing unit 121 responds to the control commands to meet the management requirements of the external device.

[0085] In terms of network exchange, the two central processing units 121 can transmit relevant data, such as data files and application data, through the network management component 114, thereby realizing network exchange between the two core boards 120. The specific type of data is not limited here.

[0086] In some embodiments, Figure 5 This is a schematic diagram illustrating the principle structure of a network management component provided in an embodiment of the present disclosure. Figure 2 Based on, refer to Figure 5 The network management component 114 includes a second Ethernet transceiver 1141 and an Ethernet switching chip 1142; the second Ethernet transceiver 1141 is connected to the central processing unit 121 in sequence through the Ethernet switching chip 1142 and the second network card chip 122.

[0087] The second Ethernet transceiver 1141, the Ethernet switching chip 1142, and the second network interface card chip 122 can all perform interface conversion and transmit external input commands and signals based on the interface conversion. It should be noted that each interface has a corresponding communication protocol or interface specification. The type of interface actually converted depends on the specific model of the second Ethernet transceiver 1141, the Ethernet switching chip 1142, and the second network interface card chip 122, which will be illustrated in the following text.

[0088] In practical applications, the second Ethernet transceiver 1141 is mainly used for signal transmission and reception. For example, in signal transmission scenarios, when an Ethernet device (such as a computer, switch, etc.) needs to send a data signal, the second Ethernet transceiver 1141 will convert the data signal into an electrical signal and send it to the Ethernet switching chip 1142 through a cable. In signal reception scenarios, when the second Ethernet transceiver 1141 receives a data signal on the cable, it will convert the data signal into an electrical signal and transmit it to the corresponding Ethernet device. During this process, the second Ethernet transceiver 1141 will amplify, shape, and restore the data signal to ensure correct data signal transmission.

[0089] In other embodiments, the second Ethernet transceiver 1141 can also perform protocol conversion on the externally input signal, converting it into a signal of a certain protocol that the Ethernet switching chip 1142 can receive, and then transmit the above signal to the central processing unit 121 through the Ethernet switching chip 1142 with network communication function and the second network card chip 122.

[0090] In some embodiments, refer to Figure 2 and Figure 5 The second Ethernet transceiver 1141 uses the domestic YT8521SH chip from Yutai Chetong, and the Ethernet switching chip 1142 uses the SF2507 5+2 high-performance switching chip from Nanfei Microelectronics.

[0091] The YT8521SH chip supports conversion between RGMII and 1000BASE-X interfaces, while the SF2507 chip supports conversion between RGMII and 1000BASE-T interfaces. Figure 2 As shown, the second network card chip 122 is connected to one end of the Ethernet switching chip 1142 through two 1000BASE-T channels. The other end of the Ethernet switching chip 1142 is connected to the second Ethernet transceiver 1141 through RGMIIx2. The second Ethernet transceiver 1141 then receives external input signals or commands by connecting to 1000BASE-X. Specifically, it can be used to connect to terminals of other circuit boards, such as the rear output terminal 05 on the back panel.

[0092] It is understandable that the communication protocol corresponding to the path where the RGMII interface is located is RGMII, the interface specification corresponding to the path where 1000BASE-T is located is 1000BASE-T, and the interface specification corresponding to the path where 1000BASE-X is located is 1000BASE-X.

[0093] In some embodiments, refer to Figure 2 The core board also has other signal lines connected to the central processing unit 121, such as: signal lines for transmitting the PCIE_CLK and PCIE_RSTn signals. PCIE_CLK can represent the clock signal in the PCIE protocol, and PCIE_RSTn can represent the reset signal in the PCIE protocol; there are also signal lines for the RGMII and MDIO interfaces, the CAN and I2C interfaces, the SPI and GPIO interfaces, and the UART interface; there is also a signal line for transmitting the SYS_RSTn signal, which can represent the system reset signal. The above-mentioned signals are all conventional signals, and their functions will not be described in detail here.

[0094] In some embodiments, refer to Figure 3 The core board 120 is also provided with a first connector 125; the core board 120 and the carrier board 110 are connected through the first connector 125.

[0095] For example, the first connector 125 may be of model number JL121-100TJM03.

[0096] In some embodiments, refer to Figure 2 The core board 120 is also connected to the backplane rear output terminal 05 (hereinafter referred to as backplane rear output) via a UART interface to communicate with external devices through the backplane rear output terminal 05.

[0097] In some embodiments, refer to Figure 2 The carrier board 110 also includes a second connector 115 and an external communication component; the external communication component is used to provide the carrier board 110 with external devices (not shown) for exchanging signals, data, etc.

[0098] For example, the second connector 115 may be a VPX connector from Factory 158, which may be model C1410187-3, VPX20-1132-0001 or C1410189-3.

[0099] The carrier board 110 is connected to an external device via a second connector 115. Specifically, based on the connection established between the carrier board 110 and the external device, the carrier board 110 and the external device can exchange various forms of signals through the external communication component, including but not limited to optical signals and electrical signals. The form of the signals transmitted by the external communication component can be set according to actual interaction requirements, and is not limited here.

[0100] In some embodiments, refer to Figure 2 The external communication components include an optical module 1161, an electrical module 1162, and a signal transmission line 1163; the optical module 1161, the electrical module 1162, and the signal transmission line 1163 are respectively connected between the field programmable gate array 111 and the second connector 115.

[0101] Among them, optical module 1161 is used to transmit 10 Gigabit optical signals. For example, optical module 1161 can be a Zhonghang Haixin optical module, model HTG8506, which has 4 10G-SFI interfaces exposed to the outside. Electrical module 1162 is used to transmit gigabit electrical signals. For example, electrical module 1162 can be a YT8521SH(x2) chip, which has 4 1000BASE-T interfaces exposed to the outside and an SGMII interface exposed to the field programmable gate array 111.

[0102] For example, the signal direct transmission line 1163 can directly transmit 4xSRIO×4 compatible 10G-KRx4 signals, or directly transmit other forms of signals. The signals transmitted by the signal direct transmission line 1163 are all conventional signals, and their functions and forms will not be described in detail here.

[0103] In some embodiments, refer to Figure 2 The carrier board 110 also includes an IPMI module 117; the IPMI module 117 is connected to an external device and the baseboard via a second connector 115.

[0104] In addition, in the actual circuit design, the carrier board 110 is also equipped with a power conversion chip (not shown in the figure). Based on this, external devices can input power signals to the carrier board 110 through the second connector 115 to supply power to it. Then the power conversion chip converts the voltage of the power signal into the voltage applicable to each component on the carrier board 110 to meet the voltage requirements of the relevant components.

[0105] For example, the voltage of the power signal may be 12V, and the voltage applicable to each component may include 8V, 6V or other voltages, which are not limited herein.

[0106] It is understandable that the IPMI module 117 is used to monitor and manage the health status of the carrier board 110, including but not limited to monitoring the operating parameters of the carrier board 110 such as temperature, voltage, and current, and sending the monitored operating parameters to the baseboard and external devices. In this way, the baseboard and external devices can further determine whether the carrier board 110 is working properly, and when it is determined that the carrier board 110 is abnormal, they can take relevant measures in a timely manner according to preset rules to prevent the problem from worsening.

[0107] Based on the above embodiments, this disclosure also provides a general protocol processing board system, including a baseboard and any of the general protocol processing boards provided in the above embodiments; the general protocol processing board is connected to the baseboard.

[0108] Compared to existing general-purpose protocol processing boards that are limited by imported components, the general-purpose protocol processing board provided in this disclosure adopts a fully domestically selected design for both the core board and the carrier board, and is equipped with fully domestically produced components. This enables an independent and self-reliant fully domestically produced general-purpose protocol processing board, meets the information security requirements of the industrial field, and reduces the risk of information leakage.

[0109] In some embodiments, multiple general protocol processing boards are located on the base plate.

[0110] For example, the base plate may be provided with two, three or other numbers of general protocol processing boards to meet the (task) processing requirements of the general protocol processing board system.

[0111] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0112] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A universal protocol processing board, characterized in that, include: A carrier board and multiple core boards; the core boards include a central processing unit, and the carrier board includes a field-programmable gate array and multiple inter-board communication components; The central processing unit of each core board is connected to the field-programmable gate array via an inter-board communication component. The field-programmable gate array is used at least to forward a preset number of signals to be processed to each of the central processing units via the inter-board communication components; the central processing unit is used at least to perform protocol conversion on the received signals to be processed.

2. The universal protocol processing board according to claim 1, characterized in that, The inter-board communication component includes: a first network interface card chip and a first Ethernet transceiver; One end of the first network interface card chip and the first Ethernet transceiver are both connected to the central processing unit, and the other end of the first network interface card chip and the first Ethernet transceiver are both connected to the field-programmable gate array.

3. The universal protocol processing board according to claim 1, characterized in that, The carrier board also includes multiple carrier board storage chips; Multiple carrier memory chips are respectively connected to the field-programmable gate array.

4. The universal protocol processing board according to claim 3, characterized in that, The multiple carrier board memory chips include DDR3 chips and SRAM chips.

5. The universal protocol processing board according to claim 1, characterized in that, The core board also includes a second network card chip, multiple core board storage chips, and a power-on / off control module. The second network interface card chip and the multiple core board storage chips are respectively connected to the central processing unit; the second network interface card chip, the central processing unit, and the multiple core board storage chips are all connected to the power-on / off control module.

6. The universal protocol processing board according to claim 5, characterized in that, The core board's storage chips include EEPROM chips, DDR4 chips, SSD chips, and FLASH chips.

7. The universal protocol processing board according to claim 5, characterized in that, The power-on / off control module includes a CPLD chip.

8. The universal protocol processing board according to claim 5, characterized in that, The carrier board also includes network management components; Each of the core boards is connected to the network management component.

9. The universal protocol processing board according to claim 8, characterized in that, The network management component includes a second Ethernet transceiver and an Ethernet switching chip; The second Ethernet transceiver is connected to the central processing unit in sequence through the Ethernet switching chip and the second network interface card chip.

10. A universal protocol processing board system, characterized in that, Includes a base plate and a general protocol processing board as described in any one of claims 1-9; The general protocol processing board is connected to the base plate.

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