Printed circuit board (PCB) structure for embedding device
By encapsulating the chip before manufacturing and designing an anti-static structure on the PCB board, the problem of high cost of electrostatic protection is solved, enabling low-cost and high-reliability electronic device production.
Patent Information
- Application Number
- CN202423141193.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-12-19
AI Technical Summary
Existing PCB boards have high electrostatic discharge (ESD) protection costs during manufacturing, testing, storage, transportation, and assembly, resulting in a high risk of damage to electronic components, and the cost of modification is also high.
Before chip manufacturing, a molding process is performed to form a molding layer. An isolation layer and a copper foil layer are then set on the PCB board. Conductive pins and conductive components are designed to achieve anti-static function and simplify subsequent processing.
It reduces the cost of electrostatic discharge protection, improves the reliability of chips and products embedded in printed circuit boards, reduces production costs, and simplifies mass production.
Smart Images
Figure CN223798402U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of PCB board manufacturing technology, and in particular to a PCB board structure for embedding components. Background Technology
[0002] Currently, the core technologies of new energy vehicles are the motor drive system and the battery, which has generated a huge market demand for power electronic devices. Driven by this huge market, there is a growing demand for new power electronic devices with increasingly higher power density and lower costs. A key product direction for embedded technology is to embed power chips into printed circuit boards, achieving the packaging and integration of power electronic devices and modules.
[0003] Power electronic devices based on the embedded process of printed circuit boards (PCBs) have significant advantages such as low cost, low loss, and good heat dissipation (double-sided heat dissipation), and are very likely to become the next generation of advanced packaging technology solutions.
[0004] Power electronic chips are electrostatically sensitive products, highly susceptible to damage from static electricity in the environment. The existing packaging industry requires strict hardware and software measures to control static electricity and minimize its impact during manufacturing, testing, storage, transportation, and assembly processes, encompassing equipment, materials, and operators. Printed circuit board (PCB) factories must invest heavily in environmental protection, process protection, and personnel protection to control their ESD levels. This involves not only high initial investment costs but also substantial operating and maintenance costs.
[0005] To reduce the cost of electrostatic protection during the manufacturing process of embedding electronic components in PCB boards, this solution improves the structure of the PCB board and proposes a PCB board structure for component embedding. Utility Model Content
[0006] The purpose of this invention is to reduce the electrostatic discharge (ESD) protection cost in the manufacturing process of embedding electronic components into PCB boards, thereby improving the structure of the PCB board. The specific improvement scheme is as follows:
[0007] A PCB structure for embedding devices includes a copper-clad laminate (CCL), with a window in the CCL containing a chip. An upper isolation layer is provided on the upper surface of the CCL, and a lower isolation layer is provided on the lower surface. A first copper foil layer is provided on the upper surface of the upper isolation layer, and a second copper foil layer is provided on the lower surface of the lower isolation layer. The chip includes a core, an upper insulating layer covering the upper surface of the core, and a lower insulating layer covering the lower surface of the core. A gap is provided between the chip and the window, and the upper and lower isolation layers are interconnected through the gap. Multiple pins are provided on the upper and lower surfaces of the core. Each upper pin has a conductive pin that passes sequentially through the upper insulating layer and the upper isolation layer and is electrically connected to the first copper foil layer. Each lower pin has a conductive pin that passes sequentially through the lower insulating layer and the lower isolation layer and is electrically connected to the second copper foil layer. The copper-clad laminate is also provided with a through-conductor running vertically. The middle part of the through-conductor is electrically connected to the copper foil layer of the copper-clad laminate. The upper end of the through-conductor passes through the upper isolation layer and enters the first copper foil layer and is electrically connected to it. The lower end of the through-conductor passes through the lower isolation layer and enters the second copper foil layer and is electrically connected to it.
[0008] Furthermore, the copper-clad laminate is a double-layer copper-clad laminate, consisting of upper and lower copper foil surfaces and a substrate sandwiched between the upper and lower copper foil surfaces.
[0009] Furthermore, the thickness of the copper-clad laminate is 0.2-0.25 mm.
[0010] Furthermore, both the upper and lower isolation layers are adhesive sheets.
[0011] Furthermore, the thickness of the adhesive sheet is 65-100 μm.
[0012] Furthermore, the size of the window is at least 0.1 mm larger than one side of the chip.
[0013] Furthermore, both the upper and lower insulating layers are molding layers with a thickness of 20-40 μm.
[0014] Furthermore, the core is cut from a wafer with a thickness of 0.2 mm.
[0015] Furthermore, the conductive pin is a copper-plated blind hole with a diameter of 0.102-0.152 mm.
[0016] Furthermore, the conductive element is a copper-plated through hole with a diameter of 0.4-1.0 mm.
[0017] In summary, the technical solution of this utility model has the following beneficial effects:
[0018] This solution proposes a PCB structure for embedded devices. First, the chip is pre-encapsulated (i.e., has a molding layer) before embedding, providing anti-static properties. No further anti-static modifications are needed in subsequent PCB fabrication processes; existing equipment and mature technologies can meet the requirements. Second, this novel structure and process incorporates anti-static design before chip embedding, maximizing the reliability of the chip's functionality and thus improving the overall reliability of the product after embedding. Finally, compared to traditional chip embedding PCB solutions, this approach is lower in cost, easier to implement, and simpler for mass production.
[0019] This solution emphasizes that the wafer is first encapsulated in plastic before the chip is embedded in the PCB board. Then, the encapsulated wafer is divided into multiple chips, and the encapsulated chips are then embedded in the printed circuit board. The structural principle of this solution can be applied to various PCB board production and processing applications for embedded devices, thereby forming a highly reliable, mature, and low-cost production method for electronic devices. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of a PCB board structure for embedding devices according to the present invention.
[0022] Explanation of reference numerals in the attached figures:
[0023] 10-Copper clad laminate, 11-Window, 12-Copper foil layer, 13-Substrate, 20-Chip, 21-Core, 22-Upper insulating layer, 23-Lower insulating layer, 30-Upper isolation layer, 31-Lower isolation layer, 40-First copper foil layer, 41-Second copper foil layer, 50-Conductive pin, 60-Conductive component. Detailed Implementation
[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the scope of protection of the present utility model.
[0025] like Figure 1As shown, a PCB structure for embedding devices includes a copper-clad laminate 10, with a window 11 in the copper-clad laminate 10, and a chip 20 disposed in the window 11. An upper insulating layer 30 is disposed on the upper surface of the copper-clad laminate 10, and a lower insulating layer 31 is disposed on the lower surface of the copper-clad laminate 10. A first copper foil layer 40 is disposed on the upper surface of the upper insulating layer 30, and a second copper foil layer 41 is disposed on the lower surface of the lower insulating layer 31. The chip 20 includes a core 21 in the middle, an upper insulating layer 22 wrapped around the upper surface of the core 21, and a lower insulating layer 23 wrapped around the lower surface of the core 21. A gap is provided between the chip 20 and the window 11, and the upper insulating layer 30 and the lower insulating layer 31 are interconnected through the gap. The core 21 has multiple pins (not shown in the figure) on its upper and lower surfaces. Each upper pin has a conductive foot 50 that passes through the upper insulating layer 22 and the upper isolation layer 30 and is electrically connected to the first copper foil layer 40. Each lower pin has a conductive foot 50 that passes through the lower insulating layer 23 and the lower isolation layer 31 and is electrically connected to the second copper foil layer 41. The copper clad laminate 10 also has a through-type conductor 60. The middle part of the conductor 60 is electrically connected to the copper foil layer 12 of the copper clad laminate 10. The upper end of the conductor 60 passes through the upper isolation layer 30 and enters the first copper foil layer 40 and is electrically connected to it. The lower end of the conductor 60 passes through the lower isolation layer 31 and enters the second copper foil layer 41 and is electrically connected to it.
[0026] Preferably, the copper clad laminate 10 is a double-layer copper clad laminate, consisting of upper and lower copper foil surfaces (that is, two copper foil layers 12) and a substrate 13 sandwiched between the upper and lower copper foil surfaces.
[0027] Optionally, the thickness of the copper clad laminate 10 is 0.2-0.25 mm.
[0028] Specifically, both the upper insulating layer 30 and the lower insulating layer 31 are adhesive sheets. Adhesive sheets have the advantage of serving both adhesive and insulating purposes.
[0029] Specifically, the thickness of the adhesive sheet is 65-100 μm.
[0030] Specifically, the size of window 11 is at least 0.1 mm larger than the chip 20 on one side.
[0031] Specifically, both the upper insulating layer 22 and the lower insulating layer 23 are molding layers with a thickness of 20-40 μm.
[0032] Specifically, the core 21 is cut from a wafer with a thickness of 0.2 mm. A wafer refers to a silicon wafer used to fabricate silicon semiconductor circuits; this is existing technology, and specific details will not be elaborated here.
[0033] Specifically, conductive pin 50 is a copper-plated blind via with a diameter of 0.102-0.152 mm. The number of copper-plated blind vias depends on the specific product requirements and is not limited.
[0034] Specifically, the conductive element 60 is a copper-plated through hole with a diameter of 0.4-1.0 mm. The number of copper-plated through holes depends on the specific product requirements and is not limited.
[0035] The manufacturing process of this structure is briefly described below:
[0036] (1) Wafer molding:
[0037] A molding compound is used to encapsulate the wafer by adding molding compound. The molding compound wraps around the chip and provides insulation protection, preventing electrostatic discharge from damaging the chip. The molding compound is a powdered molding compound made of epoxy resin as the base resin, high-performance phenolic resin as the curing agent, silicon micropowder and other fillers, and various additives. This is existing technology.
[0038] (2) Wafer dicing:
[0039] A dedicated wafer dicing machine is used to dic the encapsulated wafer into chips 20.
[0040] (3) Fabricate a PCB board and embed chip 20 inside the PCB board:
[0041] The first step is to use a copper-clad laminate 10 to create a window 11 at the location where the chip 20 needs to be embedded. The size of the window 11 is at least 0.1 mm larger than the chip 20 on one side. The window 11 of the copper-clad laminate 10 is generally processed by four methods: mechanical milling, mechanical drilling, die punching, and UV laser milling.
[0042] The second step is to apply a type of tape to one side (i.e. the bottom) of the copper-clad laminate 10 of the window 11, and then place the chip 20 inside the window 11. Anti-static treatment is required during the placement of the chip 20.
[0043] The third step is to attach an adhesive sheet (i.e., to create an isolation layer 30) above the chip 20 and the copper-clad laminate 10. The fast pressing pre-pressing step is completed in the press, and the chip 20 is pre-adheded onto the adhesive sheet. After the pre-pressing is completed, anti-static treatment is required.
[0044] After the fourth step of pre-pressing is completed, the tape is removed. Anti-static treatment is required during the process. An adhesive sheet (i.e., the lower isolation layer 31) is placed under the chip 20 and the copper-clad laminate 10, and a second copper foil layer 41 is placed under the adhesive sheet and then pressed together.
[0045] The fifth step involves placing a first copper foil layer 40 on the upper side of the adhesive sheet on the chip 20 and the copper clad laminate 10, and then performing a lamination process.
[0046] (4) Signal output from chip 20 and electrical connections of each layer:
[0047] After chip 20 is embedded in the PCB board, laser-drilled blind vias (i.e., conductive pins 50) need to be fabricated at the location of chip 20 to bring out the signal. Simultaneously, through-holes (i.e., conductive elements 60) and circuit patterns (not shown in the diagram) are fabricated on the PCB board to bring out the entire signal from chip 20. Laser-drilled blind vias are typically created by burning through the insulating layers above or below chip 20 (referring to upper insulating layer 22 and lower insulating layer 23) using a pulsed CO2 laser, exposing chip 20. Both laser-drilled blind vias and through-holes require electroplating with copper. In subsequent PCB board processing, each production step requires anti-static treatment to prevent the chip from being damaged by electrostatic discharge; these are existing technologies and will not be elaborated upon here.
[0048] In summary, the technical solution of this utility model has the following beneficial effects:
[0049] This solution proposes a PCB structure for embedded devices. First, the chip is pre-encapsulated (i.e., has a molding layer) before embedding, providing anti-static properties. No further anti-static modifications are needed in subsequent PCB fabrication processes; existing equipment and mature technologies can meet the requirements. Second, this novel structure and process incorporates anti-static design before chip embedding, maximizing the reliability of the chip's functionality and thus improving the overall reliability of the product after embedding. Finally, compared to traditional chip embedding PCB solutions, this approach is lower in cost, easier to implement, and simpler for mass production.
[0050] This solution emphasizes that the wafer is first encapsulated in plastic before the chip is embedded in the PCB board. Then, the encapsulated wafer is divided into multiple chips, and the encapsulated chips are then embedded in the printed circuit board. The structural principle of this solution can be applied to various PCB board production and processing applications for embedded devices, thereby forming a highly reliable, mature, and low-cost production method for electronic devices.
[0051] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.
Claims
1. A PCB board structure for embedding components, characterized in that: The system includes a copper-clad laminate (CCL), which has a window containing a chip. The upper surface of the CCL has an upper insulating layer, and the lower surface has a lower insulating layer. The upper surface of the upper insulating layer has a first copper foil layer, and the lower surface of the lower insulating layer has a second copper foil layer. The chip includes a core, an upper insulating layer covering the upper surface of the core, and a lower insulating layer covering the lower surface of the core. A gap exists between the chip and the window, and the upper and lower insulating layers are interconnected through this gap. Multiple pins are located on the upper and lower surfaces of the core. Each upper pin has a conductive foot that passes through the upper insulating layer and the upper isolation layer in sequence and is electrically connected to the first copper foil layer. Each lower pin has a conductive foot that passes through the lower insulating layer and the lower isolation layer in sequence and is electrically connected to the second copper foil layer. The copper-clad laminate also has a through-type conductor. The middle part of the conductor is electrically connected to the copper foil layer of the copper-clad laminate. The upper end of the conductor passes through the upper isolation layer and enters the first copper foil layer and is electrically connected to it. The lower end of the conductor passes through the lower isolation layer and enters the second copper foil layer and is electrically connected to it.
2. The PCB board structure for device embedding according to claim 1, characterized in that: The copper-clad laminate is a double-layer copper-clad laminate, consisting of upper and lower copper foil surfaces and a substrate sandwiched between the upper and lower copper foil surfaces.
3. The PCB board structure for device embedding according to claim 1, characterized in that: The thickness of the copper-clad laminate is 0.2-0.25 mm.
4. The PCB board structure for device embedding according to claim 1, characterized in that: Both the upper and lower isolation layers are adhesive sheets.
5. The PCB board structure for device embedding according to claim 4, characterized in that: The thickness of the adhesive sheet is 65-100 μm.
6. The PCB board structure for device embedding according to claim 1, characterized in that: The size of the window is at least 0.1 mm larger than one side of the chip.
7. The PCB board structure for device embedding according to claim 1, characterized in that: Both the upper and lower insulating layers are molding layers with a thickness of 20-40 μm.
8. The PCB board structure for device embedding according to claim 1, characterized in that: The core is cut from a wafer with a thickness of 0.2 mm.
9. The PCB board structure for device embedding according to claim 1, characterized in that: The conductive pin is a copper-plated blind hole with a diameter of 0.102-0.152 mm.
10. A PCB board structure for device embedding according to claim 1, characterized in that: The conductive component is a copper-plated through hole with a diameter of 0.4-1.0 mm.