Semiconductor element

Abstract

The embodiment of the utility model provides a semiconductor element. The semiconductor element may include a substrate, a first channel region and a second channel region on the substrate, a gate structure on one or more sidewalls of the first channel region and on one or more sidewalls of the second channel region, and dielectric spacers on first and second sides of the gate structure in a top view. The first side edge is opposite to the second side edge. The first portion of the dielectric spacer may extend between the first channel region and the second channel region.

Description

Technical Field

[0001] This utility model relates to a semiconductor element. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern each material layer to form integrated circuit components and their parts.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] According to one embodiment of the present invention, a semiconductor device is provided, comprising a substrate, a first channel region and a second channel region, a gate structure, and a dielectric spacer. The first channel region and the second channel region are located above the substrate. The gate structure is located on one or more sidewalls of the first channel region and one or more sidewalls of the second channel region. The dielectric spacer is located on a first side and a second side of the gate structure in a top view. The first side and the second side are opposite to each other. A first portion of the dielectric spacer extends between the first channel region and the second channel region.

[0005] According to another embodiment of the present invention, a semiconductor device is provided, comprising: a substrate; a first channel region above the substrate; a gate structure, wherein the gate structure is located on the upper surface and / or multiple sidewalls of the first channel region; and an insulating spacer. In a top view, a first portion of the insulating spacer is located on a first side of the gate structure, and a second portion of the insulating spacer is located on a second side of the gate structure. The first side and the second side are opposite to each other. In the top view, a third portion of the insulating spacer extends through the gate structure, and wherein the third portion of the insulating spacer contacts the first and second portions of the insulating spacer.

[0006] According to another embodiment of the present invention, a semiconductor device is provided, comprising a substrate, a first channel region and a second channel region, a gate structure, a dielectric spacer, and a dielectric layer. The first channel region and the second channel region are above the substrate. The gate structure is located on one or more sidewalls of the first channel region and one or more sidewalls of the second channel region. In a top view, the dielectric spacer is located on a first side and a second side of the gate structure. The first side and the second side are opposite to each other. A first portion of the dielectric spacer extends between the first channel region and the second channel region. The dielectric layer is located on the first side of the first channel region. The first portion of the dielectric spacer is on the dielectric layer. The gate structure is on the second side of the first channel region, and the first side and the second side are opposite to each other. Attached Figure Description

[0007] When with the attached Figure 1 When reading this work, the various solutions disclosed in the embodiments of this utility model can be best understood from the following detailed description. It should be noted that, according to general industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 Examples of nanostructure field-effect transistors (nano-FETs) according to some implementations are shown in three-dimensional view;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 21 It is a view of a semiconductor device (e.g., nano-FET) at an intermediate stage of manufacturing based on some implementations;

[0010] Figure 22 and Figure 23 A cross-sectional view of a fin field-effect transistor (FET) according to some embodiments is shown;

[0011] Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 26A , Figure 26B , Figure 26C , Figure 26D and Figure 27 It is a view of a semiconductor device (e.g., a fin-FET) at an intermediate stage of manufacturing, based on some implementations;

[0012] Figure 28 and Figure 29 A cross-sectional view of a finned FET according to some embodiments is shown.

[0013] [Symbol Explanation]

[0014] 20: Separator

[0015] 50:Substrate

[0016] 50P:p-type area

[0017] 50N: n-type region

[0018] 51, 51A, 51B, 51C: First semiconductor layer

[0019] 52, 52A, 52B, 52C: First nanostructure

[0020] 53, 53A, 53B, 53C: Second semiconductor layer

[0021] 54, 54A, 54B, 54C: Second nanostructures

[0022] 55: Nanostructures

[0023] 64: Multi-layer stacking

[0024] 66: Fin

[0025] 68: Shallow trench isolation area

[0026] 70: Virtual dielectric layer

[0027] 71: Virtual gate dielectric

[0028] 72: Virtual Gate Layer

[0029] 73: Gap

[0030] 74: Masking layer

[0031] 76: Virtual Gate

[0032] 78: Mask

[0033] 80: Spacer layer

[0034] 81: Spacer

[0035] 86: Groove

[0036] 88: Side wall depression

[0037] 90: First internal spacer

[0038] 92: Epitaxial source / drain region

[0039] 92A: First liner layer

[0040] 92B: Second liner layer

[0041] 92C: Filler layer

[0042] 94: Contact Etching Stop Layer

[0043] 96: First interlayer dielectric

[0044] 98: Third Groove

[0045] 100: Gate dielectric layer

[0046] 102: Gate electrode

[0047] 104: Gate Mask

[0048] 106: Interlayer dielectric

[0049] 108: Fourth Groove

[0050] 110: First silicide region

[0051] 112: Source / Drain Contact

[0052] 114: Gate contact

[0053] A-A', B-B', C-C', D-D': Reference cross-sections

[0054] H1, H2: Height

[0055] W1, W2: Width Detailed Implementation

[0056] The following disclosure provides many different embodiments or examples to implement various features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these are merely embodiments and are not intended to limit the embodiments of the present invention. For example, if the following disclosure describes forming a first feature on or above a second feature, it indicates that it includes embodiments where the formed first and second features are in direct contact, and it may also include embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, this specification may use repeated symbolic elements and / or letters in various embodiments. Such repetition is for simplification and clarity and is not in itself intended to limit the relationship between the various embodiments and / or configurations discussed.

[0057] Furthermore, to facilitate the description of the relationship between one element or feature in the accompanying drawings and another element(s) or feature(s), spatially related terms such as "below," "under," "lower," "above," and "upper" may be used in this specification. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptive symbols used in this specification may be interpreted accordingly.

[0058] Various embodiments provide semiconductor devices and methods for their fabrication. For example, some embodiments provide nano-FETs and fin-FETs, allowing selection of appropriate materials for forming the dummy gate during their fabrication. As results show, improved control of the gate electrode over the channel region can be achieved in nano-FETs and fin-FETs, thereby enhancing the performance of nano-FETs and fin-FETs.

[0059] Some embodiments discussed in this specification are described in the context of semiconductor devices including nano-FETs. However, various embodiments can be applied to other types of transistors (e.g., fin-FETs, vertical field-effect transistors (VFETs), complementary field-effect transistors (CFETs), planar transistors, etc.) to replace or combine with nano-FETs.

[0060] Figure 1 An example of a nano-FET (e.g., nanowire FET, nanosheet FET, etc.) is shown in a three-dimensional view. The nano-FET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nano-FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66 and may protrude above and between adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer solely to a semiconductor substrate or to a combination of a semiconductor substrate and a shallow trench isolation region. Additionally, although the bottom portion of the fin 66 is shown as being a single, continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this specification, fin 66 refers to the portion extending between adjacent shallow trench isolation regions 68. The gate dielectric layer 100 is located above the upper surface of the fin 66 and along the upper surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0061] Figure 1The reference cross sections used in the following figures are further illustrated. Reference cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Reference cross section B-B' is parallel to reference cross section A-A' and extends through the epitaxial source / drain regions 92 of the multiple nano-FETs. Reference cross section C-C' is perpendicular to reference cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nano-FET and along, for example, the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. For clarity, the following figures refer to these reference cross sections. Some embodiments discussed in this specification are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate schemes used in planar devices, such as planar FETs or in fin-FETs.

[0062] Figures 2 to 21 It is a view of the intermediate stages in the manufacturing of some implementations of semiconductor devices (such as nano-FETs). Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21 It shows along Figure 1 The cross-sectional view of the reference cross section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B It shows along Figure 1The cross-sectional view of the reference cross section B-B' is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 11D , Figure 12C , Figure 12E , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C It shows along Figure 1 The cross-sectional view of the reference cross section C-C' is shown.

[0063] exist Figure 2 The diagram provides a substrate 50. Substrate 50 can be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide; or combinations thereof.

[0064] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, for example, n-type nano-FETs, and the p-type region 50P can be used to form p-type devices, such as PMOS transistors, for example, p-type nano-FETs. The n-type region 50N and the p-type region 50P can be physically separated (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although only one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0065] In addition, Figure 2 In this embodiment, a multilayer stack 64 is formed above the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layer 53). For illustrative purposes and in more detail below, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form channel regions for nano-FETs in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions for nano-FETs in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions for nano-FETs in the p-type region 50P. In some embodiments, the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of a nano-FET in the n-type region 50N, and the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form a channel region of a nano-FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of a nano-FET in both the n-type region 50N and the p-type region 50P.

[0066] For illustrative purposes, the multilayer stack 64 shows a first semiconductor layer 51 and a second semiconductor layer 53, each comprising three layers. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (such as silicon-germanium), and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material (such as silicon, carbon-doped silicon, etc.).

[0067] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. Thus, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nano-FET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nano-FET.

[0068] exist Figure 3 In some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutron beam etching (NBE), or combinations thereof. Etching can be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 can also define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) from first semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0069] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, one or more lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fin 66 and nanostructure 55. Generally, dual-patterning or multi-patterning processes combine lithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0070] For illustrative purposes, Figure 3 Fins 66 with substantially equal widths are shown in the n-type region 50N and the p-type region 50P. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, although each fin 66 and nanostructure 55 is shown to always have a consistent width, in other embodiments, the fin 66 and / or nanostructure 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 increases continuously in the direction toward the substrate 50. In these embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0071] exist Figure 4In this embodiment, a shallow trench isolation region 68 is formed adjacent to the fin 66. The shallow trench isolation region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof. Other insulating materials can be formed using any acceptable process. In the illustrated embodiment, the insulating material is silicon oxide formed via an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a pad (not shown separately) can be formed first along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Thus, a filler material, such as that discussed above, can be formed over the pad.

[0072] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back, combinations thereof, or similar processes, can be used. The planarization process exposes the nanostructure 55 so that the upper surfaces of the nanostructure 55 and the insulating material are substantially coplanar or flush after the planarization process is completed.

[0073] Next, the insulating material is recessed to form shallow trench isolation regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude between adjacent shallow trench isolation regions 68. Furthermore, the upper surface of the shallow trench isolation regions 68 can have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof, as shown. The upper surface of the shallow trench isolation regions 68 can be formed into a planar, convex, and / or concave surface by appropriate etching. The shallow trench isolation regions 68 can be recessed using acceptable etching processes, such as etching processes selectively applied to the insulating material (e.g., etching the insulating material at a faster rate than that applied to the fins 66 and nanostructures 55). For example, an oxide of dilute hydrofluoric acid can be used for removal.

[0074] The above reference Figures 2 to 4The described process is one embodiment of how the fin 66 and nanostructure 55 are formed. In some embodiments, a masking and epitaxial growth process can be used to form the fin 66 and / or nanostructure 55. For example, a dielectric layer can be formed above the upper surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structures can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material can be doped in situ during growth, which can avoid prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0075] Furthermore, for illustrative purposes, the first semiconductor layer 51 (and the obtained first nanostructure 52) and the second semiconductor layer 53 (and the obtained second nanostructure 54) shown and discussed in this specification contain the same material in the p-type region 50P and the n-type region 50N. In some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0076] In addition, Figure 4 In this embodiment, suitable wells (not shown separately) can be formed in the fins 66, nanostructures 55, and / or shallow trench isolation regions 68. In embodiments with different well types, different implantation steps for the n-type region 50N and for the p-type region 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over the fins 66 and shallow trench isolation regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in the region at a concentration of approximately 10. 13 atoms per square centimeter (atoms / cm) 3 ) to about 10 14 Atoms per square centimeter. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0077] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in the region at a concentration of approximately 10. 13 atoms / square centimeter to approximately 10 14 Atoms per square centimeter. After implantation, the photoresist can be removed, for example, by an acceptable ashing process. After implantation in the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, although in-situ doping and implantation doping can be used together.

[0078] exist Figure 5 In the process, a virtual dielectric layer 70 is formed on the fin 66 and / or nanostructure 55, a virtual gate layer 72 is formed above the virtual dielectric layer 70, and a masking layer 74 is formed above the virtual gate layer 72. The virtual dielectric layer 70 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown using appropriate processes. For illustrative purposes, Figure 5 The diagram shows a virtual dielectric layer 70 covering the fin 66 and nanostructure 55. In some embodiments, the virtual dielectric layer 70 may be deposited such that it also covers the shallow trench isolation region 68 and extends between the virtual gate layer 72 and the shallow trench isolation region 68.

[0079] A dummy gate layer 72 can be deposited over a dummy dielectric layer 70 and then planarized, for example, by CMP. The dummy gate layer 72 can be formed of a material with high etch selectivity relative to the material of the shallow trench isolation region 68. The dummy gate layer 72 can be formed of polysilicon or the like. The dummy gate layer 72 can be deposited using a suitable deposition process, such as physical vapor deposition (PVD), CVD, sputtering deposition, etc. The deposition temperature can be from about 500°C to about 700°C, and the deposition pressure can be from about 0.1 torr to about 0.5 torr.

[0080] After forming the dummy gate layer 72, gaps 73 can be provided in the dummy gate layer 72. For illustrative purposes, Figure 5A gap 73 is shown in an n-type region 50N and a gap 73 is shown in a p-type region 50P. The n-type region 50N and / or the p-type region 50P may each have more than one gap 73. For illustrative purposes, Figure 5 The vertical position of the void 73 adjacent to the second nanostructure 54A is shown. The vertical position of the void 73 can be anywhere in the virtual gate layer 72, including positions adjacent to the top portions of other nanostructures in nanostructure 55 and / or fins 66. For illustrative purposes, Figure 5 The horizontal position of the gap 73 between the two stacks of nanostructure 55 is shown. The horizontal position of the gap 73 can be any position in the dummy gate layer 72, including the left and / or right sides of the two stacks of nanostructure 55. For illustrative purposes, Figure 5 A gap 73 with a semi-elliptical shape is shown. The gap 73 can have any shape (e.g., a semi-circle).

[0081] In some embodiments, the void 73 contacts the dummy dielectric layer 70, which causes the dummy dielectric layer 70 to be partially covered and partially exposed by the dummy gate layer 72. Such embodiments may correspond to embodiments using polysilicon to form the dummy gate layer 72, and as... Figures 5 to 21 The embodiments described. In some embodiments, the void 73 is surrounded by a dummy gate layer 72, which can completely cover the dummy dielectric layer 70 with the dummy gate layer 72. Such embodiments may correspond to embodiments using amorphous silicon to form the dummy gate layer 72, and will be referred to later. Figures 24A to 27 A more detailed description follows. The void 73 can be at least partially filled during subsequent processes. A masking layer 74 can be deposited over the dummy gate layer 72. The masking layer 74 may include silicon nitride, silicon oxynitride, etc. In some embodiments, a single dummy gate layer 72 and a single masking layer 74 are formed across the n-type region 50N and the p-type region 50P.

[0082] Figures 6A to 21 Various additional steps in the fabrication of nano-FET devices according to some implementations are shown. Figures 6A to 21 Features of either or both of the n-type region 50N or the p-type region 50P are shown. Figures 6A to 6D In the middle, a mask 78, a virtual gate 76 and a virtual gate dielectric 71 are formed. Figure 6D It shows Figure 6A , Figure 6B and Figure 6C The top view of the structure (including the second nanostructure 54A) shown along the reference cross section D-D'. The dummy gate 76 and the dummy gate dielectric 71 can be collectively referred to as the dummy gate structure.

[0083] The mask layer 74 (see [reference]) can be processed using appropriate lithography and etching techniques. Figure 5 The mask 78 is patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70, using appropriate etching processes to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover the respective channel regions of the fins 66. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from its adjacent dummy gates 76. The dummy gates 76 can also have a length direction substantially perpendicular to the length direction of the respective fins 66. A gap 73 can contact a portion of the dummy gate dielectric 71 and can extend along a portion of the dummy gate dielectric 71, thus exposing a portion of the dummy gate dielectric 71. The gap 73 can extend through the corresponding dummy gate 76. The etching process used to form the dummy gates 76 can enlarge the gap 73.

[0084] exist Figures 7A to 7D In the middle, a spacer layer 80 is formed. Figure 7D It shows Figure 7A , Figure 7B and Figure 7C A top view of the structure (including the second nanostructure 54A) shown along reference cross section D-D'. Spacer layer 80 may be formed on the upper surface of the shallow trench isolation region 68; on the upper surface and sidewalls of the nanostructure 55 and the shield 78; and on the sidewalls of the fin 66, dummy gate 76, and dummy gate dielectric 71. Spacer layer 80 may also at least partially fill the voids 73 in the dummy gate 76. Figure 7D As shown, the first and second portions of the spacer layer 80 may extend on opposite sides of the dummy gate 76, and the third portion of the spacer layer 80 may extend through the dummy gate 76 and connect to the first and second portions of the spacer layer 80. The first, second, and third portions of the spacer layer 80 may form an H shape in the top view.

[0085] The spacer layer 80 can be a single layer of a single material or multiple sublayers of different materials with different etch rates. In some embodiments, the spacer layer 80 comprises two sublayers of different materials with different etch rates. The material of the spacer layer 80 can be selected from dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The spacer layer 80 can be formed by a suitable thermal oxidation process or a suitable deposition process (e.g., CVD, ALD, etc.). Figure 7A As shown, in some embodiments, the third portion of the spacer layer 80 that fills the void 73 can be semi-elliptical, with a height H1 of about 1 nm to about 30 nm and a width W1 of about 1 nm to about 30 nm.

[0086] In an embodiment where spacer 81 comprises two sublayers of different materials, implantation for lightly-doped source / drain (LDD) regions (not shown separately) can be performed after the formation of the first sublayer and before the formation of the second sublayer. Similar to the above... Figure 4 The implantation discussed herein can involve forming a mask, such as a photoresist, over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of a suitable type (e.g., p-type) into the exposed fin 66 and nanostructure 55 located in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have a doping density of approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The concentration of impurities. Annealing can be used to repair implant damage and activate impurities in the implant.

[0087] exist Figures 8A to 8C In this process, spacer layer 80 is patterned to form first spacer 81. Spacer 81 can be self-aligned in the subsequently formed source and drain regions and protects dummy gate dielectric 71 and dummy gate 76 in subsequent etching processes. Spacer layer 80 can be patterned by one or more suitable etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), etc. After one or more etching processes, spacer 81 can remain on the sidewalls of fin 66, nanostructure 55, mask 78, dummy gate 76, and dummy gate dielectric 71. (See reference...) Figure 7D The first, second, and third portions of the spacer layer 80 described herein may remain intact after one or more etching processes and may be referred to as the first, second, and third portions of spacer 81.

[0088] exist Figures 9A to 9C In some embodiments, a groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions can then be formed in the groove 86. The groove 86 can extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Figure 9BAs shown, the upper surface of the shallow trench isolation region 68 may be flush with the bottom surface of the groove 86. In some embodiments, the bottom surface of the groove 86 is located below the upper surface of the shallow trench isolation region 68, etc.

[0089] The groove 86 can be formed by etching the fin 66, nanostructure 55, and substrate 50 using anisotropic etching processes (such as RIE, NBE, etc.). Spacers 81 and masks 78 can shield portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the groove 86. Each layer of the nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching after the groove 86 reaches the desired depth.

[0090] exist Figures 10A to 10C In this process, the sidewall portion of the first nanostructure 52 exposed through the groove 86 is etched to form a sidewall recess 88. Although in Figure 10C The sidewall of the first nanostructure 52 adjacent to the sidewall recess 88 shown is straight; in some embodiments, the sidewall may be concave. The sidewall can be etched using a unidirectional etching process such as wet etching. In embodiments where the first nanostructure 52 comprises silicon, germanium, etc., and the second nanostructure 54 comprises silicon, silicon carbide, etc., the sidewall of the first nanostructure 52 can be etched using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0091] exist Figures 11A to 11D In this configuration, a first internal spacer 90 is formed in a sidewall recess 88. The first internal spacer 90 can serve as an isolation component between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions can be formed in a recess 86, and the first nanostructure 52 can be replaced by a corresponding gate structure.

[0092] The first internal spacer 90 can be passed through Figures 10A to 10C An internal spacer layer (not shown separately) is deposited on the structure shown, and then etched to form the internal spacer layer. The internal spacer layer can be deposited using a conformal deposition process, such as CVD, ALD, etc. The internal spacer layer can include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k value less than about 3.5. The internal spacer layer can then be etched using an anisotropic etching process such as RIE, NBE, etc., to form a first internal spacer 90. The first internal spacer 90 can be used to protect the subsequently formed source / drain regions during subsequent etching processes, such as etching processes for forming the gate structure.

[0093] Although the outer wall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the first internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54. While in Figure 11C The outer wall of the first inner spacer 90 shown is straight, but the outer wall of the first inner spacer 90 can be concave. As an example, Figure 11D An embodiment is shown in which the sidewall of the first nanostructure 52 is recessed, the outer sidewall of the first internal spacer 90 is recessed, and the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54.

[0094] exist Figures 12A to 12E In this embodiment, epitaxial source / drain regions 92 are formed in the groove 86. In some embodiments, the epitaxial source / drain regions 92 can apply stress to the second nanostructure 54, thereby improving performance. For example... Figure 12C As shown, epitaxial source / drain regions 92 are formed in the recess 86, such that each dummy gate 76 is disposed between each pair of adjacent epitaxial source / drain regions 92.

[0095] Epitaxial source / drain regions 92 in n-type regions 50N (e.g., NMOS regions) can be formed by masking p-type regions 50P (e.g., PMOS regions). Epitaxial growth of the epitaxial source / drain regions 92 is then performed within a recess 86 of the n-type region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 92 can have surfaces protruding from the respective upper surfaces of the nanostructures 55 and can have facets.

[0096] Epitaxial source / drain regions 92 in p-type regions 50P (e.g., PMOS regions) can be formed by masking n-type regions 50N (e.g., NMOS regions). Epitaxial growth of the epitaxial source / drain regions 92 is then performed within the recesses 86 of the p-type regions 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for p-type nano-FETs. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain regions 92 can comprise materials that apply compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or similar materials. The epitaxial source / drain regions 92 can have surfaces protruding from the individual surfaces of the fins 66 and can have facets.

[0097] Epitaxial source / drain regions 92, first nanostructure 52, second nanostructure 54, and / or substrate 50 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a size of approximately 1 × 10⁻⁶. 19 atoms / cm 3 Up to approximately 1×10 21 atoms / cm 3 The impurity concentration. The n-type and / or p-type impurities used in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0098] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has laterally extended faces that extend outward beyond the sidewalls of the nanostructure 55. In some embodiments, these faces result in the merging of adjacent epitaxial source / drain regions 92 within the same nano-FET, such as... Figure 12B As shown. In some implementations, such as Figure 12D As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Figure 12B and Figure 12D In the illustrated embodiment, spacer 81 can be formed on the upper surface of the shallow trench isolation region 68, thereby preventing epitaxial growth of the epitaxial source / drain region 92 adjacent to the upper surface of the shallow trench isolation region 68. As a result, spacer 81 can extend on the lower sidewall of the separated lower portion of the epitaxial source / drain region 92. In some embodiments, the etching process used to form spacer 81 can be adjusted to remove spacer 81 on the upper surface of the epitaxial source / drain region 92, allowing the epitaxial source / drain region 92 to extend on the upper surface of the shallow trench isolation region 68.

[0099] The epitaxial source / drain region 92 may include one or more layers of semiconductor material. In some embodiments, the epitaxial source / drain region 92 includes a first pad layer 92A on the sidewall of the second nanostructure 54, a second pad layer 92B on the first pad layer 92A, and a fill layer 92C on the second pad layer 92B, such as... Figure 12C As shown. The first pad layer 92A, the second pad layer 92B, and the fill layer 92C can be formed from different semiconductor materials and / or can be doped to different dopant concentrations. The first pad layer 92A can be grown first, the second pad layer 92B can be grown on the first pad layer 92A, and the fill layer 92C can be grown on the second pad layer 92B.

[0100] Figure 12E An embodiment is shown in which the sidewalls of the first nanostructure 52 are recessed, the outer sidewalls of the first internal spacer 90 are recessed, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54. For example... Figure 12E As shown, the epitaxial source / drain region 92 can be formed to contact the first internal spacer 90 and can extend beyond the sidewall of the second nanostructure 54.

[0101] exist Figures 13A to 13C In the middle, the first interlayer dielectric (ILD) 96 is deposited in Figures 12A to 12C Above the structure shown. The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphorus silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphorus silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain region 92, the mask 78, and the spacer 81. The contact etch stop layer 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material covering the first interlayer dielectric 96.

[0102] exist Figures 14A to 14C In this process, a planarization process such as CMP can be performed to make the upper surface of the first interlayer dielectric 96 flush with the upper surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and the portion of the spacer 81 along the sidewall of the mask 78. After the planarization process, the upper surfaces of the dummy gate 76, the spacer 81, and the first interlayer dielectric 96 are horizontal within the process variation. Therefore, the upper surface of the dummy gate 76 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the upper surface of the first interlayer dielectric 96 flush with the upper surfaces of the mask 78 and the spacer 81.

[0103] exist Figures 15A to 15CIn one or more etching processes, at least partially, the dummy gate 76 and dummy gate dielectric 71 are removed to form a third trench 98. In some embodiments, after one or more etching processes, the portion of the dummy gate dielectric 71 between the nanostructure 55 (e.g., the second nanostructure 54A) and the third portion of the spacer 81 remains intact. In some embodiments, after one or more etching processes, a portion of the dummy gate 76 remains intact, as does the portion of the dummy gate dielectric 71 below the third portion of the spacer 81 and above the shallow trench isolation region 68. In some embodiments, the third portion of the spacer 81 is separated from the remaining portion of the dummy gate 76. The dummy gate 76 and dummy gate dielectric 71 can be at least partially removed by an anisotropic dry etching process. The dry etching process can use a reactive gas that selectively etches the dummy gate 76 and dummy gate dielectric 71 at a faster etch rate than that used on the first interlayer dielectric 96 and / or the spacer 81. Each third groove 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nano-FET. Portions of the nanostructure 55 that can serve as channel regions (e.g., second nanostructure 54) are disposed between adjacent pairs of epitaxial source / drain regions 92. During the etching process, the dummy gate dielectric 71 can serve as an etch stop layer when the dummy gate 76 is removed, and the dummy gate dielectric 71 can be removed after the dummy gate 76 is removed.

[0104] exist Figures 16A to 16C In this process, the first nanostructure 52 is removed, extending the third trench 98. The first nanostructure 52 can be removed by a unidirectional etching process (e.g., wet etching) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the shallow trench isolation region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A to 54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52.

[0105] exist Figures 17A to 17D In the third groove 98, the gate dielectric layer 100 and the gate electrode 102 are formed. Figure 17D Shown in Figure 17A , Figure 17B and Figure 17CThe top view of the structure shown includes a second nanostructure 54A along a reference cross-section D-D'. A gate dielectric layer 100 may be conformally deposited in a third recess 98. The gate dielectric layer 100 may be formed on the upper surface and sidewalls of the substrate 50, and on the upper surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the upper surfaces of the first interlayer dielectric 96, the contact etch stop layer 94, the spacer 81, and the shallow trench isolation region 68, and on the sidewalls of the spacer 81 and the first inner spacer 90. Furthermore, the gate dielectric layer 100 may also be formed on the exposed surface of the third portion of the spacer 81, and on the exposed surfaces of the residual portions of the dummy gate dielectric 71 and the dummy gate 76.

[0106] In some embodiments, the gate dielectric layer 100 comprises one or more dielectric layers, such as oxides or combinations thereof. For example, in some embodiments, the gate dielectric may comprise a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may comprise oxides or silicates of the following: hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0107] Gate electrode 102 is deposited over gate dielectric layer 100 and fills the remaining portion of third groove 98. Gate electrode 102 and gate dielectric layer 100 may surround (e.g., enclose) some of the second nanostructure 54A and extend between the second nanostructure 54A and fin 66. In some embodiments, gate electrode 102 and gate dielectric layer 100 may surround (e.g., enclose) the second nanostructure 54A, the third portion of spacer 81, and the remaining portion of dummy gate dielectric 71 located between the second nanostructure 54A and the third portion of spacer 81. As a result, the second nanostructure 54A, the third portion of spacer 81, and the remaining portion of dummy gate dielectric 71 located between the second nanostructure 54A and the third portion of spacer 81 may extend through the same opening in gate electrode 102. In some embodiments, gate electrode 102 and gate dielectric layer 100 extend between the third portion of spacer 81 and the remaining portion of dummy gate 76.

[0108] The gate electrode 102 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although Figure 17A , Figure 17C and Figure 17D A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and in the n-type region 50N between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P located between adjacent first nanostructures 52.

[0109] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 in each region can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0110] After filling the third recess 98, a planarization process (e.g., CMP) can be performed to remove excess portions of the gate dielectric layer 100 and material of the gate electrode 102, which are located above the upper surface of the first interlayer dielectric 96. The remaining portions of the gate electrode 102 and the material of the gate dielectric layer 100 thus form the alternative gate structure of the obtained nano-FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the gate structure.

[0111] exist Figures 18A to 18C In this design, the gate structure (including the gate dielectric layer 100 and the corresponding covered gate electrode 102) is recessed, and the recess is formed directly above the gate structure and between opposing portions of the spacer 81. The gate mask 104 comprises one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) filled in the recess, followed by a planarization process to remove excess dielectric material extending above the first interlayer dielectric 96. The subsequently formed gate contact can extend through the gate mask 104 to contact the upper surface of the recessed gate electrode 102. Figures 18A to 18CAs further shown, the second interlayer dielectric 106 is deposited over the first interlayer dielectric 96 and over the gate mask 104. In some embodiments, the second interlayer dielectric 106 is a flowable thin film formed via FCVD. In some embodiments, the second interlayer dielectric 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0112] exist Figures 19A to 19C In this process, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a fourth groove 108 that exposes the surface of the epitaxial source / drain region 92 and / or some gate structure surfaces. The fourth groove 108 can be formed by etching using anisotropic etching processes such as RIE or NBE. In some embodiments, the fourth groove 108 can be etched using a first etching process to penetrate the second interlayer dielectric 106 and the first interlayer dielectric 96; the fourth groove 108 can be etched using a second etching process to penetrate the gate mask 104; and then the fourth groove 108 can be etched using a third etching process to penetrate the contact etch stop layer 94. A mask, such as a photoresist, can be formed and patterned over the second interlayer dielectric 106 to shield portions of the second interlayer dielectric 106 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch. Therefore, the fourth groove 108 extends into the epitaxial source / drain region 92 and / or some gate structures, and the bottom of the fourth groove 108 may be flush with the epitaxial source / drain region 92 and / or some gate structures (e.g., at the same level as the substrate 50, or at the same distance from the substrate 50), or lower than the epitaxial source / drain region 92 and / or some gate structures (e.g., closer to the substrate 50).

[0113] After the fourth groove 108 is formed, a first silicide region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) that can react with the semiconductor material of the underlying epitaxial source / drain region 92 to form a silicide region or a germanide region. This metal is, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, followed by a first thermal annealing process to form the first silicide region 110. In some embodiments, the first thermal annealing process is performed at a temperature of approximately 450°C. Unreacted portions of the deposited metal are removed by, for example, an etching process. Although the first silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon germanide region (e.g., a region comprising both silicide and germanide).

[0114] exist Figures 20A to 20D In the fourth groove 108, source / drain contacts 112 and gate contacts 114 (also referred to as conductive contacts) are formed. Figure 20D Shown in Figure 20A , Figure 20B and Figure 20C The top view of the structure shown includes a second nanostructure 54A along a reference cross section D-D'. The source / drain contact 112 and gate contact 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, the source / drain contact 112 and gate contact 114 each include a barrier layer and a conductive material, and are each electrically connected to an underlying conductive component (e.g., gate electrode 102 and / or first silicide region 110). Gate contact 114 is electrically connected to gate electrode 102, and source / drain contact 112 is electrically connected to first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second interlayer dielectric 106. Figures 20A to 20C The structure shown can be referred to as semiconductor element 120.

[0115] Figure 21 Showing with Figure 20A The semiconductor element 120 shown is similar to semiconductor element 121, and according to some embodiments, the same element symbols refer to the same features formed by the same process. In semiconductor element 121, the third portion of spacer 81 may be connected to a redundant portion of dummy gate 76 on shallow trench isolation region 68. A layer of dummy gate dielectric 71 may be located between the second nanostructure 54A and the third portion of spacer 81, and between fin 66 and the redundant portion of dummy gate 76. Figure 21 The vertical position, horizontal position, and shape of the third portion of the spacer 81 are provided as examples. The third portion of the spacer 81 can be located anywhere on the gate electrode 102 and can have any shape, similar to Figure 20A The third part of the spacer 81 shown.

[0116] Figure 22 Showing with Figure 20AThe semiconductor element 120 shown is similar to semiconductor element 122, and according to some embodiments, the same element symbol refers to the same features formed by the same process. Semiconductor element 122 may be a fin-FET, wherein the top portion of fin 66 may be a channel region. In semiconductor element 122, a third portion of spacer 81 may be adjacent to the top portion of fin 66, and a portion of dummy gate dielectric 71 may be between the top portion of fin 66 and the third portion of spacer 81.

[0117] Figure 23 It shows the relationship with Figure 21 Semiconductor element 123, similar to semiconductor element 121 shown, is described in some embodiments where the same element designation refers to the same features formed by the same process. Semiconductor element 123 may be a fin-FET, where the top portion of fin 66 may be a channel region. In semiconductor element 123, a third portion of spacer 81 may be adjacent to the top portion of fin 66, and a portion of dummy gate dielectric 71 may be between the top portion of fin 66 and the third portion of spacer 81, or between the top portion of fin 66 and any remaining portion of dummy gate 76 located on shallow trench isolation region 68.

[0118] Figures 24A to 27 It is a view of a semiconductor device (e.g., a nano-FET) at an intermediate stage of manufacturing, based on some implementations. Figure 24A , Figure 25A , Figure 26A and Figure 27 It shows along Figure 1 The cross-sectional view of the reference cross section A-A' is shown. Figure 24B , Figure 25B and Figure 26B It shows along Figure 1 The cross-sectional view of the reference cross section B-B' is shown. Figure 24C , Figure 25C and Figure 26C It shows along Figure 1 The cross-sectional view of the reference cross section C-C' is shown.

[0119] Figures 24A to 24D It shows the relationship with Figures 6A to 6D The structure shown is similar to some embodiments, wherein the same symbolic elements refer to those formed by, for example, Figures 2 to 6D The same features are formed by the same process described. Figures 24A to 24D Features of either or both of the n-type region 50N and / or the p-type region 50P are shown. Figure 24D It shows Figure 24A , Figure 24B and Figure 24CA top view of the structure shown (including the second nanostructure 54A) along a reference cross-section D-D'. Figures 24A to 24D In the illustrated embodiment, the void 73 is surrounded by a dummy gate 76 in the cross-sectional view and extends through the dummy gate 76 in the top view. The dummy gate 76 can be formed from amorphous silicon or the like. The dummy gate 76 can be formed by a suitable deposition process, such as physical vapor deposition (PVD), CVD, sputtering deposition, etc., followed by a patterning process. The deposition temperature can be from about 400°C to about 500°C, and the deposition pressure can be from about 0.5 torr to about 2.5 torr. Using amorphous silicon to form the dummy gate 76 can cause the void 73 to separate from the dummy gate dielectric 71, which can improve the performance of the subsequently formed semiconductor device.

[0120] For illustrative purposes, Figure 24A A gap 73 is shown disposed in the dummy gate 76. The dummy gate 76 may have more than one gap 73. For illustrative purposes, Figure 24A The vertical position of the void 73 adjacent to the second nanostructure 54A is shown. The vertical position of the void 73 can be anywhere on the dummy gate 76, including adjacent to the top portion of other nanostructures in nanostructure 55 and / or fins 66. For illustrative purposes, Figure 24A The figure illustrates the horizontal position of the gap 73 between the two stacked nanostructures 55. The horizontal position of the gap 73 can be any location in the dummy gate layer 72, including the left and / or right sides of the two stacks of nanostructures 55. For illustrative purposes, Figure 24A A gap 73 with an elliptical shape is shown. The gap 73 can have any shape (e.g., circular).

[0121] Figures 25A to 25D It shows the relationship with Figures 7A to 7D The structure shown is similar to some embodiments, where the same element symbols refer to those formed by, for example... Figures 7A to 7D The same features are formed by the same process described. Figure 25D It shows Figure 25A , Figure 25B and Figure 25C The structure shown (including the second nanostructure 54A) is a top view along a reference cross-section D-D'. The spacer layer 80 may at least partially fill the voids 73 in the dummy gate 76. Figure 25D As shown, the first and second portions of the spacer layer 80 may extend on opposite sides of the dummy gate 76, and a third portion may also extend on opposite sides of the dummy gate 76. The third portion of the spacer layer 80 may extend through the dummy gate 76 and connect to the first and second portions of the spacer layer 80. The first, second, and third portions of the spacer layer 80 may form an H-shape in the top view. Figure 25A As shown, in some embodiments, the third portion of the spacer layer 80 that fills the void 73 can be elliptical, with a height H2 of about 1 nm to about 30 nm and a width W2 of about 1 nm to about 30 nm.

[0122] Figures 26A to 26D It shows the relationship with Figures 20A to 20D The structure shown is similar to some embodiments, where the same element symbols refer to those formed by, for example... Figures 8A to 20D The same features are formed by the same process described. Figure 26D It shows Figure 26A , Figure 26B and Figure 26C The structure shown (including the second nanostructure 54A) is a top view along the reference cross section D-D'. Figures 26A to 26C The structure shown can be referred to as semiconductor device 124. A gate dielectric layer 100 can be formed on the exposed surface of the third portion of spacer 81, and on the exposed surfaces of the remaining portions of dummy gate dielectric 71 and dummy gate 76. The gate dielectric layer 100 and gate electrode 102 can surround (e.g., enclose) all of the second nanostructure 54 and the third portion of spacer 81. The gate dielectric layer 100 and gate electrode 102 can extend between the second nanostructure 54 and the third portion of spacer 81, and between the second nanostructure 54 and fin 66. As a result, improved control of the channel region (e.g., the second nanostructure 54) through the gate electrode 102 can be achieved, thereby improving the performance of semiconductor device 124. In some embodiments, the gate dielectric layer 100 and gate electrode 102 extend between the third portion of spacer 81 and the remaining portions of dummy gate 76.

[0123] Figure 27 It shows the relationship with Figure 26A Semiconductor element 124, similar to semiconductor element 125, according to some embodiments, refers to the same element symbols as those formed by the same process, where the same element symbol indicates the same feature. In semiconductor element 125, the third portion of spacer 81 may be connected to an additional portion of the dummy gate 76 on the shallow trench isolation region 68. Figure 27 The vertical position, horizontal position, and shape of the third portion of the spacer 81 are provided as examples. The third portion of the spacer 81 can be located anywhere on the gate electrode 102 and can have any shape, similar to... Figure 26A The third part of the spacer 81 shown.

[0124] Figure 28 It shows the relationship with Figure 26AThe semiconductor element 124 shown is similar to the semiconductor element 126, and according to some embodiments, the same element symbol refers to the same features formed by the same process. The semiconductor element 126 can be a fin-FET, where the top portion of the fin 66 can be a channel region. In the semiconductor element 126, a third portion of the spacer 81 can be adjacent to the top portion of the fin 66.

[0125] Figure 29 It shows the relationship with Figure 27 The semiconductor element 125 shown is similar to the semiconductor element 127, and according to some embodiments, the same element symbol refers to the same features formed by the same process. The semiconductor element 127 can be a fin-FET, where the top portion of the fin 66 can be a channel region. In the semiconductor element 127, a third portion of the spacer 81 can be adjacent to the top portion of the fin 66.

[0126] The embodiments disclosed in this utility model have several advantageous features. By selecting appropriate materials to form the dummy gate 76, improved control of the channel region (e.g., the second nanostructure 54) via the gate electrode 102 can be achieved, thereby improving the performance of various semiconductor devices.

[0127] In one embodiment, the semiconductor device includes a substrate; a first channel region and a second channel region above the substrate; a gate structure located on one or more sidewalls of the first channel region and one or more sidewalls of the second channel region; and a dielectric spacer located on a first side and a second side of the gate structure in a top view, wherein the first side and the second side are opposite each other, and wherein a first portion of the dielectric spacer extends between the first channel region and the second channel region. In one embodiment, the semiconductor device further includes a first dielectric layer on a first side of the first channel region, wherein the first portion of the dielectric spacer is on the first dielectric layer, and the gate structure is on a second side of the first channel region, wherein the first side and the second side are opposite each other. In one embodiment, the gate structure surrounds the first portion of the dielectric spacer. In one embodiment, the gate structure surrounds the first channel region and the second channel region. In one embodiment, the first channel region and the second channel region are the top portions of a fin structure projecting from the substrate. In one embodiment, the semiconductor device further includes a semiconductor dummy gate structure, wherein the first portion of the dielectric spacer is in contact with the semiconductor dummy gate structure. In one embodiment, the semiconductor virtual gate structure comprises amorphous silicon. In another embodiment, the semiconductor element further includes a source / drain region in contact with the first channel region, wherein a second portion of the dielectric spacer extends on the lower sidewall of the source / drain region.

[0128] In one embodiment, the semiconductor element includes: a substrate; a first channel region above the substrate; a gate structure located on an upper surface and one or more sidewalls of the first channel region; and an insulating spacer, wherein, in a top view, a first portion of the insulating spacer is located on a first side of the gate structure, and a second portion of the insulating spacer is located on a second side of the gate structure, wherein the first side and the second side are opposite each other, and wherein, in a top view, a third portion of the insulating spacer extends through the gate structure, and wherein the third portion of the insulating spacer contacts the first and second portions of the insulating spacer. In one embodiment, the first, second, and third portions of the insulating spacer form an H-shape in a top view. In one embodiment, the semiconductor element further includes a fin structure projecting from the substrate, wherein the first channel region is located above the fin structure, and wherein the gate structure extends between the fin structure and the first channel region. In one embodiment, the gate structure extends between the first channel region and the third portion of the insulating spacer. In one embodiment, the semiconductor element further includes a semiconductor virtual structure located below the third portion of the insulating spacer, wherein the semiconductor virtual structure comprises amorphous silicon. In one embodiment, a third portion of the insulating spacer extends along the sidewall of the first channel region, and wherein the third portion of the insulating spacer and the first channel region extend through the same opening in the gate structure. In another embodiment, the semiconductor element further includes a semiconductor dummy structure located below the third portion of the insulating spacer, wherein the semiconductor dummy structure comprises polysilicon.

[0129] In one embodiment, a method of forming a semiconductor device includes: forming a first channel region and a second channel region over a substrate; forming a dummy gate structure along a first sidewall of the first channel region and a first sidewall of the second channel region, wherein a void extends through the dummy gate structure; forming a dielectric spacer, wherein a first portion of the dielectric spacer at least partially fills the void; removing at least a portion of the dummy gate structure; and forming a gate structure along the first sidewall of the first channel region and the first sidewall of the second channel region, wherein the first portion of the dielectric spacer extends through the gate structure. In one embodiment, the first portion of the dielectric spacer is located between the first channel region and the second channel region. In one embodiment, the gate structure surrounds the first portion of the dielectric spacer. In one embodiment, a portion of the dummy gate structure extends between the first channel region and the first portion of the dielectric spacer. In one embodiment, after removing at least a portion of the dummy gate structure, a portion of the dummy gate structure remains below the first portion of the dielectric spacer.

[0130] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various solutions disclosed in the embodiments of this utility model. Those skilled in the art should understand that they can readily use the embodiments of this utility model as the basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described in this utility model. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments of this utility model, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments of this utility model.

Claims

1. A semiconductor element characterized by comprising: Comprising: a substrate; a first channel region and a second channel region over the substrate; a gate structure, wherein the gate structure is on one or more sidewalls of the first channel region and one or more sidewalls of the second channel region; and a dielectric spacer on a first side and a second side of the gate structure in a top view, wherein the first side is opposite the second side, and wherein a first portion of the dielectric spacer extends between the first channel region and the second channel region.

2. The semiconductor device according to claim 1, wherein The gate structure surrounds the first portion of the dielectric spacer.

3. The semiconductor device according to claim 2, wherein The gate structure surrounds the first channel region and the second channel region.

4. The semiconductor device of claim 1, further comprising a semiconductor dummy gate structure, wherein: The first portion of the dielectric spacer is in contact with the semiconductor dummy gate structure.

5. The semiconductor device of claim 1, further comprising a source / drain region in contact with the first channel region, wherein, A second portion of the dielectric spacer extends on a lower sidewall of the source / drain region.

6. A semiconductor element characterized by comprising: Comprising: a substrate; a first channel region over the substrate; a gate structure, wherein the gate structure is on an upper surface and one or more sidewalls of the first channel region; and an insulating spacer, wherein a first portion of the insulating spacer is on a first side of the gate structure and a second portion of the insulating spacer is on a second side of the gate structure in a top view, wherein the first side is opposite the second side, wherein a third portion of the insulating spacer extends through the gate structure in the top view, and wherein the third portion of the insulating spacer is in contact with the first portion and the second portion of the insulating spacer.

7. The semiconductor device of claim 6, further comprising a fin structure protruding from the substrate, wherein, The first channel region is over the fin structure, and wherein the gate structure extends between the fin structure and the first channel region.

8. The semiconductor device according to claim 6, wherein The gate structure extends between the first channel region and the third portion of the insulating spacer.

9. The semiconductor device according to claim 6, wherein The third portion of the insulating spacer extends along a sidewall of the first channel region, and wherein the third portion of the insulating spacer and the first channel region extend through a same opening in the gate structure.

10. A semiconductor element characterized by comprising: Comprising: a substrate; a first channel region and a second channel region over the substrate; a gate structure, wherein the gate structure is on one or more sidewalls of the first channel region and one or more sidewalls of the second channel region; and a dielectric spacer on a first side and a second side of the gate structure in a top view, wherein the first side is opposite the second side, and wherein a first portion of the dielectric spacer extends between the first channel region and the second channel region; and a dielectric layer on a first side of the first channel region, wherein the first portion of the dielectric spacer is on the dielectric layer, wherein the gate structure is on a second side of the first channel region, and wherein the first side is opposite the second side.

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