Semiconductor device
By employing a front trench and rear trench design in HEMT devices, combined with external and internal sealing rings, and using highly selective etchants, the problems of high manufacturing cost and low yield in existing technologies are solved, achieving higher manufacturing efficiency and device reliability.
Patent Information
- Application Number
- CN202423110236.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-12-12
- Filing Date
- 2024-12-17
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2034-12-17
AI Technical Summary
Existing HEMT devices have difficulty controlling the etching selectivity between the semiconductor heterostructure and the source metal layer during manufacturing, resulting in high manufacturing costs, low yield, and mechanical stress caused by lattice mismatch that may lead to device failure.
The design employs front and rear trenches, combined with external and internal sealing rings. The trenches are formed by sharing the same mask and etching steps, optimizing the manufacturing process. Highly selective etchants are used to control the etching rate and sidewall slope, ensuring good contact.
This increases the manufacturing yield and reduces the manufacturing cost of HEMT devices, while also reducing the risk of cracks and dislocations, and improving the reliability of the devices and the stability of the electrical connections.
Smart Images
Figure CN223810086U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a transistor device based on a heterostructure with a back contact area, such as a high electron mobility transistor (HEMT) device. The present disclosure also relates to a HEMT device for radio frequency (RF) applications. BACKGROUND
[0002] It is known that HEMT devices are field effect transistor devices based on a heterostructure, which are spreading widely due to the possibility of operating at high voltages, high breakdown voltage and high electron density and mobility.
[0003] HEMT devices for radio frequency applications typically have better RF performance than similar silicon lateral diffused metal oxide semiconductor (LDMOS) devices.
[0004] The operation of transistor devices based on a heterostructure is based on the formation of a two-dimensional charge carrier (electron) gas within the semiconductor heterostructure, at the interface between two different semiconductor materials, typically AlGaN / GaN layers.
[0005] The transistor device has an active region, in which the two-dimensional carrier gas forms a conductive channel between two conductive regions, a source region and a drain region. Moreover, the formation of the two-dimensional carrier gas within the active region is electrostatically modulated by a gate region.
[0006] In HEMT devices, the semiconductor heterostructure is grown on a wafer of a different material, such as silicon (Si) or silicon carbide (SiC), with respect to the materials forming the heterostructure.
[0007] In some HEMT devices, such as for RF applications, the source region is electrically contacted from the back of the HEMT device.
[0008] Figure 1 An intermediate step of the manufacturing process of a known HEMT device is shown. In Figure 1 In the figure, a semiconductor heterostructure 3 based on GaN layers has been grown on the front side of a wafer 5 of silicon or silicon carbide. A source metal layer 6 of TiAlCu or gold has been formed on the semiconductor heterostructure 3 and forms the source region.
[0009] A back metal layer 7 of nickel or copper extends on the back side of the wafer 5.
[0010] In order to form the contact via of the source region, a trench 8 is formed from the back of the wafer 5 through the back metal layer 7 and the wafer 5 up to the semiconductor heterostructure 3. The back metal layer 7 is used as a hard mask to form the trench 8.
[0011] Subsequently, Figure 2From the back of the wafer 5 and through the trench 8 up to the source metal layer 6, the part of the semiconductor heterostructure 3 exposed by the trench 8 is removed. Summary of the utility model
[0012] This method allows the use of the same photolithographic mask (i.e. the back metal layer 7) to remove parts of the wafer 5 and of the semiconductor heterostructure 3. However, it has proven difficult to control due to the low etch selectivity between GaN, which forms the semiconductor heterostructure 3, and the source metal layer 6.
[0013] Indeed, both the semiconductor heterostructure 3 and the source metal layer 6 are etched using a chlorine-based etchant solution.
[0014] Furthermore, this method makes the implementation of a post-etch treatment aimed at inhibiting the corrosion of the source metal layer 6 (such as when the source metal layer 6 is based on aluminum) and the integration of the HEMT device with other devices (such as if the integration is done by bonding) difficult.
[0015] Therefore, this method requires a lower manufacturing process yield and higher manufacturing costs.
[0016] Furthermore, in the known HEMT devices, the lattice mismatch between the material forming the semiconductor heterostructure and the wafer can cause mechanical stress in the wafer. During the dicing of the wafer, the residual mechanical stress can cause cracks and dislocations to propagate towards the active area of the HEMT device, which can very well break or malfunction.
[0017] According to one method, an outer sealing ring and an inner sealing ring surrounding the active area are formed in the HEMT device before dicing the wafer.
[0018] The outer sealing ring is formed by removing a part of the semiconductor heterostructure around the active area through the thickness of the semiconductor heterostructure.
[0019] The inner sealing ring is formed by removing a part of the dielectric layer formed on the HEMT device around the active area between the active area and the outer sealing ring. The trench formed across the dielectric layer is then filled with a metal layer stack.
[0020] The outer sealing ring and the inner sealing ring reduce the risk of cracks and dislocations propagating during the dicing of the wafer.
[0021] However, the formation of the outer sealing ring and the inner sealing ring requires the introduction of additional manufacturing steps, which can reduce the yield of the overall manufacturing process and increase its costs.
[0022] It is an object of the present disclosure to overcome at least part of the drawbacks of the prior art.
[0023] Thus, a transistor device based on a heterostructure such as a HEMT is provided.
[0024] According to one or more embodiments, a semiconductor device comprises:
[0025] a die comprising a substrate having a front surface and a back surface and an epitaxial multilayer on the substrate extending from the front surface of the substrate along a first direction up to an upper surface;
[0026] an active region comprising a first conductive region of conductive material on the epitaxial multilayer; and
[0027] a contact region for biasing the first conductive region,
[0028] wherein the contact region comprises:
[0029] a front trench extending in the die from the upper surface of the epitaxial multilayer towards the back surface of the substrate up to a contact surface;
[0030] a conductive region extending within the front trench on the contact surface and in electrical contact with the first conductive region;
[0031] a back trench extending in the die from the back surface of the substrate towards the upper surface of the epitaxial multilayer up to the contact surface; and
[0032] a back metallization layer extending on the contact surface on the back surface of the substrate and within the back trench.
[0033] According to one or more embodiments, the semiconductor device, the front trench has a first width along a second direction transverse to the first direction at the upper surface comprised between 15 pm and 100 pm and a second width along the second direction at the contact surface comprised between 10 pm and 95 pm, the second width being smaller than the first width.
[0034] According to one or more embodiments, the semiconductor device further comprises an outer sealing ring extending around the active region and comprising an outer trench extending in the die from the upper surface of the epitaxial multilayer towards the back surface of the substrate up to a lower surface, the outer trench having a same profile as the front trench and a same depth and a same slope as the side wall.
[0035] According to one or more embodiments, the semiconductor device is for radio frequency applications and wherein the substrate has a thickness along the first direction comprised between 40 pm and 120 pm.
[0036] According to one or more embodiments, a semiconductor device comprises:
[0037] a die having an active region and a substrate, the substrate comprising a first surface and a second surface opposite to the first surface;
[0038] an epitaxial multilayer on a first surface of the substrate, the epitaxial multilayer extending from the first surface of the substrate to an upper surface in the first direction; and
[0039] a trench extending through the epitaxial multilayer in the first direction and partially within the substrate to a lower surface, the trench having a first width along the second direction at the upper surface and a second width along the second direction at the lower surface.
[0040] According to one or more embodiments, the first width is between 10 pm and 100 pm, and the second width is less than the first width.
[0041] According to one or more embodiments, the epitaxial multilayer has a thickness between 1.5 pm and 5 pm between the first surface and the upper surface.
[0042] According to one or more embodiments, the trench includes a sidewall, a width of the sidewall trending to decrease along the second direction from the upper surface toward the lower surface.
[0043] According to one or more embodiments, the sidewall has a slope less than 60°.
[0044] The present disclosure is therefore able to overcome at least some of the drawbacks of the prior art. BRIEF DESCRIPTION OF DRAWINGS
[0045] Embodiments of the present disclosure will now be described, by way of non-limiting example only, with reference to the accompanying drawings:
[0046] Figure 1 and Figure 2 shows a cross-section of a known HEMT device in subsequent manufacturing steps;
[0047] Figure 3 shows a top view of a HEMT device according to one embodiment;
[0048] Figure 4A shows a cross-section of a portion of the sealing ring region of the HEMT device of Figure 3 along section line IVA-IVA of Figure 3
[0049] Figure 4B shows a cross-section of a portion of the active region of the HEMT device of Figure 3 along section line IVB-IVB of Figure 3
[0050] Figures 5A to 11A shows the HEMT device of Figure 3 in subsequent manufacturing steps along Figure 3 a cross-section along section line IVA-IVA of the HEMT device of
[0051] Figures 5B to 11B a cross-section along section line IVB-IVB of the HEMT device of Figure 3 Figure 3 a cross-section along section line IVA-IVA of the HEMT device of DETAILED DESCRIPTION
[0052] The following description refers to the arrangement shown in the accompanying drawings; therefore, such terms as "above", "below", "upper", "lower", "right", "left", "top", "bottom", and the like are to be interpreted in reference to the drawings and not in a limiting manner.
[0053] Figure 3 , Figure 4A and Figure 4B shows a heterostructure-based field effect transistor device, such as a high electron mobility transistor (HEMT) device 20, in a Cartesian reference frame XYZ comprising a first axis X, a second axis Y and a third axis Z.
[0054] The HEMT device 20 is formed in a die 21 and comprises an active region 23 and an outer seal ring 25 surrounding the active region 23.
[0055] In this embodiment, the HEMT device 20 further comprises an inner seal ring 27, which surrounds the active region 23 and is arranged between the active region 23 and the outer seal ring 25.
[0056] As can be seen in Figure 4A and Figure 4B , the die 21 comprises a substrate 30 and an epitaxial multilayer 31 extending on the substrate 30.
[0057] The substrate 30 can be formed of one or more layers of silicon, silicon carbide, gallium nitride (GaN), sapphire (AI2O3) or other materials. The substrate 30 can be made of a semiconductor material, for example silicon or silicon carbide.
[0058] The substrate 30 has a front surface 30A and a back surface 30B opposite to each other.
[0059] The substrate 30 can have a thickness measured along the third axis Z between the front surface 30A and the back surface 30B, for example comprised between 40 pm and 120 pm. For RF applications, the substrate 30 can have a thin thickness, for example comprised between 60 pm and 100 pm.
[0060] The epitaxial multilayer 31 extends from the front surface 30A of the substrate 30 up to the upper surface 31 A and comprises a buffer region 32 and a semiconductor heterostructure 33.
[0061] The epitaxial multilayer 31 can have a thickness, measured along the third axis Z between the front surface 30A and the upper surface 31 A, comprised between 1.5 pm and 5 pm.
[0062] The buffer region 32, which is optionally of a material different from the substrate 30 (e.g. AIN, AlGaN, GaN, SiC), extends between the substrate 30 and the semiconductor heterostructure 33 and can serve to allow epitaxial growth of the semiconductor heterostructure 33 on the substrate 30.
[0063] The semiconductor heterostructure 33 is configured to host a two-dimensional gas of (mobile) charge carriers, such as electrons.
[0064] In detail, the semiconductor heterostructure 33 comprises two or more compound semiconductor materials different from each other, including elements from group III and group V of the periodic table.
[0065] The semiconductor heterostructure 33 can be based on GaN, i.e. comprising layers including GaN, such as for example GaN and alloys including GaN.
[0066] In detail, although not shown herein, the semiconductor heterostructure 33 can comprise a channel layer, for example of gallium nitride (GaN) or of an alloy including gallium nitride, such as InGaN, such as GaN; and a barrier layer, for example of a compound based on ternary or quaternary gallium nitride alloys, such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x Al, AlScN, such as having aluminum gallium nitride (AlGaN)), the channel layer and the barrier layer being overlaid to each other.
[0067] The semiconductor heterostructure 33 forms the upper surface 31 A.
[0068] The external sealing ring 25 is a trench (hereinafter referred to as external trench 25) extending through the thickness of the epitaxial multilayer 31 along the third axis Z through the epitaxial multilayer 31.
[0069] In this embodiment, the external sealing ring 25 also extends, partially, within the substrate 30 up to the lower surface 40. This can allow optimizing the manufacturing of the present HEMT device and reducing its manufacturing costs.
[0070] In this embodiment, the width of the external trench 25, i.e. the distance between the inner surface of the external trench 25 and the outer surface of the epitaxial multilayer 31, is constant along the third axis Z. Figure 4AThe width (measured along the first axis X) in the cross-section decreases from the upper surface 31A toward the lower surface 40. For example, the sidewalls of the outer groove 25 may have a slope of less than 60°, as shown below. Figure 7A It was discussed in detail.
[0071] Specifically, the external trench 25 has a width W at the upper surface 31A of the epitaxial multilayer 31. SR,t It is between, for example, 10 μm and 100 μm, and has a width W at 40 on the lower surface. SR,b The width W SR,b Less than width W SR,t And for example, it is between 5μm and 95μm.
[0072] As discussed below, the profile (depth and width trend) along the third axis Z of the outer groove 25 indicates the specific manufacturing process used to form the outer groove 25.
[0073] The internal sealing ring 27 includes a stack of metal layers 42 extending on the epitaxial multilayer 31, such as being in direct contact with the upper surface 31A.
[0074] In this embodiment, the stack 42 includes a contact region 43 on the epitaxial multilayer 31, the contact region 43 being, for example, Ti, Ta, Al, AlCu, AlSiCu, Au, Ni and other metallic materials; an intermediate region 44 on the contact region 43, the intermediate region 44 being, for example, Ti, Al, AlCu, AlSiCu, Ni, Au and other metallic materials; and an upper region 45 on the intermediate region 44, the upper region being, for example, Ti, Al, AlCu, AlSiCu, Ni, Au and other metallic materials.
[0075] like Figure 3 and Figure 4B As shown, the HEMT device 20 includes a source region 50, a drain region 51, and a gate region 52 in the active region 23, which respectively form the source electrode S, drain electrode D, and gate electrode G of the HEMT device 20.
[0076] The source region 50 and the drain region 51 extend in contact with the epitaxial multilayer 31 and are each formed by a plurality of conductive layers (such as metal layers) disposed on top of the other.
[0077] In detail, the source region 50 and the drain region 51 each comprise: a respective functional portion 50A, 51A, e.g. of Ti, Ta, Al, AlCu, AlSiCu, Au, Ni and other metallic materials, in electrical contact (such as ohmic contact) with the semiconductor heterostructure 33; a respective first contact portion 50B, 51B, e.g. of Ti, Al, AlCu, AlSiCu, Au, Ni and other metallic materials, extending over the respective functional portion 50A, 51A; and a respective second contact portion 50C, 51C, e.g. of Ti, Al, AlCu, AlSiCu, Au, Ni and other metallic materials, extending over the respective first contact portion 50B, 51B.
[0078] The gate region 52 comprises a respective functional portion 52A configured to modulate the formation of 2DEG in the semiconductor heterostructure 33.
[0079] The nature of the functional portion 52A depends on the type of HEMT device 20 (normally-on or normally-off). For example, the functional portion 52A can be of a metallic material, such as to obtain a normally-on device; or the functional portion 52A can be of a semiconducting material (e.g. p-GaN), such as to obtain a normally-off device.
[0080] In the case of a HEMT device for RF applications, the HEMT device can be normally-on, and for example the functional portion 52A can be of a metallic material.
[0081] The functional portion 52A extends over the semiconductor heterostructure 33 between the functional portion 50A, the functional portion 51A of the source region 50 and the drain region 51, respectively.
[0082] The gate region 52 can be of an insulating type, i.e. comprising an insulating region in contact with the semiconductor heterostructure 33.
[0083] The gate region 52 further comprises a gate contact region (not shown here) of an electrically conductive material (such as a metallic material) in electrical contact with the functional portion 52A, for biasing the gate region 52 in use.
[0084] For simplicity, in Figure 3 the respective functional portions 50A, 51A, 52A of the source 50, drain 51 and gate 52 regions are shown.
[0085] The HEMT device 20 further comprises a source contact region 60 Figure 4B extending in the active region 23, for biasing the source region 50 in use.
[0086] The source contact region 60 includes a front trench 61 extending along the third axis Z from the upper surface 31A through the epitaxial multilayer 30, and a rear trench 62 extending along the third axis Z from the rear surface 30B of the substrate 30 through the substrate 30 toward the front surface 30A of the substrate 31.
[0087] Specifically, the front groove 61 extends along the third axis Z to the contact surface 65, and the rear groove 62 extends along the third axis Z to the contact surface 65.
[0088] In fact, the contact surface 65 defines a front groove 61 at the bottom and a rear groove 62 at the top.
[0089] In this embodiment, the front trench 61 extends through the thickness of the epitaxial multilayer 31 and extends with respect to the thickness of the substrate 30. In other words, in this embodiment, the contact surface 65 extends within the substrate 30.
[0090] In this embodiment, the width of the front groove 61 (i.e., in) Figure 4B The width (measured along the first axis X) in the cross-section decreases from the upper surface 31A to the contact surface 65. For example, the sidewalls of the front groove 61 may have a slope of less than 60°, as shown below. Figure 7B It was discussed in detail.
[0091] Specifically, the front groove 61 has a width W at the upper surface 31A of the epitaxial multilayer 31. G,t It is between, for example, 15 μm and 100 μm, and has a width W at 65 on the contact surface. G,b The width W G,b Less than width W G,t And for example, it is between 10μm and 95μm.
[0092] As discussed below, the profile (depth and width trend) along the third axis Z of the front groove 61 indicates the specific manufacturing process used to form the front groove 61.
[0093] In one embodiment, the outer groove 25 and the front groove 61 may have the same profile; this can allow for simplification and reduction of manufacturing costs.
[0094] The rear groove 62 has a width W at the contact surface 65, measured along the first axis X. S Width W S Unlike the width W of the front groove 61 G,b In this embodiment, the width W of the rear groove 62 S Width W less than the front groove 61 G,b .
[0095] This allows for good contact between the front groove 61 and the rear groove 62.
[0096] width W S may for example be comprised between 8 pm and 93 pm.
[0097] Depending on the process used to form the back trench 62, the width of the back trench 62 measured along the first axis X can present a decreasing or substantially constant trend along the third axis Z from the back surface 30B towards the contact surface 65.
[0098] The first and second contact portions 50B, 50C of the source region 50 extend within the front trench 61.
[0099] In detail, the first contact portion 50B extends on the contact surface 65 and also coformally with the sidewalls of the front trench 61. This can ensure that the first contact portion 50B of the source region 50 is continuous between the contact surface 65 and the respective functional portion 50A and thus a good electrical connection.
[0100] The back metallization region 70, comprising one or more layers (e.g. Au, Cu, Al, AlCu, AlSiCu and other metallic materials), extends on the back side of the die 21.
[0101] In detail, on the contact surface 65, the back metallization region 70 extends on the back surface 30B of the substrate 30 and within the back trench 62. The back metallization region 70 can coformally extend on the sidewalls of the back trench 62 to obtain a good electrical connection.
[0102] The back metallization region 70 is in contact with the first contact portion 50B of the source region 50 within the front trench 61.
[0103] The back metallization region 70 can be used as a contact electrode to bias the source region 50.
[0104] An insulating layer can extend on the front side of the die 41, e.g. for optimizing the electrical performance of the HEMT device 20, for passivation of the HEMT device 20 and / or for other reasons related to the manufacturing of the HEMT device 20 (e.g. used as growth, deposition and / or etching mask).
[0105] A sealing layer 72, e.g. of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride, can have a portion 72B which extends in the active region 23 (i.e. inside the inner sealing ring 27 Figure 4B ), on the upper surface 31A on the side of the functional portion 52A of the gate region 52 and partially on the contact portion 50A of the source region 50 and on the contact portion 51A of the drain region 51. The sealing layer can also have a portion 72A on the upper surface 31A which extends outside the active region 23 Figure 4A ), i.e. outside the inner sealing ring 27.
[0106] The insulating layer 73, e.g. silicon nitride or silicon oxide, can have a portion 73B extending over the portion 72B of the sealing layer 72 inside the inner sealing ring 27 and over the portion 72A of the sealing layer 72 outside the inner sealing ring 27.
[0107] The insulating layer 74, e.g. TEOS, silicon oxide or silicon nitride, can have a portion 74B extending over the die 21 inside the inner sealing ring 27, e.g. in the active region 23 over portions of the source 50, drain 51 and gate 52 regions Figure 4B ); and a portion 74A extending over the die 21 outside the inner sealing ring 27 over the insulating layer 73 or directly over the epitaxial multilayer 31. Figure 4A
[0108] As can be seen in Figure 4A , the inner sealing ring 27 extends along the third axis Z through the entire thickness of the insulating layer 72, the insulating layer 73, the insulating layer 74 up to the upper surface 31A of the epitaxial multilayer 31. The stack 42 forming the inner sealing ring 27 is an interruption of the insulating layer 72, the insulating layer 73, the insulating layer 74. In other words, the portions 72B, 73B, 74B of the insulating layer 72, the insulating layer 73, the insulating layer 74 arranged inside the inner sealing ring 27 (towards the center of the die 21 in the view of Figure 3 ) are separated by the portions 72A, 73A, 74A of the insulating layer 72, the insulating layer 73, the insulating layer 74 arranged outside the inner sealing ring 27 (towards the outer periphery of the die 41).
[0109] In detail, the insulating layer 74 can also extend within the outer trench 25 forming the outer sealing ring 25, such as conformally on the walls of the trench 25.
[0110] A further insulating layer 75, e.g. silicon nitride and / or polyimide and polyamide, can extend over the insulating layer 74 and the second contact portions 50C, 51C, e.g. in such a way that an upper passivation layer of the HEMT device 20 is formed.
[0111] The HEMT device 20 can further comprise a field plate region 80 of an electrically conductive material, e.g. the same material as the portions 50B, 51B, extending in the active region 23 between the source region 50 and the drain region 51 over the upper surface 31 (at a distance from the upper surface 31). For example, in Figure 4B , the field plate region 80 extends over the insulating layer 73.
[0112] The source contact region 60 gives the HEMT device 20 a good electrical connection of the source region 50 (such as for RF applications) as well as a high reliability.
[0113] Furthermore, the presence of the outer and inner sealing rings allows to further improve the reliability of the HEMT device 20.
[0114] In the following the manufacturing process steps of the HEMT device 20 are described with reference to the cross-sections of Figure 4A and Figure 4B .
[0115] In detail, Figures 5A to 11A the subsequent manufacturing steps of the portion of the sealing ring region shown in Figure 4A are shown, and Figures 5B to 11B the subsequent manufacturing steps of the portion of the active region 23 shown in Figure 4B are shown.
[0116] Therefore, in the description of the manufacturing process, elements common to those already described with reference to Figure 4A and 4B are indicated with the same reference numerals and are not further described in detail.
[0117] Figure 5A and Figure 5B shows a workpiece 100 comprising a wafer 130, for example formed of one or more layers of silicon, silicon carbide, gallium nitride (GaN), sapphire (AI2O3) or other materials. In this embodiment, the wafer 130 is of a semiconductor material, for example silicon or silicon carbide.
[0118] The wafer 130 has a front surface 130A and a back surface 130B opposite to each other.
[0119] The wafer 130 is intended to form the substrate 30.
[0120] An epitaxial multilayer 31 has been grown on the wafer 130.
[0121] Furthermore, a contact region 43( Figure 5A ) as well as functional portions 50A, 51A and 52A( Figure 5B ) of the source 50, drain 51 and gate 52 regions have been formed on the epitaxial multilayer 31, respectively.
[0122] The region 43 and the portions 50A, 51A can be formed starting from the same metal layer, for example by deposition and subsequent selective removal or by mask deposition and lift-off.
[0123] Still with reference to Figure 5A and Figure 5B , a working sealing layer 133, for example of aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, intended to form the sealing layer 72, is formed on the front side of the workpiece 100.
[0124] Subsequently, Figure 6A and Figure 6B An insulating layer 73 is formed on the working sealing layer 133. For example, the insulating layer 73 can be formed by blanket deposition and subsequent masking, lithography and etching steps.
[0125] At the portions of the semiconductor heterostructure 33 intended to form respectively the outer trench 25 Figure 4A and the front trench 61 Figure 4B , two openings 135, 136 are formed through the insulating layer 73 and the working sealing layer 133.
[0126] The opening 135, the opening 136 expose the upper surface 31A of the epitaxial multilayer 31.
[0127] Then, Figure 7A and 7B The outer trench 25 is formed within the opening 135 and the front trench 61 is formed within the opening 136.
[0128] In detail, a mask 140 of a material that can be patterned for example by lithography (such as photoresist) is formed on the working body 100. The mask 140 has two windows 137, 138 within the opening 135 and the opening 136 respectively.
[0129] As a first approximation, the window 138 can have along the first axis X a width W G,t ( Figure 4B ) described with reference to the front trench 61.
[0130] As a first approximation, the window 137 can have along the first axis X a width W SR,t ( Figure 4A ) described with reference to the outer trench 25.
[0131] To form the outer trench 25 and the front trench 61, an etchant configured to remove the material forming the epitaxial multilayer 31 is used to remove (etch) the epitaxial multilayer 31 within the window 137, the window 138.
[0132] For example, in case the epitaxial multilayer 31 comprises GaN-based materials, the etchant can be a chlorine-based mixture.
[0133] The removal of the epitaxial multilayer 31 can be a plasma-mediated etching in an environment comprising CI2, BCI3 and Ar.
[0134] The use of BCI3 can allow to control the etching rate and the slope of the sidewalls 145, 146 of the trenches 25, 61. Increasing the BCI3 concentration allows to decrease the etching rate and to decrease the slope of the sidewalls 145, 146 (i.e. it allows to obtain trenches with a greater difference between the upper width at the surface 31A and the lower width at the surface 40, the surface 65).
[0135] The use of Ar allows to control the etching rate, the selectivity of the etching to the mask 140 and the profile of the trench 25, 61. Increasing the Ar concentration allows to increase the selectivity to the mask 140 and to increase the slope of the sidewalls 145, 146 (i.e. it allows to obtain a trench having a more uniform width along the third axis Z; in other words, it allows to obtain a smaller difference between the upper width at the surface 31A and the lower width at the surface 40, 65).
[0136] In one embodiment, the etchant can be adjusted so that the sidewalls 145, 146 form an angle a in a direction parallel to the first axis X which is less than 60°, the angle a being comprised between 30° and 60°.
[0137] The etching time can be chosen as a function of the thickness of the epitaxial multilayer 31 and of the desired thickness of the trench 25, 61.
[0138] For example, the fact that the trench 25, 61 is formed so that the surface 40, 65 extends within the wafer 130 can ensure the complete removal of the epitaxial multilayer 31 and thus optimize the manufacturing of the present HEMT device. For example, in the case where the wafer 130 is silicon, the portion of the trench 25, 61 which extends within the wafer 130 can be over-etched by the openings 137, 138, with the same etchant as the one used to remove the epitaxial multilayer 31, with respect to the etching time required to remove the epitaxial multilayer 31. For example, in the case where the wafer 130 is silicon carbide, the portion of the trench 25, 61 which extends within the wafer 130 can be formed from the back.
[0139] The mask 140 is then removed.
[0140] In this embodiment, the same mask 140 is used to form the external trench 25 and the front trench 61. This allows to obtain a good uniformity of the thickness and width between the external trench 25 and the front trench 61 across the entire die 21 and between the different dies obtained by dicing the workpiece 100.
[0141] Moreover, the fact that the same etching mask 140 is used to form the external trench 25 and the front trench 61 allows to form the external trench 25 and the front trench 61 simultaneously (in other words, with the same etching step). Thus, the external trench 25 and the front trench 61 can have the same profile (same depth along the third axis Z and same slope of the sidewalls 145, 146).
[0142] Then, as Figure 8A , Figure 8BAs shown, a metal layer 150 is deposited and patterned to form the middle region 44 of the inner seal ring 27, the first contact portion 50B of the source 50 and drain 51 regions, the contact portion 51B, and in this embodiment also the field plate region 80.
[0143] The slope of the sidewall 146 of the front trench 61 being lower than 60° can ensure good continuity of the metal layer 150 between the contact surface 65 and the functional portion 50A within the front trench 61.
[0144] Subsequently, Figure 9A , Figure 9B An insulating layer 74 is formed on the workpiece 100, for example by deposition, lithography and etching steps. The slope of the sidewall 145 of the outer trench 25 being lower than 60° can ensure good continuity of the insulating layer 74 between the lower surface 40 and the upper surface 31A.
[0145] In Figure 10A and 10B , a metal layer 151 is deposited on the workpiece 100 and patterned to form the upper region 45 of the inner seal ring 27 and the second contact portion 50C of the source 50 and drain 51 regions, the second contact portion 51C.
[0146] Still referring to Figure 10A , Figure 10B A passivation layer 75 is formed on the front side of the workpiece 100.
[0147] Subsequently, Figure 11A , Figure 11B The wafer 130 is thinned from the back surface 130B until a thickness of, for example, between 40 pm and 120 pm is obtained, as previously discussed with respect to the substrate 30. The thinning can be optional. The thinning can be useful in case the HEMT device 20 is used for RF applications.
[0148] A mask 160 is formed on the back surface 130B of the wafer. The mask 160 has a window 162 that exposes a portion of the wafer 130 below the contact surface 65.
[0149] The width of the window 162 is smaller than the width of the window 138 Figure 7B ).
[0150] A back trench 62 is formed by removing the portion of the wafer 130 exposed by the mask 160 from the back surface 130B up to the contact surface 65. For example, in case the wafer 130 is silicon or silicon carbide, a fluorine-based etchant can be used to remove the wafer 130.
[0151] The windows 138 and 162 of the masks 140 and 160, respectively, are not self-aligned to each other. Therefore, the fact that the width of the window 162 (formed after the mask 140) is smaller than the width of the window 138 allows to compensate possible lithography misalignments in the formation of the masks 140, 160 to obtain a good alignment between the trenches 61, 62 and, thus, a good electrical connection between the portion 50B of the source region 50 and the back metallization layer 70.
[0152] For example, in order to thin the wafer 130 and form the back trenches 62, a temporary support (not shown here) can be bonded to the front side of the workpiece 100.
[0153] Subsequently, the back metallization layer 70 is deposited on the back side of the workpiece 100, on the back surface 130B and within the back trenches 62 by means not shown here.
[0154] Finally, next are final manufacturing steps, not shown here and known per se, such as dicing the workpiece 100 and forming electrical connections, thereby obtaining the HEMT device 20.
[0155] The fact that the source contact region 60 is formed by removing the material forming the epitaxial multilayer 31 from the front side of the workpiece 100 and the material forming the wafer 130 from the back side of the workpiece 100 allows to accurately control the formation of the front trenches 61 and the back trenches 62.
[0156] In fact, both the epitaxial multilayer 31 and the wafer 130 can be removed using a highly selective etchant, such as when the semiconductor heterostructure 33 is based on layers containing GaN.
[0157] In detail, such as when the wafer 130 is silicon or silicon carbide, the etchant used to remove the wafer 130 can have a high selectivity with respect to the metallic material forming the first contact portion 50B of the source region 50 within the front trenches 61, such as if based on aluminum. Therefore, the formation of the source contact region 60 can thus have a lower risk of damaging the metallic region within the front trenches 61.
[0158] Therefore, the formation of the source contact region 60 can have a high yield.
[0159] Moreover, in the shown embodiment, the front trenches 61 and the external trench 25 can be formed simultaneously using the same mask 140. This allows to optimize the number of manufacturing steps for forming the external sealing ring 25 and the source contact region 60. Therefore, the HEMT device 20 can have a lower manufacturing cost and a higher manufacturing yield.
[0160] Finally, modifications and changes to the HEMT device and to the manufacturing process thereof described and illustrated herein can be made without departing from the scope of the present disclosure.
[0161] For example, the front trench 61 can be formed after the back trench 62. In this case, the width of the front trench 61 can be smaller than the width of the back trench 62.
[0162] The outer trench 25 and the front trench 61 can be formed using two different masks and / or etching steps.
[0163] Depending on the specific design layout, the front trench 61 and the back trench 62 can have equal or different tendencies along the second axis Y from each other. For example, the front trench 61 and / or the back trench 62 can extend in the shape of an elongated stripe along the second axis Y, or they can have different shapes.
[0164] The source contact region 60 can be one of a plurality of source contact regions.
[0165] In an alternative embodiment, the back contact region can be used to contact different conductive regions of the present transistor device from the back, e.g. to contact the drain region 51 instead of the source region 50. In this case, the first contact portion 51B of the drain region 51 can extend within the front trench 61.
[0166] For example, the source region 50 and the drain region 51 can have different numbers of contact portions, depending on the number of interconnection metal layers of the HEMT device.
[0167] Depending on the specific application, the top view layout of the source, drain and gate regions can be different from Figure 3 what is shown.
[0168] The functional portions 50A, 51A of the source region 50 and the drain region 51 can also extend within the semiconductor heterostructure 33.
[0169] The contact surface 65 of the source contact region 60 can also not extend within the substrate 30; for example it can extend within the epitaxial multilayer 31 or at the front surface 30A of the substrate 30.
[0170] For example, the inner sealing ring 27 and / or the outer sealing ring 25 can be absent.
[0171] Finally, the different embodiments described above can be combined to provide further solutions.
[0172] A process of manufacturing a heterostructure-based transistor device (20) starting from a workpiece (100) which is summarized to comprise a wafer (130) having a front surface (130A) and a back surface (130B) and an epitaxial multilayer (31) extending on the wafer along a first direction (Z) from the front surface of the wafer up to an upper surface (31A), the manufacturing process comprising: forming an active region (23) including forming a first electrically conductive region (50A) of electrically conductive material on the epitaxial multilayer; and forming a contact region (60) for biasing the first electrically conductive region, wherein forming the contact region comprises: forming a front trench (61) in the workpiece (100) starting from the upper surface (31A) of the epitaxial multilayer towards the back surface (130B) of the wafer up to a contact surface (65); forming on the contact surface (65) an electrically conductive region (50B, 50C) extending within the front trench (61) and in electrical contact with the first electrically conductive region (50A); forming a back trench (62) in the workpiece (100) starting from the back surface (130B) of the wafer (130) towards the upper surface of the epitaxial multilayer up to the contact surface; and forming on the contact surface a back metallization layer (70) on the back surface of the wafer and within the back trench.
[0173] Forming the front trench comprises forming a first etch mask (140) having a window (138) on the upper surface (31A) of the epitaxial multilayer (31), the window (138) having a first width (W G,t ) along a second direction (X) transverse to the first direction (Z), and forming the back trench (62) comprises forming a second etch mask (160) having a window (162) on the back surface (130B) of the wafer (130), the window (162) having a second width (W S ) along the second direction (X) different from the first width.
[0174] The front trench (61) is formed before the back trench (62), the first width being greater than the second width.
[0175] The manufacturing process further comprises forming an outer seal ring (25) around the active region (23), wherein forming the outer seal ring comprises forming an outer trench (25) in the workpiece (100) starting from the upper surface (31A) of the epitaxial multilayer towards the back surface (130B) of the wafer up to a lower surface (40).
[0176] The outer trench (25) and the front trench (61) are formed using the same etch mask (140).
[0177] The front trench (61) extends along the first direction (Z) through a thickness of the epitaxial multilayer (31).
[0178] The contact surface (65) is arranged within the wafer (130).
[0179] The front trench (61) has a width measured along a second direction (X) transverse to the first direction (Z) that decreases from the upper surface (31A) towards the contact surface (65).
[0180] The front trench (61) has a side wall (146) forming an angle (a) between the side wall and a direction parallel to the second direction (X) transverse to the first direction (Z) that is less than 60°.
[0181] The epitaxial multilayer (31) comprises a GaN-based semiconductor heterostructure (33).
[0182] The wafer (130) is of a semiconductor material, for example silicon or silicon carbide.
[0183] A heterostructure-based transistor device (20) is summarized as comprising: a die (21) comprising a substrate (30) having a front surface (30A) and a back surface (30B), and an epitaxial multilayer (31) extending on the substrate along a first direction (Z) from the front surface of the substrate up to an upper surface (31A); an active region (23) comprising a first conductive region (50A) of electrically conductive material on the epitaxial multilayer; and a contact region (60) for biasing the first conductive region, wherein the contact region comprises a front trench (61) extending in the die (21) from the upper surface (31A) of the epitaxial multilayer towards the back surface (30B) of the substrate up to a contact surface (65); a conductive region (50B, 50C) extending on the contact surface (65) within the front trench (61) and in electrical contact with the first conductive region; a back trench (62) extending in the die (21) from the back surface (30B) of the substrate (30) towards the upper surface of the epitaxial multilayer up to the contact surface (65); and a back metallization layer (70) extending on the contact surface on the back surface (30B) of the substrate and within the back trench.
[0184] The front trench (61) has a first width (W G,t , for example between 15 pm and 100 pm, along a second direction (X) transverse to the first direction (Z) at the upper surface (31A), and a second width (W G,b , for example between 10 pm and 95 pm, along the second direction at the contact surface (65).
[0185] The device also comprises an outer sealing ring (25) extending around the active area (23) and comprising an outer trench in the die extending from the upper surface (31 A) of the epitaxial multilayer towards the back surface (30B) of the substrate (30) up to the lower surface (40), the outer trench having the same profile as the front trench (61), for example the same depth and the same slope of the sidewalls.
[0186] The device is for radio frequency applications and the substrate has a thickness along the first direction (Z) between 40 pm and 120 pm.
[0187] The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification are hereby incorporated by reference, in their entireties. If a definition set forth in various patents, applications, and publications is inconsistent with a definition set forth in this specification, the definition set forth in this specification prevails.
[0188] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the used terms are not to be interpreted as limiting the claims to the specific embodiments disclosed in the specification and the claims, but rather to include all possible embodiments and the full scope of equivalents to which such claims are entitled. The claims are not to be limited to the embodiments disclosed in this disclosure.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises: a die comprising a substrate having a front surface and a back surface and an epitaxial multilayer on the substrate extending from the front surface of the substrate along a first direction up to an upper surface; an active region comprising a first conductive region of conductive material on the epitaxial multilayer; and a contact region for biasing the first conductive region, wherein the contact region comprises: a front trench extending in the die from the upper surface of the epitaxial multilayer towards the back surface of the substrate up to a contact surface; a conductive region extending on the contact surface within the front trench and in electrical contact with the first conductive region; a back trench extending in the die from the back surface of the substrate towards the upper surface of the epitaxial multilayer up to the contact surface; and a back metallization layer extending on the contact surface on the back surface of the substrate and within the back trench.
2. The semiconductor device according to claim 1, wherein The front trench has a first width along a second direction transverse to the first direction at the upper surface comprised between 15 pm and 100 pm and a second width along the second direction at the contact surface comprised between 10 pm and 95 pm, the second width being smaller than the first width.
3. The semiconductor device of claim 1, wherein The semiconductor device further comprises an outer sealing ring extending around the active region and comprising an outer trench extending in the die from the upper surface of the epitaxial multilayer towards the back surface of the substrate up to a lower surface, the outer trench having the same profile as the front trench and the same depth and the same slope as the side wall.
4. The semiconductor device of claim 1, wherein The semiconductor device is for radio frequency applications and wherein the substrate has a thickness along the first direction comprised between 40 pm and 120 pm.
5. A semiconductor device, characterized by, The semiconductor device comprises: a die having an active region and a substrate, the substrate comprising a first surface and a second surface opposite to the first surface; an epitaxial multilayer on the first surface of the substrate, the epitaxial multilayer extending in a first direction from the first surface of the substrate to an upper surface; and a trench extending in the first direction through the epitaxial multilayer and partially within the substrate to a lower surface, the trench having a first width along a second direction at the upper surface and a second width along the second direction at the lower surface.
6. The semiconductor device according to claim 5, wherein The first width is comprised between 10 pm and 100 pm and the second width is smaller than the first width.
7. The semiconductor device of claim 5, wherein, The epitaxial multilayer has a thickness between the first surface and the upper surface comprised between 1.5 pm and 5 pm.
8. The semiconductor device of claim 5, wherein, The trench comprises a side wall, a width of the side wall decreasing along the second direction from the upper surface towards the lower surface.
9. The semiconductor device of claim 8, wherein, The side wall has a slope lower than 60°.