Power tube
By introducing an interleaved third metal layer and a redistribution structure into the integrated circuit, the problem of uneven current density in the power transistor was solved, resulting in a more uniform current distribution and lower on-resistance, thus improving the performance of the power transistor.
Patent Information
- Application Number
- CN202423173747.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2034-12-23
AI Technical Summary
The uneven current density distribution of power transistors in existing integrated circuits leads to performance degradation, especially the excessive current pressure on the first and second metal lines, which fails to meet design requirements.
An interleaved third metal layer is used, and the source and drain regions of the power transistor are connected by at least four third metal lines. An interleaved redistribution structure is set on the redistribution layer to form a grid-like connection, which reduces the pressure of current passing through the first and second metal layers and distributes the current density evenly.
This results in a more uniform current density distribution in the power transistor, reduced on-resistance, improved power transistor efficiency, and a current density distribution closer to design requirements.
Smart Images
Figure CN223816406U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to integrated circuit technical field, especially a kind of power tube. BACKGROUND
[0002] In integrated circuit, the pipe with high power characteristic when working can be called power tube, for example, the pipe in circuit as final stage output. In existing integrated circuit technology, most can integrate high-power power tube in integrated circuit chip and carry out overall packaging.
[0003] Take low-voltage power tube as an example, the source area S and drain area D of power tube are staggered, and the source area S and drain area D are separated by polysilicon strip. First metal layer, second metal layer are sequentially arranged on the source area S and drain area D. The first metal layer includes a plurality of first metal lines arranged in parallel and at equal intervals, which correspondingly cover and connect the source area S and drain area D of the power tube. The second metal layer includes a plurality of second metal lines arranged in parallel and at equal intervals, which correspondingly cover and connect the plurality of first metal lines. When the current pressure on the first metal line and the second metal line is large, the problem of performance degradation of the power tube due to uneven current density distribution will occur.
[0004] The current density that the first metal line and the second metal line can bear is 1mA / um. Taking the current requirement of the power tube as 0.5A, the width of the polysilicon strip as 150um, and the number of the polysilicon strip as 200 as an example, the width of the first metal line is only 0.44um at the widest, and the width of the second metal line is only 0.66um at the widest, resulting in that the current pressure of the first metal line and the second metal line is too large (i.e. the actual current density borne is much larger than the current density that it can bear), the current density of the power tube is unevenly distributed, and the performance of the power tube is affected.
[0005] Therefore, a new power tube needs to be proposed to solve the above problems. SUMMARY
[0006] In view of the above problems, the purpose of the utility model is to provide a kind of power tube, so that the current density distribution and on-resistance of power tube can be improved.
[0007] According to one aspect of the utility model, provide a kind of power tube, including multiple first active region and multiple second active region, located above semiconductor substrate;First metal layer, second metal layer and third metal layer, sequentially set in multiple first active region and multiple second active region above, first metal layer includes multiple first metal lines spaced apart along first direction, each first active region is connected with a first metal line, each second active region is connected with a first metal line, second metal layer includes multiple second metal lines spaced apart along first direction, multiple second metal lines are connected one by one with multiple first metal lines, third metal layer includes at least four third metal lines spaced apart along second direction, at least four third metal lines are connected with first active region and second active region.
[0008] Optionally, the at least four third metal lines are parallel and equally spaced.
[0009] Optionally, the spacing between adjacent two third metal lines is 4um.
[0010] Optionally, the length and width of the at least four third metal lines are equal.
[0011] Optionally, the first direction is perpendicular to the second direction.
[0012] Optionally, the first direction and the second direction are arranged at an oblique angle.
[0013] Optionally, the number of the at least four third metal lines is even, and the number of third metal lines connected to the first active region is equal to the number of third metal lines connected to the second active region.
[0014] Optionally, the power tube further comprises a redistribution layer disposed above the third metal layer, the redistribution layer comprises first redistribution structure and second redistribution structure spaced apart, the first redistribution structure is connected with the first active region and first voltage terminal, the second redistribution layer is connected with the second active region and second voltage terminal, the redistribution layer and the third metal layer are connected by PAD via hole.
[0015] Optionally, the first redistribution structure and the second redistribution structure are spaced apart and parallel to each other, and the first redistribution structure and the second redistribution structure extend in opposite directions of the region spaced apart from each other.
[0016] Optionally, the plurality of first active regions and the plurality of second active regions are arranged in a staggered strip array, the first active regions and the second active regions are spaced by polysilicon strips, each first metal line covers a corresponding first active region or a corresponding second active region, and each second metal strip covers a corresponding first metal line.
[0017] The power tube provided by the utility model, comprising a plurality of first active regions and a plurality of second active regions located above a semiconductor substrate, a first metal layer, a second metal layer and a third metal layer arranged above the first active region and the second active region in sequence, the first metal layer comprises a plurality of first metal lines arranged at intervals along a first direction, each first active region is connected with a first metal line, each second active region is connected with a first metal line, the second metal layer comprises a plurality of second metal lines arranged at intervals along the first direction, the plurality of second metal lines are connected with the plurality of first metal lines one by one, and the third metal layer comprises at least four third metal lines arranged at intervals along a second direction, the at least four third metal lines are connected with the first active regions and the second active regions in a staggered mode, so that the current density of the first metal lines and the second metal lines can be reduced, the current density distribution of the power tube is more uniform, and the on-resistance of the power tube can be reduced. BRIEF DESCRIPTION OF DRAWINGS
[0018] The above and other objects, features and advantages of the present utility model will become more apparent from the following description of the utility model embodiments referring to the accompanying drawings. In the drawings:
[0019] Figure 1 A structural schematic diagram of a power tube is shown;
[0020] Figure 2 A structural schematic diagram of a power tube according to an embodiment of the utility model is shown. DETAILED DESCRIPTION
[0021] Various embodiments of the present utility model will be described in more detail below with reference to the accompanying drawings. In each drawing, the same elements or modules are denoted by the same or similar reference numerals. For the sake of clarity, each part in the drawings is not drawn to scale.
[0022] It should be understood that, in the following description, "circuitry" can include a single or multiple combinations of hardware circuitry, programmable circuitry, state machine circuitry, and / or elements that can store instructions for execution by the programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there are no intervening elements present.
[0023] Also, various terminology can be used in the present patent document and claims to refer to particular components. As one skilled in the art will appreciate, different companies can refer to a component by different names and / or different numbering schemes. Reference to a component by a particular terminology does not foreclose reference to the component by another terminology. Additionally, terminology can evolve between time periods and / or across different technologies. As such, reference to a component by a particular terminology employed in a secondiary document can not foreclose reference to the component by another terminology employed in a first document.
[0024] In addition, it should be noted that terminology of relation such as first and second are used herein only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.
[0025] Figure 1 A structural diagram of a power tube is shown; see Figure 1 The power tube 100 includes a plurality of source regions S and a plurality of drain regions D above a semiconductor substrate (not shown in the figure), which are arranged in an interlaced strip array, and adjacent source regions S and drain regions D are separated by polysilicon strips.
[0026] The power transistor 100 further comprises a first metal layer metal1 (not shown in the figure), a second metal layer metal2 (not shown in the figure) and a third metal layer metal3, which are sequentially arranged above the source regions S and the drain regions D. The first metal layer metal1 comprises a plurality of first metal lines arranged equidistantly and in parallel along the first direction, each of which corresponds to and covers each of the source regions S and each of the drain regions D. The second metal layer metal2 comprises a plurality of second metal lines arranged equidistantly and in parallel along the first direction, each of which corresponds to and covers each of the first metal lines. The first metal lines and the second metal lines are electrically connected through vias 12 (not shown in the figure). The third metal layer metal3 comprises two third metal lines 110 and 120 arranged equidistantly and in parallel along the second direction, which are spaced apart from each other and have equal length and width. The second metal layer metal2 is electrically connected to the third metal layer metal3 through vias 23. The third metal line 110 connects the drain regions D of the power transistor 100 together to form the drain electrode of the power transistor 100, and the third metal line 120 connects the source regions S of the power transistor 100 together to form the source electrode of the power transistor 100. The second direction is perpendicular to the first direction.
[0027] The power transistor 100 further comprises a redistribution layer RDL, which comprises a first redistribution structure 130 and a second redistribution structure 140. The first redistribution structure 130 is electrically connected to the drain electrode of the power transistor 100 and the first voltage terminal A through a plurality of PAD vias. The second redistribution structure 140 is electrically connected to the source electrode of the power transistor 100 and the second voltage terminal B through a plurality of PAD vias.
[0028] In the design, the first redistribution structure 130 and the second redistribution structure 140 can cover as much of the third metal layer metal3 as possible, and a plurality of PAD vias can be arranged between the third metal layer metal3 and the redistribution layer RDL. The shapes of the first redistribution structure 130 and the second redistribution structure 140 can be set according to the positions of the first voltage terminal A and the second voltage terminal B. For example, Figure 1 when the first voltage terminal A and the second voltage terminal B are spherical and located above the redistribution layer RDL, the first redistribution structure 130 and the second redistribution structure 140 can be set to the shapes as shown in Figure 1 to ensure that they can correctly connect the source electrode and the drain electrode of the power transistor 100 to the corresponding voltage terminals.
[0029] The area of the power tube 100 which is not covered by the third metal layer metal3, the current can only flow from the first metal layer metal1 and the second metal layer metal2, and the length of the first metal line and the second metal line carrying current reaches about 75um, which causes the first metal layer metal1 and the second metal layer metal2 to have large overcurrent pressure, and the area 150 between the third metal lines 110 and 120 is the area with the weakest current density, and the current pressure in the area of the via in the area is larger, and the current density distribution is more uneven.
[0030] Figure 2 A structure diagram of a power tube is shown according to an embodiment of the utility model.
[0031] Referring to Figure 2 , the power tube 200 includes a plurality of first active regions and a plurality of second active regions above a semiconductor substrate (not shown in the figure), the plurality of first active regions and the plurality of second active regions are staggered strip arrays, and the first active regions and the second active regions are spaced by polysilicon strips. Among them, the first active region is one of the source region S or the drain region D of a single power device, the second active region is the other one of the source region S or the drain region D in a single power device, and the polysilicon strip is the gate of a single power device.
[0032] The power tube 200 further includes a first metal layer metal1 (not shown in the figure), a second metal layer metal2 (not shown in the figure) and a third metal layer metal3 which are sequentially arranged above the first active region and the second active region. The first metal layer metal1 includes a plurality of first metal lines arranged at intervals along a first direction, each first active region is connected to a first metal line, and each second active region is connected to a first metal line. The second metal layer metal2 includes a plurality of second metal lines arranged at intervals along the first direction, and the plurality of second metal lines are connected to the plurality of first metal lines one by one. The first metal line and the second metal line are electrically connected by a via 12 (not shown in the figure). Each first metal line covers the corresponding first active region or second active region thereon, and each second metal line covers the corresponding first metal line thereon.
[0033] The third metal layer metal3 includes at least four third metal lines (only six third metal lines 211-216 are exemplarily shown in the figure) arranged at intervals along a second direction, Figure 2 The at least four third metal lines are alternately connected to the first active regions and the second active regions. For example, from top to bottom, the odd-numbered third metal lines are connected to one of the first active regions and the second active regions, and the even-numbered third metal lines are connected to the other one of the first active regions and the second active regions. The second metal layer metal2 and the third metal layer metal3 are connected by a via 23.
[0034] The power tube 200 further comprises a redistribution layer RDL disposed above the third metal layer metal3, and the redistribution layer RDL is electrically connected with the third metal layer metal3 through the PAD via hole. The redistribution layer RDL comprises a first redistribution structure 221 and a second redistribution structure 222 which are arranged at intervals, the first redistribution structure 221 is connected with the first voltage terminal A and the first active region of the power tube 200, and the second redistribution structure 222 is connected with the second voltage terminal B and the second active region of the power tube 200. The shape of the first redistribution structure 221 and the second redistribution structure 222 can be set according to the position of the first voltage terminal A and the second voltage terminal B. For example, Figure 2 When the first voltage terminal A and the second voltage terminal B are spherical and located above the redistribution layer RDL, the first redistribution structure 221 and the second redistribution structure 222 are arranged at intervals along the first direction, and the first redistribution structure 221 and the second redistribution structure 222 respectively extend to the direction opposite to the interval area between them, so as to ensure that the source and the drain of the power tube 100 can be correctly connected to the corresponding voltage terminal.
[0035] Optionally, the second direction is perpendicular to the first direction. For example, the first direction is transverse, and the second direction is longitudinal, the right side edge of the first redistribution structure 221 exceeds the edge of the rightmost first active region, and the left side edge of the second redistribution structure 222 exceeds the edge of the leftmost first active region.
[0036] Optionally, the second direction is arranged at an oblique angle with the first direction. For example, the second direction is arranged at an angle of 80° / 70° with the first direction.
[0037] Optionally, the number of the third metal lines is even, and the number of the third metal lines connected to the first active region is equal to the number of the third metal lines connected to the second active region.
[0038] Optionally, the width and the length of the at least four third metal lines are equal.
[0039] Optionally, the at least four third metal lines are arranged at equal intervals and in parallel.
[0040] For example, the width of the third metal line can be determined according to the size of the PAD via hole in the power tube 200 and the number of the PAD via holes in the second direction, and the number of the third metal lines and the interval between the adjacent two third metal lines can be determined according to the design rules of the power tube on the premise that the width of the third metal line is determined. For example, the size of the PAD via hole is a*a, the interval between the adjacent two PAD via holes is bum, and the third metal line needs to exceed the edge of the PAD via hole by bum, the width of the third metal line is N*a+(N+1)*b, wherein N represents the number of the PAD via holes in the second direction.
[0041] Optionally, the distance between two adjacent third metal lines in the power tube 200 is 4um.
[0042] In the power tube 200, the current mainly flows through each third metal line to the first metal layer and the second metal layer, the third metal layer is the main path of the current, and the first metal layer and the second metal layer have less overcurrent pressure and more uniform current density distribution.
[0043] Hereinafter, the current requirement of the power tube 100 and 200 is taken as 0.5A, the width of the adjacent polysilicon strip is taken as 150um, and the number of the polysilicon strips is taken as 200.
[0044] Table 1 shows the maximum current density actually required to be borne by each metal layer of the source end and the drain end of the power tube 100 and the power tube 200 respectively.
[0045] Table 1
[0046]
[0047] According to the design requirement of the power tube, the current density that can be borne by the metal layer metal1 / 2 is 1mA / um, and the current density that can be borne by the metal layer metal3 is 7mA / um. It can be seen from Table 1 that the maximum current density required to be borne by the metal layer metal1 / 2 / 3 of the source end of the power tube 100 is 1.82 / 3.21 / 4.7mA / um, and the maximum current density required to be borne by the metal layer metal1 / 2 / 3 of the drain end is 1.76 / 3.19 / 4.3mA / um, so the current density actually required to be borne by the metal layer metal1 / 2 of the source end and the drain end of the power tube 100 is greater than the current density that can be borne, which does not meet the design requirement of the power tube. The maximum current density required to be borne by the metal layer metal1 / 2 / 3 of the source end of the power tube 200 is 0.61 / 0.98 / 6.2, and the maximum current density required to be borne by the metal layer metal1 / 2 / 3 of the drain end is 0.58 / 0.96 / 6.04, so the metal layer metal1 / 2 / 3 of the source end and the drain end of the power tube 200 can meet the design requirement.
[0048] Table 2 shows the current density distribution of the first voltage end A and the second voltage end B connected with the power tube 100 and the power tube 200 respectively.
[0049] Table 2
[0050]
[0051] It can be seen from Table 2 that the current density of the first voltage end A and the second voltage end B connected with the power tube 200 is closer to 50%, and the current density distribution is more uniform.
[0052] Furthermore, this application connects the source and drain terminals of the power transistor using at least four third metal lines, creating a mesh-like connection between the source and drain terminals. This effectively reduces the metal connection resistance, thereby reducing the on-resistance Rdson of the power transistor 200 and improving its efficiency. This advantage is particularly pronounced when the source and drain terminals of the power transistor 200 are close together. Ideally... Figure 1 and Figure 2 The on-resistance Rdson of the power transistor shown is 0.06Ω. To verify the improvement effect of the power transistor 200 on the on-resistance Rdson of this application, the inventors of this application obtained the following through testing: Figure 1 The on-resistance Rdson of the power transistor 100 shown is 0.09Ω, while Figure 2 The on-resistance Rdson of the power transistor 200 shown is 0.073Ω. Therefore, the power transistor 200 provided in this embodiment can improve its on-resistance Rdson, making it closer to the ideal value.
[0053] The embodiments of this utility model described above are examples of specific examples, and do not exhaustively describe all details, nor do they limit the utility model to only specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to make good use of this utility model and its modifications. The scope of protection of this utility model should be determined by the scope defined by the claims of this utility model and their equivalents.
Claims
1. A power tube, characterized by, The application relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a plurality of first active regions and a plurality of second active regions above a semiconductor substrate; a first metal layer, a second metal layer and a third metal layer above the plurality of first active regions and the plurality of second active regions, the first metal layer comprises a plurality of first metal lines arranged at intervals along a first direction, each first active region is connected to a first metal line, and each second active region is connected to a first metal line, the second metal layer comprises a plurality of second metal lines arranged at intervals along the first direction, and the plurality of second metal lines are connected to the plurality of first metal lines one by one, 2. The power tube of claim 1, wherein, the third metal layer comprises at least four third metal lines arranged at intervals along a second direction, and the at least four third metal lines are connected to the first active regions and the second active regions alternately.
3. The power tube of claim 2, wherein, The at least four third metal lines are parallel and arranged at equal intervals.
4. The power tube of claim 1, wherein, The interval between two adjacent third metal lines is 4 um.
5. The power tube of claim 1, wherein, The length and width of the at least four third metal lines are equal.
6. The power tube of claim 1, wherein, The first direction is perpendicular to the second direction.
7. The power tube of claim 1, wherein The first direction and the second direction are arranged at an oblique angle.
8. The power tube of claim 1, wherein, The number of the at least four third metal lines is even, and the number of third metal lines connected to the first active regions is equal to the number of third metal lines connected to the second active regions. The semiconductor structure further comprises:
9. The power tube of claim 8, wherein, a redistribution layer above the third metal layer, the redistribution layer comprises first redistribution structures and second redistribution structures arranged at intervals, the first redistribution structures are connected to the first active regions and a first voltage terminal, the second redistribution structures are connected to the second active regions and a second voltage terminal, and the redistribution layer and the third metal layer are connected by PAD through holes.
10. The power tube of claim 1, wherein, The first redistribution structures and the second redistribution structures are arranged at intervals along the first direction, and the first redistribution structures and the second redistribution structures extend in opposite directions of the interval regions. The plurality of first active regions and the plurality of second active regions are arranged in a strip array alternately, the first active regions and the second active regions are separated by polysilicon strips, each first metal line covers a corresponding first active region or second active region, and each second metal line covers a corresponding first metal line.