Substrate layout structure for improving conversion efficiency of power supply module

Abstract

The utility model discloses a substrate layout structure for improving the conversion efficiency of a power supply module, which comprises a PCB (Printed Circuit Board), a circuit with four channels which are linearly arranged is adopted by a top layer bonding pad of the PCB, CLKIN and CLKOUT pins are arranged in two channels and are connected with each other, and corresponding devices of the circuit of the same channel are arranged in a centralized manner. According to the utility model, a large number of through holes and via holes are adopted, and a copper coating mode is adopted, so that the utilization rate of the substrate is optimal, and the loss and interference between wires and between wires and holes are reduced; the electrical connection of the product is realized, and the conversion efficiency of the product is improved.

Description

Technical Field

[0001] This utility model relates to a substrate layout structure for improving the conversion efficiency of a power module, and belongs to the field of power module technology. Background Technology

[0002] The XEC4644BS is an independent quad-output non-isolated switch-mode DC / DC power supply module. It has four independent channels, each capable of providing up to 4A of continuous output current, while requiring minimal external input and output capacitors. Each regulator provides a precisely adjustable output voltage over an input voltage range of 4V to 14V, with an adjustment range of 0.6V to 5.5V. With an external bias voltage, the module can operate at a low voltage of 2.375V.

[0003] The XEC4644BS integrates four independent constant-frequency valley-mode controllers, power MOSFETs, inductors, and other discrete components. The typical switching frequency is set to 1MHz. For applications sensitive to switching noise, the power module can be synchronized with an external clock ranging from 700kHz to 1.3MHz.

[0004] The XEC4644BS module employs current-mode control with built-in feedback loop compensation, providing sufficient stability margin and excellent transient performance. Furthermore, it offers a wide range of output capacitor values, maintaining good loop stability and transient performance even when all output capacitors are ceramic capacitors.

[0005] Current-mode control provides flexible parallel operation of individual channels with precise current distribution. The XEC4644BS features a built-in clock interleaving between every two channels, allowing for easy parallel operation in 2+2, 3+1, or 4-channel configurations, offering great flexibility in multi-track POL applications such as FPGAs. Furthermore, the XEC4644BS has CLKIN and CLKOUT pins for frequency synchronization or multi-device synchronization, allowing up to eight phases to cascade simultaneously.

[0006] Current-mode control also provides cycle-by-cycle fast current monitoring. It offers foldback current limiting under overcurrent conditions, reducing the inductor valley current to approximately 40% of its original value when VFB drops. An internal overvoltage or undervoltage comparator pulls the open-drain PGOOD pin output low if the output feedback voltage exceeds a window of ±10% near the setpoint. Continuous conduction mode (CCM) is forced into operation during overvoltage or undervoltage conditions, except during the initial rise of the TRACK pin voltage to 0.6V at startup.

[0007] Pulling the run pin below 1.1V will shut down the controller, simultaneously turning off the MOSFETs and most of the internal control circuitry. Under light load current, setting the mode pin to SGND allows operation in discontinuous conduction mode (DCM), which is more efficient than continuous conduction mode (CCM). The TRACK / SS pins are used for tracking and soft-start settings.

[0008] However, an unreasonable circuit layout can affect the conversion efficiency of the power module. Summary of the Invention

[0009] The technical problem to be solved by this utility model is to provide a substrate layout structure that improves the conversion efficiency of power modules, so as to solve the problems existing in the prior art.

[0010] The technical solution adopted by this utility model is as follows: a substrate layout structure for improving the conversion efficiency of a power module, including a PCB board, wherein the top pad of the PCB board adopts a circuit with four channels arranged linearly, and two channels are interconnected by CLKIN and CLKOUT pins, and the corresponding devices of the same channel circuit are placed in a concentrated manner.

[0011] Preferably, the soldering position of the top layer device in the above PCB board corresponds to the pin area of ​​the bottom layer.

[0012] Preferably, the chip pads on the PCB are connected to the substrate pads via gold wires.

[0013] Preferably, the top-level pads correspond to the channel positions of the bottom-level pin pads, the inductor package is 3mm*3mm, the product length and width are 9mm*15mm, and the size of the four inductors is 12mm.

[0014] Preferably, the signal connection layers of the above-mentioned substrate are connected by copper plating between the same signals, and the signal layers are connected by vias.

[0015] Preferably, the PCB board connection to the GND layer uses vias and through holes.

[0016] The beneficial effects of this utility model are as follows: Compared with the prior art, this utility model optimizes the utilization rate of the substrate by using a large number of through holes and copper plating, reducing losses and interference between lines and between lines and holes; while realizing the electrical connection of the product, it improves the conversion efficiency of the product. Attached Figure Description

[0017] Figure 1 This is a 5V input efficiency curve;

[0018] Figure 2 This is the efficiency curve for a 12V input.

[0019] Figure 3 It is a circuit schematic;

[0020] Figure 4 This is the product pinout diagram;

[0021] Figure 5 This is a diagram showing the layout of the chip pads;

[0022] Figure 6 This is a diagram of the gold wire connection on the front of the chip;

[0023] Figure 7 This is a diagram showing the connection of the gold wires on the back of the chip.

[0024] Figure 8 This is a schematic diagram of the device distribution in channel 1;

[0025] Figure 9 This is a layout diagram of the top layer pads of the channel;

[0026] Figure 10 This is a schematic diagram of the signal layer 1 connection;

[0027] Figure 11 This is a schematic diagram of the signal layer 2 connection;

[0028] Figure 12 This is a schematic diagram of the GND layer 1 layout;

[0029] Figure 13 This is a schematic diagram of the GND 2-layer layout;

[0030] Figure 14 This is a schematic diagram of the underlying layout;

[0031] Figure 15 This is a schematic diagram of the product's pin pads;

[0032] Figure 16 This is a 3D schematic diagram of the substrate. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0034] Example 1: As Figure 1-11 As shown, a substrate layout structure for improving the conversion efficiency of a power module includes a PCB board. The top layer pad of the PCB board adopts a circuit with four channels arranged linearly. Two channels are interconnected by CLKIN and CLKOUT pins. Corresponding devices of the same channel circuit are placed in a concentrated manner. The soldering position of the top layer device in the PCB board corresponds to the bottom layer pin area. The chip pads on the PCB board are connected to the substrate pads by gold wires.

[0035] From the circuit connection

[0036] As seen in the schematic diagram, this module has four channels, each arranged linearly and independently. The channels are only connected by the CLKIN and CLKOUT pins. Therefore, in terms of board layout, corresponding devices in the same channel should be placed together as much as possible to reduce mutual interference between channels.

[0037] 2. Device packaging

[0038] According to the component BOM, only the chip and inductor packages are relatively large, thus occupying a lot of substrate space. When considering the substrate layout, the position of the chip and inductor should be given priority. Then, the components should be laid out reasonably according to the connection situation and the component packages to effectively utilize the substrate layout, enhance space utilization, reduce component interference, and improve module efficiency.

[0039] 3. On the product pins

[0040] Based on the pin pads on the bottom of the product Figure 4 Starting from pin 1 and working downwards, the pads correspond to the pins of channels 1, 2, 3, and 4 in sequence. To shorten the routing path and reduce losses caused by excessively long lines, the soldering positions of the top-level components should be aligned with the pin areas of the bottom layers as much as possible. This will prevent excessive damage and interference between channels caused by cross-area wiring.

[0041] Table 1. Description of Lead-Out Terminals

[0042]

[0043] VOUT1 (A1, A2, A3), VOUT2 (C1, D1, D2), VOUT3 (F1, G1, G2), VOUT4 (J1, K1, K2): Power output pins. Apply an output load between these pins and the GND pin, and place output decoupling capacitors between these pins and the GND pin.

[0044] GND (A4-A5, B1-B2, C5, D3-D5, E1-E2, F5, G3-G5, H1-H2, J5, K3-K4, L1-L2): Power ground pins. Use a large area of ​​PCB copper to connect all GND pins together.

[0045] VIN1 (B3, B4), VIN2 (E3, E4), VIN3 (H3, H4), VIN4 (L3, L4): Power supply input pins. Connected to the drain of the power MOSFET inside each channel, an input voltage is applied between these pins and the GND pin. It is recommended to place an input decoupling capacitor between each VIN pin and the GND pin.

[0046] PGOOD1, PGOOD2, PGOOD3, PGOOD4 (C3, C2, F2, J2): Power supply output goodness indicators, open-drain logic output pins. PGOOD is pulled low to GND when the voltage on the FB pin is not within ±10% (typical) of the internal 0.6V reference voltage.

[0047] CLKOUT (J3): Clock output pin. Used for multi-phase output clock signal. The phase of CLKOUT relative to CLKIN is set to 180°. The peak-to-peak value of CLKOUT is INTVCC to GND. This is an output pin and should not be driven.

[0048] INTVCC1, INTVCC2, INTVCC3, INTVCC4 (C4, F4, J4, K5): Internal power supply output pins. The internal power driver and control circuitry are powered by this voltage. Each pin uses a 2.2μF low-ESR ceramic capacitor to GND as a decoupling capacitor.

[0049] SVIN1, SVIN2, SVIN3, SVIN4 (B5, E5, H5, L5): Bias input power supply. This is the input voltage for the internal 3.3V regulator, affecting the control circuitry of each channel. In most applications, this pin is typically connected to the VIN pin. The input voltage of SVIN should be greater than 4V and greater than the output voltage.

[0050] TRACK / SS1, TRACK / SS2, TRACK / SS3, TRACK / SS4 (A6, D6, G6, K6): Output tracking and soft-start pins. The user controls the rise time of the output voltage by setting this pin. Applying a voltage below 0.6V to this pin bypasses the internal reference input of the error amplifier, matching the FB pin to the TRACK voltage. Above 0.6V, the tracking function stops, and the internal reference resumes control of the error amplifier. The INTVCC pin on this pin has a typical internal pull-up current of 2.5μA, so placing a capacitor here provides soft-start functionality. This pin must not be left floating.

[0051] MODE1, MODE2, MODE3, MODE4 (B6, E6, H6, L6): Operating mode selection pins. Connecting this pin to INTVCC will force all outputs to operate in CCM mode; connecting it to SGND enables DCM mode operation under light load. This pin must not be left floating. DCM mode increases ripple; CCM mode is recommended.

[0052] RUN1, RUN2, RUN3, RUN4 (C6, F6, J6, K7): Enable input pins. Connecting the RUN pin above 1.6V enables the regulator. Pulling it low below 0.8V disables the corresponding regulator channel. This pin must not be left floating.

[0053] FB1, FB2, FB3, FB4 (A7, D7, G7, J7): Feedback pins (negative input pins of the error amplifier). Internally in the XEC4644BS, these pins are connected to VOUT of each channel via a 60.4kΩ precision resistor. Different voltage outputs can be achieved by connecting different external resistors between the FB and SGND pins. For multi-phase parallel operation, the FB pins are connected together for parallel operation.

[0054] COMP1, COMP2, COMP3, COMP4 (B7, E7, H7, L7): Current threshold control and stability compensation pins. The internal current comparator threshold is proportional to this voltage. Connecting the COMP pins together enables parallel operation; the device has internal compensation.

[0055] CLKIN (C7): External clock input pin. An external clock is input to the internal phase-locked loop (PLL) module. This pin is internally terminated to SGND with a 20kΩ impedance. The PLL forces the channel 1 turn-on signal to synchronize with the rising edge of the CLKIN signal. Channels 2, 3, and 4 will also synchronize with the rising edge of the CLKIN signal and have a set phase shift.

[0056] SGND (F7): Signal ground pin. SGND connects to the internal signal's GND. A separate SGND ground copper area is used as ground for the feedback resistor and other signals. It is recommended to make a secondary connection between the PGND and SGND planes on the bottom layer of the PCB.

[0057] TEMP(F3): Temperature sensing pin. Used to monitor the change in VBE junction voltage with temperature.

[0058] The chip is the main component of the product. The chip pads also need to be connected to the substrate pads via gold wires to achieve circuitry. The chip pads are located around the chip... Figure 5 The chips are arranged in a distributed manner, so their positions need to be fixed first. The placement of surrounding components depends on the chip's orientation, and the chip's circuit connection is as follows:

[0059] Table 2 Chip Pad Locations and Gold Wire Quantities

[0060]

[0061]

[0062]

[0063] Top-level layout: Based on the above layout requirements and chip connection scheme, the top-level pads should be arranged linearly according to the channels, corresponding to the channel positions of the bottom-level pin pads. The inductor package is 3mm*3mm, and the product dimensions are 9mm*15mm. The dimensions of the four inductors are 12mm. The placement of the inductors can only be sorted according to the length of the product. After determining the chip position and orientation, the connecting devices corresponding to the chip pin pads should be placed as close as possible to reduce losses.

[0064] Therefore, the placement area of ​​the corresponding device should be arranged according to the gold wire connection area of ​​the chip, such as... Figure 7 As shown, the inductors and chips are arranged in parallel to improve substrate utilization and shorten the connection distance between the chips and other devices, thus reducing losses. The layout of each channel is linearly distributed according to a single channel to determine the top-layer pad layout of the substrate.

[0065] Signal layer layout: The signal connection layer of the substrate is mainly used to realize the circuit connection between various devices. The connection lines are based on the principle of short connection distance and low interference between lines. In addition to the signal circuit connection, copper pouring is used to connect the same signals to enhance the stability of the connection between the same signals. The signal layers are connected by vias, which effectively utilizes space and reduces interference.

[0066] GND layer layout: The module is a power device, and each device will generate a lot of heat during operation. If this heat cannot be effectively dissipated, it will increase the module loss and have a significant impact on the module's conversion efficiency. In addition to being conducted to the module surface through the molding compound and then dissipated by subsequent heat dissipation measures, this heat can also be dissipated through the substrate layout design. This can be achieved by increasing the GND layer layout area of ​​the substrate, using more vias and through-holes, and then dissipating the heat through a large area of ​​copper plating before conducting the heat to the entire board through the module pins for diffusion. Bottom layer layout: The bottom pad layout of the module should correspond to the module pin pads, and copper plating should also be used between the same pads to increase the connection area.

[0067] The substrate utilizes numerous vias and copper plating to optimize its utilization, reducing losses and interference between lines and between lines and vias. This achieves electrical connectivity for the product while improving its conversion efficiency.

[0068] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A substrate layout structure for improving the conversion efficiency of a power module, characterized in that: The circuit board includes a PCB board. The top pad of the PCB board uses a linear arrangement of four channels. Two channels are connected to each other by CLKIN and CLKOUT pins. The corresponding components of the same channel circuit are placed together.

2. The substrate layout structure for improving the conversion efficiency of a power module according to claim 1, characterized in that: The soldering positions of the top-layer components on the PCB board correspond to the pin areas of the bottom layer.

3. The substrate layout structure for improving the conversion efficiency of a power module according to claim 1, characterized in that: The chip pads on the PCB are connected to the substrate pads via gold wires.

4. The substrate layout structure for improving the conversion efficiency of a power module according to claim 1, characterized in that: The top-level pads correspond to the channel positions of the bottom-level pin pads. The inductor package is 3mm*3mm, and the product dimensions are 9mm*15mm. The dimensions of the four inductors are 12mm.

5. The substrate layout structure for improving the conversion efficiency of a power module according to claim 1, characterized in that: The same signals on the substrate's signal connection layer are connected using copper plating, while signal layers are connected using vias.

6. The substrate layout structure for improving the conversion efficiency of a power module according to claim 1, characterized in that: Vias and through-holes are used at the GND layer connection of the PCB board.

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