Ceramic package substrate

Abstract

The utility model discloses a ceramic packaging substrate, which comprises a ceramic core plate, a rewiring structure, a solder mask, a first external bonding pad and a second external bonding pad, the ceramic core plate is provided with a first surface and a second surface which are opposite to each other, and a conductive through hole penetrating through the ceramic core plate; the re-wiring structure is arranged on the first surface, and the re-wiring structure is electrically connected with the conductive through hole; the solder mask layer covers the rewiring structure, and the solder mask layer is provided with an opening for exposing the metal wiring layer; the first external bonding pad is arranged at the opening and is electrically connected with the metal wiring layer; and the second external bonding pad is electrically connected with the conductive through hole on the second surface. The ceramic packaging substrate is good in heat dissipation effect and high in thermal expansion coefficient matching degree.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a ceramic packaging substrate. Background Technology

[0002] As semiconductor devices evolve towards higher power, higher frequency, and greater integration, higher demands are placed on the thermal conductivity of insulating substrates. The good matching of thermal expansion coefficients between ceramic substrates and copper foil effectively avoids thermal stress caused by temperature differences, ensuring the stability of the circuit board. Furthermore, the high thermal conductivity of ceramic substrates effectively dissipates heat, ensuring the stability of electronic products. This is particularly important for power semiconductor devices, as most of the heat they generate is dissipated through the packaging substrate; good thermal conductivity can prevent chip damage due to excessive temperature.

[0003] In related technologies, ceramic packaging substrates typically employ a symmetrical structure. Since heat is mainly concentrated on one side of the chip, the symmetrical structure cannot effectively guide the heat to dissipate quickly, leading to heat accumulation. Therefore, it is necessary to develop an asymmetrical ceramic packaging substrate. Utility Model Content

[0004] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, the objective of this invention is to provide a ceramic packaging substrate with good heat dissipation and a high degree of thermal expansion coefficient matching.

[0005] To achieve the above objectives, this utility model proposes a ceramic packaging substrate, which includes: a ceramic core board, a redistribution structure, a solder mask layer, a first external pad, and a second external pad.

[0006] The ceramic core plate has opposing first and second surfaces, and conductive through holes penetrating the ceramic core plate;

[0007] The rewiring structure is disposed on the first surface, and the rewiring structure is electrically connected to the conductive via.

[0008] The solder mask layer covers the redistribution structure, and the solder mask layer has an opening that exposes the metal wiring layer of the redistribution structure.

[0009] The first external pad is disposed at the opening and electrically connected to the metal wiring layer;

[0010] The second external pad is disposed on the second surface and electrically connected to the conductive via.

[0011] According to this utility model, a ceramic packaging substrate uses ceramic as the core material. Utilizing the high thermal conductivity of ceramic and its similar coefficient of thermal expansion to semiconductor materials, the problem of low thermal conductivity and mismatched coefficients of thermal expansion is effectively solved. Through an asymmetrical design where the redistribution structure is only set on one side of the ceramic substrate, heat from one side of the chip can be quickly conducted to the other side, greatly improving the heat dissipation of the ceramic substrate. This makes it suitable for packaging high-power, high-frequency, and high-performance semiconductor devices, avoiding frequency throttling caused by excessive temperature in high-performance computing processors, which leads to processor performance degradation and application service interruptions.

[0012] In addition, the ceramic packaging substrate proposed above according to this utility model may also have the following additional technical features:

[0013] Optionally, the ceramic core plate is further provided with positioning holes, which are located near the edge of the ceramic core plate.

[0014] Optionally, the conductive via is electrically connected to a first patterned circuit, and the redistribution structure includes at least one metal wiring layer and at least one dielectric layer, wherein the metal wiring layer is electrically connected to the first patterned circuit.

[0015] Optionally, the first patterned circuit is electrically connected to a second patterned circuit.

[0016] Optionally, the first external pad and the second external pad are made of nickel, tin, silver, gold, nickel alloy or nickel-palladium alloy. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating steps S1 to S2 of the process for fabricating a ceramic substrate according to an embodiment of the present invention.

[0018] Figure 2 This is a flowchart illustrating step S3 of the process for fabricating a ceramic substrate according to an embodiment of the present invention.

[0019] Figure 3 This is a flowchart illustrating step S4 of the process for fabricating a ceramic substrate according to an embodiment of the present invention.

[0020] Figure 4 This is a flowchart illustrating step S5 of the process for fabricating a ceramic substrate according to an embodiment of the present invention.

[0021] Figure 5 This is a flowchart illustrating step S6 of the process for fabricating a ceramic substrate according to an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the structure of the ceramic packaging substrate according to an embodiment of the present invention;

[0023] Label Explanation:

[0024] 1. Ceramic core board, 11. First surface, 12. Second surface, 13. Conductive via, 14. Positioning hole, 15. Metal film, 16. Electroplated copper, 2. Rewiring structure, 21. Dielectric layer, 3. Solder resist layer, 31. Opening, 4. First external pad, 5. Second external pad, 6. First patterned circuit, 7. Second patterned circuit. Detailed Implementation

[0025] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0026] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0027] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0028] The following is for reference. Figures 1-6 The implementation of the ceramic packaging substrate proposed in the embodiments of this utility model will be described in detail.

[0029] The ceramic packaging substrate according to an embodiment of the present invention includes: a ceramic core board 1, a redistribution structure 2, a solder mask layer 3, a first external pad 4, and a second external pad 5.

[0030] Specifically, the ceramic core board 1 has a first surface 11 and a second surface 12 opposite to each other, and a conductive via 13 penetrating the ceramic core board 1; a redistribution structure 2 is disposed on the first surface 11 and electrically connected to the conductive via 13; a solder mask layer 3 covers the redistribution structure 2 and has an opening 31 that exposes the metal wiring layer of the redistribution structure 2; a first external pad 4 is disposed at the opening 31 and electrically connected to the metal wiring layer; and a second external pad 5 is disposed on the second surface 12 and electrically connected to the conductive via 13.

[0031] In other words, the ceramic packaging substrate uses ceramic as the core material, which mainly serves as a support, connection and heat dissipation. The redistribution structure 2 is only set on the first surface 11 of the ceramic core board 1, so that the heat of the first surface 11 containing the chip can be quickly conducted to the second surface 12. The conductive vias 13 on the ceramic core board 1 serve to electrically connect the redistribution structure 2 on the first surface 11 and the second external pads 5 on the second surface 12. The solder mask layer 3 can protect the outer surface of the redistribution structure 2, which helps to improve the protection performance of the ceramic packaging substrate.

[0032] The ceramic core board 1 can be Al2O3 ceramic, AlN ceramic, or Si3N4 ceramic. The conductive vias 13 can be fabricated using 3D printing or laser drilling techniques. Then, a metal thin film 15 is deposited on the surface of the ceramic core board 1 and the vias through chemical copper deposition, sputtering, or plasma-enhanced atomic layer deposition. Finally, the entire board is electroplated using a vertical continuous electroplating method to plate copper onto the surface of the ceramic substrate and into the vias. The redistribution structure 2 can be composed of a metal wiring layer and a dielectric layer 21. The redistribution structure 2 can be fabricated by film lamination, exposure, or vacuum etching. The ceramic core board 1 can be 100mm×100mm to 400mm×400mm in length and width, and 0.2mm to 1.0mm in thickness.

[0033] Therefore, by setting the rewiring structure 2 only on one side of the ceramic core board 1, the heat dissipation of the ceramic packaging substrate is greatly improved.

[0034] Optionally, the ceramic core board 1 is also provided with positioning holes 14, which are located near the edge of the ceramic core board 1. Understandably, the positioning holes 14 facilitate precise processing of the ceramic core board 1 in semiconductor manufacturing processes, thereby ensuring the processing accuracy of the ceramic core board 1. The number of positioning holes 14 can be four.

[0035] Optionally, the conductive via 13 is electrically connected to the first patterned circuit 6. The redistribution structure 2 includes at least one metal wiring layer and at least one dielectric layer 21, with the metal wiring layer electrically connected to the first patterned circuit 6. Understandably, the dielectric layer 21 insulates the metal wiring layer from the ceramic core board 1 and adjacent metal wiring layers except for electrical connections, thereby improving the overall insulation performance of the ceramic substrate. The first patterned circuit 6 acts as a connecting element, linking the conductive via 13 and the metal wiring layer, thus forming an electrical connection between the conductive via 13 and the metal wiring layer, while ensuring the robustness of the connection between the conductive via 13 and the metal wiring layer. The number of metal wiring layers and dielectric layers 21 can be one or multiple layers; the thickness of dielectric layer 21 can be 20μm to 60μm; the line width and line spacing of the first patterned circuit 6 can be 15 / 15μm to 6 / 6μm; the photosensitive material (dry film, photoresist) can be attached to the substrate surface by means of a film-coating wheel or coating; and the first patterned circuit 6 is fabricated on the ceramic core board 1 with the photosensitive material attached by means of exposure, development and etching.

[0036] Furthermore, the first patterned circuit 6 is electrically connected to the second patterned circuit 7. Understandably, this arrangement facilitates the gradual connection of the conductive vias to the outside of the dielectric layer 21, thereby facilitating the electrical connection of the first external pad 4. The linewidth and spacing of the second patterned circuit 7 can be 15 / 15μm to 6 / 6μm. The dielectric layer 21 can be first flattened onto the first surface 11 using vacuum thermopressing, and then the second patterned circuit 7 can be fabricated using conventional packaging substrate manufacturing processes. The metal film 15 of the conductive via 13 can consist of one or more layers of metal, with the outermost layer being a copper layer. The metal film 15 enables the processed vias to conduct electricity, thus forming the conductive via 13. A metal layer can be first created using chemical copper plating, sputtering, or plasma-enhanced atomic layering to improve adhesion, and then other metal layers can be electroplated to further enhance the metal. The layer has corrosion resistance and adaptability to extreme environments; the layer in contact with the ceramic core board 1 can be copper, chromium or titanium, the thickness of the copper layer can be 0.5μm to 1.0μm, and the total thickness of the metal film 15 can be 0.8μm to 2.0μm to ensure the conductivity of the conductive via 13, while also ensuring the wear resistance and corrosion resistance of the conductive via 13. The metal film 15 can be formed by chemical copper deposition, sputtering or plasma-enhanced atomic layering to form the inner metal film 15, and then the outer copper plating 16 is formed by vertical continuous electroplating (VCP) of the whole board.

[0037] Optionally, the first external solder pad 4 and the second external solder pad 5 are made of nickel, tin, silver, gold, nickel alloy, or nickel-palladium-gold alloy. Understandably, this configuration ensures the reliability of the soldering. Specifically, the first external solder pad 4 and the second external solder pad 5 can be made of nickel-palladium-gold alloy, and can be spherical or cubic in shape. The first external solder pad 4 and the second external solder pad 5 can be fabricated after the solder mask layer 3 is completed. The solder mask layer 3 can be 20μm to 40μm thick, allowing it to cover the outer surface of the redistribution structure 2 with a protective layer, while also facilitating the miniaturization of the overall ceramic substrate.

[0038] The following is an example illustrating the fabrication process of the aforementioned ceramic packaging substrate:

[0039] S1 provides a ceramic core plate 1 with dimensions of 100×100mm to 400×400mm and a thickness of 0.2mm to 1.0mm.

[0040] The S2 ceramic core plate 1 is made with through holes using technologies such as 3D printing or laser drilling, with through hole sizes ranging from 0.1mm to 1mm.

[0041] S3 deposits a metal thin film 15 on the ceramic surface and through holes by means of chemical copper deposition, sputtering or plasma-enhanced atomic layering. The metal thin film 15 can be composed of one or more layers of different metals, with the outermost surface being copper, and the layer in contact with the ceramic core plate 1 being copper, chromium or titanium. The thickness of the metal thin film 15 is 0.8μm to 2.0μm, and the thickness of the copper layer is 0.5μm to 1.0μm.

[0042] S4 uses a vertical continuous electroplating (VCP) method to plate copper onto the surface of the ceramic substrate and into the through holes. The thickness of the copper plating is 10μm to 50μm.

[0043] S5 attaches photosensitive material (dry film, photoresist) to the substrate surface by means of a film-coating wheel or coating, and fabricates the first patterned circuit 6 on the ceramic core board 1 with the photosensitive material attached by means of exposure, development and etching. The line width and line spacing of the first patterned circuit 6 are 30 / 30μm to 60 / 60μm.

[0044] S6 firstly, the dielectric layer 21 is flatly attached to the first surface 11 by vacuum hot pressing. The thickness of the dielectric layer 21 is 20μm to 60μm. Then, the second patterned circuit 7 is fabricated by conventional packaging substrate manufacturing process (laser drilling → Desmear → PTH → dry film application → exposure → development → electroplating → film removal → flash etching). The line width and line spacing of the second patterned circuit 7 are 15 / 15μm to 6 / 6μm.

[0045] S7 fabricates the substrate solder resist layer 3 by applying green oil coating → green oil (exposure) → green oil (development) → UV curing + thermal curing → nickel-palladium-gold alloy. The thickness of the solder resist layer 3 is 20μm to 40μm, and the thickness of the nickel-palladium-gold alloy is 8μm to 20μm.

[0046] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0049] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0050] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0051] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A ceramic packaging substrate, characterized in that, include: Ceramic core board, redistribution structure, solder mask layer, first external pad and second external pad; The ceramic core plate has opposing first and second surfaces, and conductive through holes penetrating the ceramic core plate; The rewiring structure is disposed on the first surface, and the rewiring structure is electrically connected to the conductive via. The solder mask layer covers the redistribution structure, and the solder mask layer has an opening that exposes the metal wiring layer of the redistribution structure. The first external pad is disposed at the opening and electrically connected to the metal wiring layer; The second external pad is disposed on the second surface and electrically connected to the conductive via.

2. The ceramic packaging substrate as described in claim 1, characterized in that, The ceramic core plate is also provided with positioning holes, which are located near the edge of the ceramic core plate.

3. The ceramic packaging substrate as described in claim 1, characterized in that, The conductive via is electrically connected to a first patterned circuit, and the redistribution structure includes at least one metal wiring layer and at least one dielectric layer, wherein the metal wiring layer is electrically connected to the first patterned circuit.

4. The ceramic packaging substrate as described in claim 3, characterized in that, The first patterned circuit is electrically connected to the second patterned circuit.

5. The ceramic packaging substrate as described in claim 1, characterized in that, The first external pad and the second external pad are made of nickel, tin, silver, gold, nickel alloy or nickel-palladium-gold alloy.

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