Chip packaging structure

Abstract

The utility model discloses a chip packaging structure, and belongs to the technical field of semiconductors. The chip packaging structure comprises a first rewiring structure and a second rewiring structure, the first chip is positioned on the first rewiring structure and is connected with the first rewiring structure; the packaging layer is located on the first rewiring structure and wraps the first chip; the shielding layer covers the packaging layer and extends to the side surface of the first rewiring structure; and the protective layer covers the shielding layer. According to the invention, the shielding layer can be protected, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure. Background Technology

[0002] After chip packaging is completed, a shielding layer is applied to the surface of the packaging layer of the chip package structure. However, the shielding layer is located on the outermost layer of the chip package structure and is in direct contact with air and moisture, making it prone to oxidation and peeling, which reduces the reliability of the chip package structure. Utility Model Content

[0003] This application aims to at least address one of the technical problems existing in the related art. To this end, this application proposes a chip packaging structure that can protect the shielding layer and improve the reliability of the chip packaging structure.

[0004] This application provides a chip packaging structure, including:

[0005] First rewiring structure;

[0006] The first chip is located on the first redistribution structure and is connected to the first redistribution structure;

[0007] An encapsulation layer is located on the first redistribution structure and covers the first chip;

[0008] A shielding layer covers the encapsulation layer and extends to the side of the first rewiring structure;

[0009] A protective layer that covers the shielding layer.

[0010] According to one embodiment of this application, the surface of the shielding layer near the protective layer has a rough structure, and the protective layer covers the rough structure.

[0011] According to one embodiment of this application, the first redistribution structure includes a plurality of redistribution layers stacked and connected, the plurality of redistribution layers including a ground layer, and the shielding layer extending at least to the side of the ground layer.

[0012] According to one embodiment of this application, the modulus difference between the protective layer and the shielding layer is less than or equal to 200 GPa.

[0013] According to one embodiment of this application, the protective layer includes an antioxidant layer.

[0014] According to one embodiment of this application, the antioxidant layer comprises a resin.

[0015] According to one embodiment of this application, the thickness of the protective layer is greater than or equal to 10 μm.

[0016] According to one embodiment of this application, the shielding layer includes a metal shielding layer.

[0017] According to one embodiment of this application, the thickness of the metal shielding layer is 1-10 μm.

[0018] According to one embodiment of this application, the chip packaging structure further includes:

[0019] The second rewiring structure is located on the first chip and connected to the first rewiring structure;

[0020] The second chip is located on the second redistribution structure and is connected to the second redistribution structure;

[0021] The encapsulation layer is also located on the second redistribution structure and covers the second chip, and the shielding layer also covers the side of the second redistribution structure.

[0022] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0023] By covering the surface of the shielding layer with a protective layer, the shielding layer is protected, avoiding direct contact between the shielding layer and air and moisture, reducing the risk of oxidation and peeling of the shielding layer, and improving the reliability of the chip packaging structure.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0026] Figure 1 This is one of the schematic diagrams of the chip packaging structure provided in the embodiments of this application;

[0027] Figure 2 This is the second schematic diagram of the chip packaging structure provided in the embodiments of this application. Detailed Implementation

[0028] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0029] The chip packaging structure provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0030] Figure 1 This is one of the schematic diagrams of the chip packaging structure provided in the embodiments of this application.

[0031] like Figure 1 As shown, the chip packaging structure provided in this application embodiment includes a first redistribution structure 1, a first chip 2, a packaging layer 3, a shielding layer 4, and a protective layer 5.

[0032] The first rewiring structure 1 may include a circuit structure. The material of the circuit structure of the first rewiring structure 1 may include metals such as copper.

[0033] The first chip 2 is located on and connected to the first rewiring structure 1. The first chip 2 can be connected to the circuit structure in the first rewiring structure 1. There can be one or more first chips 2. When the chip package structure includes multiple first chips 2, the multiple first chips 2 are respectively located on the first rewiring structure 1 and respectively connected to the circuit structure in the first rewiring structure 1. The first chip 2 may include radio frequency chips, or other functional chips, which are not specifically limited here.

[0034] In some embodiments, the chip package structure may further include a first pad 7. The first pad 7 is located on the first redistribution structure 1 and is connected to the circuit structure of the first redistribution structure 1. The first chip 2 may include a first bump 6, which is connected to the first pad 7, so that the first chip 2 is connected to the circuit structure in the first redistribution structure 1 through the first bump 6 and the first pad 7. The material of the first pad 7 may include a metal such as copper.

[0035] The encapsulation layer 3 is located on the first redistribution structure 1 and covers the first chip 2. The material of the encapsulation layer 3 may include resin. The resin may include compound, etc., and the compound may be composed of materials such as resin, filler, hardener and catalyst.

[0036] The shielding layer 4 covers the encapsulation layer 3 and extends to the side of the first rewiring structure 1. For example... Figure 1 As shown, the shielding layer 4 can completely cover the upper surface and sides of the encapsulation layer 3. The shielding layer 4 also covers at least part of the sides of the first redistribution structure 1, that is, the shielding layer 4 can cover part or all of the sides of the first redistribution structure 1. The shielding layer 4 is used to reduce electromagnetic interference between the first chip 2 and external electronic devices, and to improve the thermal conductivity of the multi-layer stacked chip encapsulation structure.

[0037] Protective layer 5 covers shielding layer 4. For example... Figure 1 As shown, the protective layer 5 can completely cover the upper surface and sides of the shielding layer 4.

[0038] In this embodiment, by providing a protective layer 5 on the shielding layer 4 of the chip packaging structure, the protective layer 5 completely covers the upper surface and side surface of the shielding layer 4, so that the shielding layer 4 is located inside the chip packaging structure, so that the shielding layer 4 does not come into direct contact with air and moisture, reducing the risk of oxidation and peeling off of the shielding layer 4, thereby improving the reliability of the chip packaging structure.

[0039] In some embodiments, the surface of the shielding layer 4 near the protective layer 5 has a rough structure, and the protective layer 5 covers the rough structure.

[0040] The surface of the shielding layer 4 near the protective layer 5 includes the upper surface and side surfaces of the shielding layer 4. At least a portion of the upper surface and / or at least a portion of the side surfaces of the shielding layer 4 have a roughened structure. For example, after forming the shielding layer 4, the upper surface and side surfaces of the shielding layer 4 are roughened to form a roughened structure. The roughened structure may include uneven structures, etc. The protective layer 5 covers the roughened structure of the shielding layer 4, which can enhance the bonding force between the shielding layer 4 and the protective layer 5, further improving the reliability of the chip packaging structure.

[0041] In some embodiments, the first rewiring structure 1 may include one or more rewiring layers 10, each rewiring layer 10 may include an insulating dielectric layer 11 and a wiring layer 12, the wiring layer 12 in each rewiring layer 10 being located on and penetrating the insulating dielectric layer 11. When the first rewiring structure 1 includes multiple rewiring layers 10, the multiple rewiring layers 10 are stacked, and the wiring layers 12 in adjacent rewiring layers 10 are connected, such that the wiring layers 12 in the multiple rewiring layers 10 are sequentially connected to form the wiring structure of the first rewiring structure 1. The shielding layer 4 covers the encapsulation layer 3 and extends to the side of the insulating dielectric layer 11 in the multiple rewiring layers 10.

[0042] For example, the multiple rerouting layers 10 of the first rerouting structure 1 include a first rerouting layer to an Nth rerouting layer stacked sequentially, where N ≥ 2. The circuit layer of the i-th rerouting layer is located on and penetrates the insulating dielectric layer of the i-th rerouting layer, and the circuit layer of the i-th rerouting layer is connected to the circuit layer of the (i-1)-th rerouting layer, where 1 < i ≤ N. The circuit layers 12 of the first rerouting layer to the Nth rerouting layer are connected sequentially to form the circuit structure of the first rerouting structure 1. The first chip 2 is located on the Nth rerouting layer (i.e., the top rerouting layer 10 of the first rerouting structure 1) and is connected to the circuit layer 12 of the Nth rerouting layer, so that the first chip 2 is connected to the circuit structure of the first rerouting structure 1.

[0043] In some embodiments, the first redistribution structure 1 may further include a cover layer 13 covering the Nth redistribution layer of the first redistribution structure 1. The cover layer 13 has openings corresponding to the positions of the line layers 12 in the Nth redistribution layer. A first pad 7 is located in the openings and is connected to the line layers 12 in the Nth redistribution layer. A first bump 6 of the first chip 2 is connected to the first pad 7, and the first chip 2 is connected to the line layers 12 in the Nth redistribution layer of the first redistribution structure 1 through the first bump 6 and the first pad 7. An encapsulation layer 3 covers the first chip 2 and the cover layer 13 of the first redistribution structure 1.

[0044] In some embodiments, the plurality of redistribution layers 10 of the first redistribution structure 1 include a ground layer 10a, and the shielding layer 4 extends at least to the side of the ground layer 10a.

[0045] For example, the j-th rewiring layer in the plurality of rewiring layers 10 is the ground layer 10a, where 1≤j≤N. The shielding layer 4 covers the upper surface and sides of the encapsulation layer 3, and covers the sides of the insulating dielectric layer 11 in the first rewiring structure 1 from the N-th to the j-th rewiring layer.

[0046] In this embodiment, the shielding layer 4 covers the encapsulation layer 3 and extends at least to the side of the ground layer 10a, which can further improve the shielding effect of the shielding layer 4, further reduce the electromagnetic interference between the first chip 2 and external electronic devices, and further improve the thermal conductivity of the chip encapsulation structure.

[0047] It should be noted that the shielding layer 4 can also extend to the side of the redistribution layer 10 below the ground layer 10a. For example, the shielding layer 4 can cover the Nth redistribution layer of the first redistribution structure 1 to the side of the insulating dielectric layer 11 in the first redistribution layer, that is, the shielding layer 4 completely covers the upper surface and side of the encapsulation layer 3 as well as the side of the first redistribution structure 1.

[0048] In this embodiment, the shielding layer 4 extends to the side of the insulating dielectric layer 11 in the redistribution layer 10 below the ground layer 10a, further improving the shielding effect of the shielding layer 4, further reducing electromagnetic interference and improving the thermal conductivity of the chip packaging structure.

[0049] In some embodiments, the modulus difference between the protective layer 5 and the shielding layer 4 is less than or equal to 200 GPa.

[0050] In this embodiment, the difference between the modulus of the protective layer 5 and the modulus of the shielding layer 4 is no greater than 200 GPa, which improves the bonding force between the protective layer 5 and the shielding layer 4, prevents the protective layer 5 from falling off, and further improves the reliability of the chip packaging structure.

[0051] In some embodiments, the protective layer 5 includes an antioxidant layer.

[0052] In this embodiment, an antioxidant layer is used as the protective layer 5. The protective layer 5 has antioxidant properties to prevent the protective layer 5 from oxidizing and peeling off, thus exposing the shielding layer 4 covered by the protective layer 5. This further improves the protective effect of the protective layer 5 on the shielding layer 4, prevents the shielding layer 4 from direct contact with air and moisture, further reduces the risk of oxidation and peeling off of the shielding layer 4, and thus improves the reliability of the chip packaging structure.

[0053] In some embodiments, the antioxidant layer comprises a resin. The resin may include a compound, which is composed of materials such as resin, filler, hardener, and catalyst.

[0054] In related technologies, shielding layers are often made of metal materials. However, metal materials have poor toughness, and scratches are easily generated on the shielding layer during the chip packaging process, affecting the identification of subsequent processes. In this embodiment, the anti-oxidation layer can be made of resin materials. Resin materials are more tough than metal materials. The anti-oxidation layer protects the shielding layer 4, preventing scratches from forming on it and solving the problem of subsequent process identification caused by scratches.

[0055] It should be noted that the antioxidant layer may also include other materials, provided that the difference between the modulus of the antioxidant layer and the modulus of the shielding layer 4 is not greater than 200 GPa. For example, the antioxidant layer may also include PI (polyimide) or ABF (a type of laminated film material mainly composed of organic epoxy resin, curing agent and inorganic particulate filler), etc.

[0056] In some embodiments, the thickness of the protective layer 5 is greater than or equal to 10 μm. When the protective layer 5 is too thin, the water absorption rate of the protective layer 5 is high, the effect of isolating air and moisture is poor, and the structure of the protective layer 5 is relatively fragile, resulting in poor protection of the shielding layer 4. Furthermore, the bonding force between the thin protective layer 5 and the shielding layer 4 is weak, making the protective layer 5 prone to delamination and peeling.

[0057] Therefore, the thickness of the protective layer 5 in this embodiment is not less than 10μm, which reduces the water absorption rate of the protective layer 5, improves the effect of the protective layer 5 in isolating air and moisture, thereby reducing the risk of oxidation and peeling off of the shielding layer 4, and improving the structural strength of the protective layer 5 to avoid scratches on the shielding layer 4. At the same time, it improves the bonding force between the protective layer 5 and the shielding layer 4, and avoids problems such as delamination and peeling off of the protective layer 5, thereby improving the reliability of the chip packaging structure.

[0058] In some embodiments, the shielding layer 4 includes a metal shielding layer, that is, the material of the shielding layer 4 is metal, such as stainless steel, copper, titanium, nickel, tin and other metals.

[0059] In related technologies, to reduce the risk of shielding layer oxidation and peeling, the chip packaging structure has extremely high requirements for the shielding layer material, and the range of materials that can be selected for the shielding layer is limited. For example, the shielding layer material is stainless steel.

[0060] In this embodiment, the protective layer 5 covers the upper surface and sides of the shielding layer 4, isolating air and moisture, reducing the risk of oxidation and peeling off of the shielding layer 4, reducing the material selection requirements of the chip packaging structure for the shielding layer 4, and expanding the range of materials that can be selected for the shielding layer 4. The shielding layer 4 can be made not only of stainless steel, but also of metals such as copper, titanium, nickel, and tin.

[0061] In some embodiments, the thickness of the metal shielding layer is 1-10 μm.

[0062] When the metal shielding layer is too thin, its shielding effect against electromagnetic interference between the first chip 2 and external electronic devices is poor. When the metal shielding layer is too thick, it increases the material cost of the chip packaging structure. Therefore, in this embodiment, the thickness of the metal shielding layer is 1-10 μm, which can achieve the shielding effect against electromagnetic interference between the first chip 2 and external electronic devices while saving the material cost of the metal shielding layer in the chip packaging structure.

[0063] In some embodiments, the depth of the metal shielding layer is 50-800 μm. It should be noted that the depth of the metal shielding layer can be determined according to the actual dimensions of the chip package structure, and is not limited here.

[0064] In some embodiments, such as Figure 2 As shown, the chip packaging structure also includes a second redistribution structure 9 and a second chip 8. The second redistribution structure 9 may include a circuit structure. The material of the circuit structure of the second redistribution structure 9 may include metals such as copper.

[0065] The second rewiring structure 9 is located on the first chip 2 and is connected to the first rewiring structure 1. The second rewiring structure 9 is located on the side of the first chip 2 opposite to the first rewiring structure 1, and the circuit structure of the second rewiring structure 9 is connected to the circuit structure in the first rewiring structure 1.

[0066] The second chip 8 is located on and connected to the second redistribution structure 9. There may be one or more second chips 8. In cases where the chip package structure includes multiple second chips 8, each second chip 8 is located on the second redistribution structure 9 and connected to the circuit structure within the second redistribution structure 9. The second chip 8 may include radio frequency chips, or other functional chips; no specific limitation is made here.

[0067] In some embodiments, the chip package structure further includes a second pad 14, which is located on the second redistribution structure 9 and connected to the circuit structure of the second redistribution structure 9. The second chip 8 may include a second bump 15, which is connected to the second pad 14, allowing the second chip 8 to be connected to the circuit structure in the second redistribution structure 9 via the second bump 15 and the second pad 14. The material of the second pad 14 may include a metal such as copper.

[0068] The encapsulation layer 3 is also located on the second redistribution structure 9 and covers the second chip 8, while the shielding layer 4 covers the sides of the second redistribution structure 9. Figure 2 As shown, the shielding layer 4 can completely cover the upper surface and sides of the encapsulation layer 3. The shielding layer 4 also covers all sides of the second redistribution structure 9 and part or all sides of the first redistribution structure 1.

[0069] The shielding layer 4 is used to reduce electromagnetic interference between the first chip 2 and the second chip 8 and external electronic devices, and to improve the thermal conductivity of the multi-layer stacked chip packaging structure.

[0070] In some embodiments, the second rewiring structure 9 may include one or more rewiring layers 10. Each rewiring layer 10 may include an insulating dielectric layer 11 and a wiring layer 12. The wiring layer 12 in each rewiring layer 10 is located on and penetrates the insulating dielectric layer 11. When the second rewiring structure 9 includes multiple rewiring layers 10, the multiple rewiring layers 10 are stacked, and the wiring layers 12 in adjacent rewiring layers 10 are connected, such that the wiring layers 12 in the multiple rewiring layers 10 are connected sequentially to form the wiring structure of the second rewiring structure 9.

[0071] In some embodiments, the chip packaging structure may further include conductive pillars 20, and there may be multiple conductive pillars 20. The multiple conductive pillars 20 may be spaced apart within the packaging layer 3 between the first redistribution structure 1 and the second redistribution structure 9, and the conductive pillars 20 may penetrate the packaging layer 3 between the first redistribution structure 1 and the second redistribution structure 2, such that the bottom of the conductive pillar 20 is connected to the circuit layer 12 of the top redistribution layer 10 of the first redistribution structure 1, and the top of the conductive pillar 20 is connected to the circuit layer 12 of the bottom redistribution layer 10 of the second redistribution structure 9, so that the circuit structure of the second redistribution structure 9 and the circuit structure of the first redistribution structure 1 are connected through the conductive pillars 20. The conductive pillars 20 may be copper pillars, etc.

[0072] In some embodiments, the chip package structure may also include other redistribution structures and chips, without being overly limited herein. For example, the chip package structure may also include a third redistribution structure and a third chip, wherein the third redistribution structure is located on the second chip 8 and connected to the second redistribution structure 9, the third chip is located on the third redistribution structure and connected to the third redistribution structure, the package layer 3 is also located on the third redistribution structure and covers the third chip, and the shielding layer 4 also covers the sides of the third redistribution structure.

[0073] In summary, according to the chip packaging structure provided in this application, by setting a protective layer 5 on the shielding layer 4, the protective layer 5 completely covers the upper surface and side surface of the shielding layer 4, so that the shielding layer 4 is located inside the chip packaging structure, so that the shielding layer 4 does not come into direct contact with air and moisture, reducing the risk of oxidation and peeling of the shielding layer 4, improving the bonding force between the shielding layer 4 and the packaging layer 3, the second redistribution structure 9 and the first redistribution structure 1, thereby improving the reliability of the chip packaging structure, and expanding the range of materials that can be selected for the shielding layer 4.

[0074] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0075] In the description of this application, "multiple" means two or more.

[0076] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0077] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that, include: First rewiring structure; The first chip is located on the first redistribution structure and is connected to the first redistribution structure; An encapsulation layer is located on the first redistribution structure and covers the first chip; A shielding layer covers the encapsulation layer and extends to the side of the first rewiring structure; A protective layer that covers the shielding layer.

2. The chip packaging structure according to claim 1, characterized in that, The surface of the shielding layer near the protective layer has a rough structure, and the protective layer covers the rough structure.

3. The chip packaging structure according to claim 1, characterized in that, The first redistribution structure includes a plurality of redistribution layers stacked and connected, the plurality of redistribution layers including a ground layer, and the shielding layer extending at least to the side of the ground layer.

4. The chip packaging structure according to claim 1, characterized in that, The difference in modulus between the protective layer and the shielding layer is less than or equal to 200 GPa.

5. The chip packaging structure according to claim 1, characterized in that, The protective layer includes an antioxidant layer.

6. The chip packaging structure according to claim 5, characterized in that, The antioxidant layer comprises resin.

7. The chip packaging structure according to claim 1, characterized in that, The thickness of the protective layer is greater than or equal to 10 μm.

8. The chip packaging structure according to claim 1, characterized in that, The shielding layer includes a metal shielding layer.

9. The chip packaging structure according to claim 8, characterized in that, The thickness of the metal shielding layer is 1-10 μm.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The chip packaging structure also includes: The second rewiring structure is located on the first chip and connected to the first rewiring structure; The second chip is located on the second redistribution structure and is connected to the second redistribution structure; The encapsulation layer is also located on the second redistribution structure and covers the second chip, and the shielding layer also covers the side of the second redistribution structure.

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