Chip packaging structure and electronic device
By introducing a buffer layer between the bonding adhesive layer and the redistribution layer, the problems of substrate warping and cracking caused by inconsistent thermal expansion coefficients of materials were solved, thereby improving the reliability of the chip packaging structure and the product yield.
Patent Information
- Application Number
- CN202423097407.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2034-12-16
AI Technical Summary
In the rewiring-first process, the inconsistent thermal expansion coefficients of different materials can cause substrate warping and increase the risk of chip packaging structure cracking.
A buffer layer is introduced between the bonding adhesive layer and the redistribution layer. The buffer layer material has a low Young's modulus to absorb the internal stress caused by the mismatch of thermal expansion coefficients, thereby reducing the risk of substrate warping and cracking.
It effectively reduces the risk of warpage and cracking in chip packaging structures, and improves the reliability of chip packaging structures and product yield.
Smart Images
Figure CN223829846U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a chip packaging structure and electronic device. Background Technology
[0002] When using the redistribution-first (RDL First) process, a redistribution layer is first built on a glass substrate, followed by subsequent operations such as chip mounting and encapsulation adhesive to achieve chip packaging. However, after packaging, the entire chip package structure suffers from chip cracking defects. Utility Model Content
[0003] To overcome the technical problems mentioned in the background, this application provides a chip packaging structure, which includes:
[0004] substrate;
[0005] A bonding adhesive layer is located on one side of the substrate;
[0006] A buffer layer is located on the side of the bonding adhesive layer away from the substrate;
[0007] A redistribution layer is located on the side of the buffer layer away from the substrate;
[0008] A chip unit is located on the side of the redistribution layer away from the substrate, and the chip unit includes at least one chip;
[0009] An encapsulation layer that at least surrounds the chip.
[0010] In one possible implementation, the chip package structure further includes conductive pillars located on the side of the redistribution layer away from the substrate and around the chip, the conductive pillars being connected to traces in the redistribution layer.
[0011] In one possible implementation, the chip includes a pin side for setting pins and a back side opposite to the pin side, the back side of the chip being disposed toward the redistribution layer;
[0012] The conductive post includes a bump, the bump of the conductive post is disposed facing the redistribution layer, and the conductive post is connected to the trace of the redistribution layer through the bump.
[0013] In one possible implementation, the orthographic projection of the bonding adhesive layer on the substrate coincides with the orthographic projection of the buffer layer on the substrate.
[0014] In one possible implementation, the bonding adhesive layer has a first thickness and the buffer layer has a second thickness in a direction perpendicular to the plane of the substrate, wherein the first thickness is less than the second thickness;
[0015] The first thickness is 0.1 micrometer to 2 micrometers, and the second thickness is 5 micrometers to 300 micrometers.
[0016] In one possible implementation, the material of the conductive pillar includes metallic copper.
[0017] In one possible implementation, the sidewalls of the corresponding encapsulation layer, the redistribution layer, the buffer layer, the bonding adhesive layer, and the substrate form a flat plane.
[0018] In one possible implementation, the material of the buffer layer includes one or more of oxides, nitrides, organics, polymers, and carbides.
[0019] In one possible implementation, the Young's modulus of the buffer layer is 120 kPa to 2 GPa at room temperature.
[0020] In an environment with a temperature of 100°C to 180°C, the Young's modulus of the buffer layer is 110 kPa to 2 GPa.
[0021] Another object of this application is to provide an electronic device comprising a plurality of the chip package structures provided in this application.
[0022] Based on any of the above aspects, embodiments of this application provide a chip packaging structure and electronic device. Thus, by introducing a buffer layer between the bonding adhesive layer and the redistribution layer, the buffer layer provides a buffering effect for the chip packaging structure, reducing the warping of the substrate due to inconsistent thermal expansion coefficients of the materials, and effectively lowering the risk of chip packaging structure cracking. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is one of the schematic diagrams of a chip packaging structure provided in this embodiment;
[0025] Figure 2a and Figure 2bThis is a process diagram of a chip packaging structure provided in this embodiment;
[0026] Figure 3 This is a second schematic diagram of a chip packaging structure provided in this embodiment;
[0027] Figure 4 for Figure 1 A magnified view of the middle dashed coil.
[0028] Icons: Substrate-10, Bonding Adhesive Layer-20, Buffer Layer-30, Redistribution Layer-40, Chip Unit-50, Chip-500, Pin Side-5001, Back Side-5002, Encapsulation Layer-60, Conductive Pillar-70, Bump-700. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0031] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0032] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0033] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.
[0034] The inventors discovered that in the Redistribution Layer First (RDL First) process, a redistribution layer is first constructed on a glass substrate, followed by subsequent operations such as chip mounting and encapsulation adhesive to achieve chip encapsulation. However, due to the inconsistent coefficients of thermal expansion between different materials, the varying degrees of expansion and contraction during temperature fluctuations can lead to substrate warping. Furthermore, the large modulus of the entire chip package structure after encapsulation increases the risk of chip cracking when the substrate warps. Therefore, the inventors innovatively designed the following technical solution, the specific implementation of which will be described in detail below with reference to the accompanying drawings.
[0035] Please see Figure 1 , Figure 1 This is one of the schematic diagrams of a chip packaging structure 1 provided in this embodiment. The chip packaging structure 1 includes: a substrate 10, a bonding adhesive layer 20, a buffer layer 30, a redistribution layer 40, a chip unit 50, and a packaging layer 60. The bonding adhesive layer 20 is located on one side of the substrate 10, the buffer layer 30 is located on the side of the bonding adhesive layer 20 away from the substrate 10, and the redistribution layer 40 is located on the side of the buffer layer 30 away from the substrate 10.
[0036] In this embodiment, the substrate 10 serves as the foundation of the chip packaging structure 1 and is typically made of glass, ceramic, or plastic materials, providing physical support for the chip unit 50. The bonding adhesive layer 20 can be a debonding adhesive. As a temporary bonding material, the debonding adhesive provides temporary support and protection for the substrate 10 during the chip packaging process. Furthermore, in the final stage of the chip packaging process, the debonding adhesive can be easily separated from the substrate 10, facilitating the transfer of the chip 500 to other support systems or subsequent processes. The buffer layer 30 is located on the side of the bonding adhesive layer 20 away from the substrate 10, and its main purpose is to provide cushioning. The redistribution layer 40 is constructed on the side of the buffer layer 30 away from the substrate 10, and it is responsible for redistributing the electrical connections of the chip unit 50 to accommodate the external structure of the package.
[0037] Because different materials have different coefficients of thermal expansion (CTE), the expansion and contraction of the materials vary with temperature fluctuations, which can easily cause warping of the substrate 10. Furthermore, after chip packaging, the overall chip packaging structure 1 has a large modulus and high rigidity, increasing the risk of chip cracking when the substrate 10 warps. Therefore, in this embodiment, a buffer layer 30 is added between the bonding adhesive layer 20 and the redistribution layer 40. This absorbs the internal stress caused by the mismatch in coefficients of thermal expansion, reducing the risk of substrate 10 warping and chip 500 damage, and also lowering the overall modulus of the chip packaging structure 1.
[0038] Chip unit 50 is located on the side of redistribution layer 40 away from substrate 10, and chip unit 50 includes at least one chip 500. Encapsulation layer 60 covers at least all four sides of chip 500.
[0039] In this embodiment, the chip unit 50 is the core of the chip packaging structure 1, and the packaging layer 60 covers at least all four sides of the chip 500. Its main function is to protect the internal components from physical damage and environmental influences, such as moisture, dust and temperature changes.
[0040] It is worth noting that the type of chip 500 in chip unit 50 is not specifically defined here and should be selected according to the actual situation. The material of the encapsulation layer 60 can be plastic, epoxy resin, or silicone rubber, etc., and the material of the encapsulation layer 60 is not specifically limited here.
[0041] Please see Figure 2a and Figure 2b , Figure 2a and Figure 2b This is a process diagram of a chip packaging structure 1 provided in this embodiment.
[0042] First, a bonding adhesive layer 20 is fabricated on the substrate 10.
[0043] Next, a buffer layer 30 is fabricated on the bonding adhesive layer 20.
[0044] Then, a redistribution layer 40 is constructed on the buffer layer 30, and then the chip 500 is mounted on the redistribution layer 40.
[0045] Finally, a packaging layer 60 is fabricated around the chip 500 for encapsulation.
[0046] Further, please see Figure 3 , Figure 3 This is a second schematic diagram of a chip packaging structure provided in this embodiment. The chip packaging structure also includes conductive pillars 70, which are located on the side of the redistribution layer 40 away from the substrate 10 and around the chip 500. The conductive pillars 70 are connected to the traces in the redistribution layer 40.
[0047] In this embodiment, the conductive pillar 70 is connected to the redistribution layer 40 via traces to transmit electrical signals. At this time, the encapsulation layer 60 at least surrounds the chip 500 and the conductive pillar 70, its main function being to protect internal components from physical damage and environmental influences such as moisture, dust, and temperature changes.
[0048] Furthermore, please see again Figure 3 The chip 500 includes a pin side 5001 for setting pins and a back side 5002 opposite to the pin side 5001, with the back side 5002 of the chip 500 facing the redistribution layer 40.
[0049] In this embodiment, chip 500 is connected to redistribution layer 40. The pin side 5001 of chip 500 is the interface for connecting chip 500 to external circuits, while the back side 5002 of chip 500 is disposed facing redistribution layer 40, allowing chip 500 to have greater flexibility in different packaging requirements and electrical connections.
[0050] It is worth noting that chip 500 can be mounted onto redistribution layer 40 via thermosetting bonding. The specific mounting method for chip 500 is not limited here and should be selected according to the actual situation.
[0051] The conductive post 70 includes a bump 700, which is positioned toward the redistribution layer 40. The conductive post 70 is connected to the traces of the redistribution layer 40 through the bump 700.
[0052] In this embodiment, the conductive pillar 70 is connected to the traces in the redistribution layer 40 via the bump 700 to achieve electrical connection. Simultaneously, the conductive pillar 70 surrounds the chip 500, and together with the pin side 5001 of the chip 500, they form a bridge connecting the chip 500 to external circuits, ensuring the electrical reliability of the chip 500's package structure.
[0053] Further, please see Figure 1 The orthographic projection of the bonding adhesive layer 20 on the substrate 10 coincides with the orthographic projection of the buffer layer 30 on the substrate 10.
[0054] In this embodiment, the buffer layer 30 is disposed on the side of the bonding adhesive layer 20 away from the substrate 10. At the same time, the orthographic projection range of the buffer layer 30 on the substrate 10 coincides with the orthographic projection range of the bonding adhesive layer 20 on the substrate 10, which helps to distribute the internal stress caused by the mismatch of thermal expansion coefficients more evenly and reduce the risk of warping and cracking of the substrate 10.
[0055] Further, please see Figure 1 and Figure 4 , Figure 4 for Figure 1 In the enlarged view of the dashed circle, in the direction perpendicular to the plane of the substrate 10, the bonding adhesive layer 20 has a first thickness h1 and the buffer layer 30 has a second thickness h2, wherein the first thickness h1 is less than the second thickness h2.
[0056] In this embodiment, the bonding adhesive layer 20 is the medium used to fix the chip 500 to the substrate 10. The buffer layer 30 is located above the bonding adhesive layer 20. Its thicker design provides additional mechanical support and stress buffering, which can reduce thermal stress caused by the mismatch of thermal expansion coefficients, reduce warping and cracking of the substrate 10, and protect the chip 500 from mechanical impact and temperature changes. The thinner bonding adhesive layer 20 reduces thermal resistance and improves the thermal conductivity between the chip 500 and the substrate 10.
[0057] Specifically, the first thickness h1 is 0.1 micrometers to 2 micrometers, and the second thickness h2 is 5 micrometers to 300 micrometers.
[0058] In this embodiment, the first thickness h1 is 0.1 micrometer to 2 micrometers. For example, the first thickness h1 is 0.1 micrometer, 0.3 micrometer, 0.5 micrometer, 0.7 micrometer, 0.9 micrometer, 1.1 micrometer, 1.3 micrometer, 1.5 micrometer, 1.7 micrometer, 1.9 micrometer and 2 micrometer, etc.
[0059] The thickness of the buffer layer 30 is a second thickness h2. If the second thickness h2 of the buffer layer 30 is too small, the buffering effect may be poor; if the second thickness h2 of the buffer layer 30 is too large, it may cause a decrease in the lifespan of the substrate 10. Therefore, the second thickness h2 of the buffer layer 30 should be designed within a certain range to achieve the best buffering effect. The second thickness h2 is from 5 micrometers to 300 micrometers. For example, the second thickness h2 is 5 micrometers, 25 micrometers, 45 micrometers, 65 micrometers, 85 micrometers, 105 micrometers, 125 micrometers, 145 micrometers, 165 micrometers, 185 micrometers, 205 micrometers, 225 micrometers, 245 micrometers, 265 micrometers, 285 micrometers, and 300 micrometers, etc.
[0060] Furthermore, the material of the conductive post 70 includes metallic copper.
[0061] In this embodiment, the conductive post 70 can be a copper post, which has good resistivity, good thermal conductivity and high resistance to electromigration.
[0062] Further, please see Figure 1 The sidewalls of the corresponding encapsulation layer 60, redistribution layer 40, buffer layer 30, bonding adhesive layer 20, and substrate 10 form a flat plane.
[0063] In this embodiment, the sidewalls of the chip packaging structure 1, namely the sidewalls of the packaging layer 60, the redistribution layer 40, the buffer layer 30, the bonding adhesive layer 20, and the substrate 10, are ensured to form a flat plane, thereby improving the reliability and overall appearance of the chip packaging structure 1.
[0064] Furthermore, the material of the buffer layer 30 includes one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), organic materials, polymers, and carbides.
[0065] In this embodiment, the material of the buffer layer 30 can be an organic polymer, which has good flexibility and adjustability. For example, the material of the buffer layer 30 can be a bonding adhesive in an organic polymer, which typically has low hardness and low elastic modulus, making it suitable for cushioning and shock absorption applications.
[0066] Furthermore, at room temperature, the Young's modulus of the buffer layer 30 is 120 kPa to 2 GPa, and at a temperature of 100°C to 180°C, the Young's modulus of the buffer layer 30 is 110 kPa to 2 GPa.
[0067] In this embodiment, Young's modulus is a physical quantity that measures the stiffness of a material. The Young's modulus of a material typically decreases with increasing temperature. The buffer layer 30 is mainly used to absorb and disperse thermal and mechanical stresses between different material layers. Maintaining the Young's modulus of the buffer layer 30 within a certain range, whether at room temperature or in an environment with increased temperature, can reduce warping and cracking of the substrate 10. At room temperature, the Young's modulus of the buffer layer 30 is 120 kPa to 2 GPa. Exemplarily, the Young's modulus of the buffer layer 30 can be 120 kPa, 1200 kPa, 120000 kPa, 1200000 kPa, or 2000000 kPa, etc.
[0068] In an environment with a temperature of 100°C to 180°C, the Young's modulus of the buffer layer 30 is 110 kPa to 2 GPa. For example, the Young's modulus of the buffer layer 30 is 110 kPa, 1100 kPa, 1100 kPa, 110000 kPa, 1100000 kPa, and 2000000 kPa, etc.
[0069] Based on the same inventive concept, another objective of this application is to provide an electronic device comprising any of the aforementioned chip packaging structures 1. By introducing a buffer layer 30, the chip packaging structure 1 can reduce warping and cracking of the substrate 10, ensuring the reliability of the chip packaging structure 1 and improving the product yield of the electronic device.
[0070] In summary, this application provides a chip packaging structure and electronic device. The chip packaging structure includes: a substrate, a bonding adhesive layer, a buffer layer, a redistribution layer, a chip unit, and a packaging layer. The bonding adhesive layer is located on one side of the substrate, the buffer layer is located on the side of the bonding adhesive layer away from the substrate, and the redistribution layer is located on the side of the buffer layer away from the substrate. The chip unit is located on the side of the redistribution layer away from the substrate, and the chip unit includes at least one chip. The packaging layer at least covers all four sides of the chip. Thus, by introducing a buffer layer between the bonding adhesive layer and the redistribution layer, the above structure provides a buffering effect for the chip packaging structure, reducing the warping of the substrate due to inconsistent thermal expansion coefficients of materials, and effectively reducing the risk of chip packaging structure cracking.
[0071] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A chip packaging structure, characterized in that, The chip packaging structure includes: substrate; A bonding adhesive layer is located on one side of the substrate; A buffer layer is located on the side of the bonding adhesive layer away from the substrate; A redistribution layer is located on the side of the buffer layer away from the substrate; A chip unit is located on the side of the redistribution layer away from the substrate, and the chip unit includes at least one chip; An encapsulation layer that at least surrounds the chip.
2. The chip packaging structure as described in claim 1, characterized in that, The chip packaging structure also includes conductive pillars, which are located on the side of the redistribution layer away from the substrate and around the chip. The conductive pillars are connected to the traces in the redistribution layer.
3. The chip packaging structure as described in claim 2, characterized in that, The chip includes a pin side for setting pins and a back side opposite to the pin side, the back side of the chip being disposed towards the redistribution layer; The conductive post includes a bump, the bump of the conductive post is disposed facing the redistribution layer, and the conductive post is connected to the trace of the redistribution layer through the bump.
4. The chip packaging structure as described in claim 1, characterized in that, The orthographic projection of the bonding adhesive layer on the substrate coincides with the orthographic projection of the buffer layer on the substrate.
5. The chip packaging structure as described in claim 1, characterized in that, In a direction perpendicular to the plane of the substrate, the bonding adhesive layer has a first thickness and the buffer layer has a second thickness, wherein the first thickness is less than the second thickness; The first thickness is 0.1 micrometer to 2 micrometers, and the second thickness is 5 micrometers to 300 micrometers.
6. The chip packaging structure as described in claim 2, characterized in that, The conductive pillar is made of metallic copper.
7. The chip packaging structure as described in claim 1, characterized in that, The sidewalls of the corresponding encapsulation layer, the redistribution layer, the buffer layer, the bonding adhesive layer, and the substrate form a flat plane.
8. The chip packaging structure as described in any one of claims 1-7, characterized in that, The material of the buffer layer includes one of oxides, nitrides, organics, polymers, and carbides.
9. The chip packaging structure as described in claim 8, characterized in that, At room temperature, the Young's modulus of the buffer layer is 120 kPa to 2 GPa. In an environment with a temperature of 100°C to 180°C, the Young's modulus of the buffer layer is 110 kPa to 2 GPa.
10. An electronic device, characterized in that, The electronic device includes the chip packaging structure described in any one of claims 1-9.