Package structure

Abstract

A package structure is provided. The package structure includes an interposer including at least a first die sandwiched between a first redistribution layer (RDL) structure and a second RDL structure. The first die includes: an element layer disposed on the substrate; an inductor element disposed on the element layer; an internal RDL structure disposed on the inductor element; a plurality of conductive connectors disposed on the internal RDL structure; and an inductor contact disposed beside the inductor element and electrically connecting the internal RDL structure and the inductor element. The internal RDL structure is configured to redistribute electrical signals from the inductor contacts to the plurality of conductive connections to prevent electromigration (EM) faults.

Description

Technical Field

[0001] An embodiment of this utility model relates to a packaging structure. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various circuit components (such as transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. Consequently, many types of packages have been developed to meet the customized requirements of integrated circuits. Power networks are also built within the packages to provide power to the component dies. Utility Model Content

[0003] This utility model embodiment provides a packaging structure including: an interposer layer, including a first die sandwiched between a first redistributed layer (RDL) structure and a second RDL structure, wherein the first die includes: a component layer disposed on a substrate; an inductor component disposed on the component layer; an inner RDL structure disposed on the inductor component; a plurality of conductive connectors disposed on the inner RDL structure; and an inductor contact disposed next to the inductor component and electrically connected to the inner RDL structure and the inductor component.

[0004] In some embodiments, conductive features of the internal RDL structure traverse the inductor element. In some embodiments, the conductive features of the internal RDL structure laterally surround the inductor element in a ring arrangement, such that the conductive features are not positioned directly above the inductor element. In some embodiments, a plurality of conductive connectors laterally surround the inductor element in a ring arrangement in a planar view of the internal RDL structure. In some embodiments, a plurality of conductive connectors are arranged in an array on the inductor element in a planar view of the internal RDL structure. In some embodiments, the first die further includes: a plurality of substrate through-holes (TSVs) penetrating the substrate to electrically connect the element layer and the second RDL structure; and a planarization layer encapsulating the substrate, the element layer, the inductor element, and the inductor contacts to contact the bottom surface of the internal RDL structure. In some embodiments, the internal RDL structure is configured to redistribute electrical signals from the inductor contacts to the plurality of conductive connectors. In some embodiments, the interposer further includes: a second die, configured parallel to the first die; a plurality of through-insulating vias (TIVs) laterally surrounding the first die and the second die; and a first encapsulation laterally encapsulating the first die, the second die, and the plurality of TIVs. In some embodiments, the interposer further includes: a second die, vertically stacked on the first die to form a die stack structure; a plurality of through-insulating vias (TIVs) laterally surrounding the die stack structure; and a first encapsulation laterally encapsulating the die stack structure and the plurality of TIVs. In some embodiments, it further includes: one or more package components disposed on the first RDL structure; a second encapsulation laterally encapsulating one or more package components; a plurality of conductive terminals disposed on the second RDL structure; and a package substrate bonded to the interposer via the plurality of conductive terminals.

[0005] This utility model embodiment provides a packaging structure including: an interposer layer, including a first packaging component sandwiched between a first RDL structure and a second RDL structure, wherein the first packaging component includes: a bottom die; an inductor element, an active component die, and a passive component die arranged side by side on the bottom die; an inner RDL structure disposed on the inductor element, the active component die, and the passive component die; and a plurality of conductive connectors disposed on the inner RDL structure to electrically connect the inner RDL structure and the first RDL structure.

[0006] In some embodiments, the first package assembly further includes: an inductor contact disposed adjacent to the inductor element and vertically sandwiched between the bottom die and the inner RDL structure, wherein the inner RDL structure is configured to redistribute electrical signals from the inductor contact to a plurality of conductive connections. In some embodiments, the bottom die includes: a substrate; an element layer disposed on the substrate; and a plurality of TSVs extending through the substrate to electrically connect the element layer and the second RDL structure. In some embodiments, the interposer further includes: a plurality of TIVs laterally surrounding the first package assembly; and a first encapsulation laterally encapsulating the first package assembly and the plurality of TIVs. In some embodiments, it further includes: one or more second package assemblies disposed on the first RDL structure; a second encapsulation laterally encapsulating one or more second package assemblies; a plurality of conductive terminals disposed on the second RDL structure; and a package substrate bonded to the interposer via the plurality of conductive terminals. In some embodiments, the inductor element includes: a coil structure and a magnetic material covering the coil structure. Attached Figure Description

[0007] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 13 and Figure 14 A cross-sectional view of an intermediate stage of the packaging structure formed according to some embodiments is shown.

[0009] Figure 4A , Figure 4B and Figure 4C A cross-sectional view of a first die having an inductor element according to various embodiments is shown.

[0010] Figure 5A , Figure 5B and Figure 5C They are shown respectively Figure 4A , Figure 4B and Figure 4C A plan view of the conductive connector.

[0011] Figure 6 A cross-sectional view of a second die according to some embodiments is shown.

[0012] Figure 12BA cross-sectional view of an integrated circuit die according to some embodiments is shown.

[0013] Figure 15 A cross-sectional view of a packaging structure according to some alternative embodiments is shown.

[0014] Figure 16A and Figure 16B A cross-sectional view of a die stack structure with inductor elements according to various embodiments is shown.

[0015] Figure 17 A cross-sectional view of a packaging structure according to some other embodiments is shown.

[0016] Figure 18 A cross-sectional view of a package assembly having an inductor element according to various embodiments is shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of this utility model. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of explanation, this document may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0019] Other features and processes may also be included. For example, test structures may be included to illustrate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, which enable testing of 3D packages or 3DICs using probes and / or probe cards. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0020] According to some embodiments, an all-in-one solution is provided to effectively integrate a local silicon interconnect (LSI) die, an active integrated voltage regulator (IVR) die, and / or an active system-on-a-chip (SoC) die within the interposer of a package structure. Compared to conventional IVR dies mounted on a package substrate, the active IVR die, with its power management integrated circuit (PMIC) and inductor elements, is embedded in the interposer, positioned closer to the upper package components. In this embodiment, the reduced distance prevents unnecessary power consumption and parasitic capacitance, resulting in better voltage regulation of electrical signals before transmission to the upper package components. Furthermore, the LSI die, active IVR die, and / or active SoC die are stacked in a single package component, which can be integrated within the interposer. In this case, the package components in the interposer communicate with the upper package components (e.g., SoC and / or HBM) via a vertical conductive path rather than a lateral RDL structure. This allows for faster inter-die transmission speeds, thereby improving the performance of the package structure.

[0021] Figures 1 to 14 The diagram illustrates an intermediate stage in the formation of a package structure 100 comprising a first die having inductor elements, according to some embodiments. Figure 1 A release film 42 is shown formed on a carrier 40. The carrier 40 may be a glass carrier, a silicon wafer, an organic carrier, etc. According to some embodiments, the carrier 40 may have a circular top view shape. The release film 42 may be formed of a polymer-based material and / or an epoxy-based heat-releasing material (e.g., a photothermal conversion (LTHC) material) that is capable of decomposition under radiation (e.g., a laser beam), allowing the carrier 40 to separate from the overlay structure to be formed in subsequent processes. According to some embodiments, the release film 42 is applied to the carrier 40 by coating.

[0022] A first redistribution layer (RDL) structure 48, comprising multiple dielectric layers 44 and multiple redistribution layers (RDLs) 46, is formed on the release film 42. For example... Figure 1As shown, a first dielectric layer 44-1 is formed on the release film 42. According to some embodiments, the dielectric layer 44-1 is formed of or contains an organic material, which may be a polymer. The organic material may also be a photosensitive material. For example, the dielectric layer 44-1 may be formed of or contain polyimide, PBO, BCB, etc. The dielectric layer 44-1 can be formed using processes such as lamination, coating (e.g., spin coating), chemical vapor deposition (CVD), etc.

[0023] A plurality of RDLs 46 (denoted as 46-1) are formed on dielectric layer 44-1. The formation of RDLs 46-1 may include patterning dielectric layer 44-1 to form via openings, forming a metal seed layer (not shown) on dielectric layer 44-1 and extending into the via openings, forming a patterned plating mask (not shown), such as photoresist, on the metal seed layer, and then performing a metal plating process to deposit a metal material (e.g., copper) on the exposed metal seed layer. The patterned plating mask and the portion of the metal seed layer covered by the patterned plating mask are then removed to leave RDLs 46-1, as shown below. Figure 1 As shown. According to some embodiments, the metal seed layer comprises a titanium layer and a copper layer above the titanium layer. The metal seed layer can be formed using, for example, PVD or a similar process. The plating process can be performed using, for example, an electrochemical plating process or an electroless plating process.

[0024] For example, Figure 1 The formation of an additional dielectric layer 44-2 and additional redistribution layers (e.g., RDLs 46-2) is further illustrated. Throughout the description, dielectric layers 44-1 and 44-2 are individually and collectively referred to as dielectric layer 44, and RDLs 46-1 and 46-2 are individually and collectively referred to as RDLs 46. According to some embodiments, dielectric layer 44-2 is first formed on RDLs 46-1. The bottom surface of dielectric layer 44-2 contacts the top surface of RDLs 46-1 and dielectric layer 44-1. Dielectric layer 44-2 may be formed of or include an organic dielectric material, which may be a polymer. For example, dielectric layer 44-2 may include a photosensitive material such as PBO, polyimide, BCB, etc. Dielectric layer 44-2 is then patterned to form via openings therein (occupied by via portions of RDLs 46-2). Therefore, some portions of RDLs 46-1 are exposed through openings in dielectric layer 44-2.

[0025] Next, RDLs 46-2 are formed on dielectric layer 44-2 to connect to RDLs 46-1. RDLs 46-2 include via portions (also called vias) extending into the dielectric layer 44-2, and trace portions (metalline portions, or RDL lines) above the dielectric layer 44-2. The formation of RDLs 46-2 can be similar to the formation of RDLs 46-1. Each via can have a tapered profile, where the upper portion is wider than the corresponding lower portion.

[0026] After RDLs 46-2 are formed, more dielectric layers and corresponding RDLs can be formed, with upper RDLs situated on and landing on their respective lower RDLs. The materials for the more dielectric layers can be selected from candidate materials of the same (or different) group as dielectric layers 44-1 and 44-2, including polymers such as polyimide, PBO, BCB, etc. Dielectric layer 44 and RDLs 46 together form the first RDL structure 48.

[0027] Reference Figure 2 After forming the first RDL structure 48, vias 45 can be formed on the first RDL structure 48. Forming the vias 45 may include depositing a metal seed layer on the RDLs 46 and forming a patterned plating mask that exposes portions of the metal seed layer. According to some embodiments, the metal seed layer may include a copper layer, a titanium layer, and a copper layer on top of a titanium layer, etc. A plating process is then performed to plate a metal material (e.g., copper, etc.) into the openings in the plating mask. The plating process may be performed using, for example, an electrochemical plating process or an electroless plating process. The plating mask is then removed, and subsequently, the exposed portions of the metal seed layer are etched to form the vias 45. The vias 45 are formed to be electrically connected to the RDLs 46.

[0028] Reference Figure 3 The first die 10 and the second die 50 are bonded to the RDLs 46. In some embodiments, the first die 10 is different from the second die 50. For example, the first die 10 is an active component die, an integrated voltage regulator (IVR) die, etc., while the second die 50 is a passive component die, an interconnect die, a bridging die, etc. Specifically, the second die 50 may include a standalone passive component (IPD) die including a capacitor, an IPD die including a resistor, an interconnect die for bridging two component dies, etc.

[0029] Figure 4AAn example first die 10A is shown. According to some embodiments of this disclosure, the first die 10 includes a voltage regulator for regulating the voltage supply to the overlying die. Specifically, the first die 10 may include a substrate 11, a component layer 12, an inductor element 20, an internal RDL structure 18, a plurality of conductive connectors 28, and inductor contacts 15.

[0030] In some embodiments, substrate 11 may comprise silicon or other semiconductor materials. Alternatively or additionally, substrate 11 may comprise other elemental semiconductor materials, such as germanium. In some embodiments, substrate 11 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 11 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, substrate 11 includes an epitaxial layer. For example, substrate 11 has an epitaxial layer covering a bulk semiconductor.

[0031] Component layer 12 may be disposed on substrate 11. In some embodiments, component layer 12 is formed on substrate 11 in a front-end (FEOL) process. Component layer 12 includes a variety of components. In some embodiments, components include active components, passive components, or combinations thereof. In some embodiments, components may include integrated circuit components. Components are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuses, or other similar components. In some embodiments, component layer 12 includes a gate structure, source / drain regions, and isolation structures, such as shallow trench isolation (STI) structures (not shown). In component layer 12, various N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) components, such as transistors or memories, may be formed and interconnected to perform one or more functions. Other components, such as capacitors, resistors, diodes, photodiodes, fuses, etc., may also be formed on substrate 11. The functions of these components may include memory, processors, sensors, amplifiers, power distribution, input / output circuits, etc. In this embodiment, component layer 12 includes a power management integrated circuit (PMIC) for power management, voltage regulation, charging functions, etc. Additionally, component layer 12 may include a PMIC and a system-on-a-chip (SoC) for logic functions. In other embodiments, component layer 12 may include an SoC and a high-bandwidth memory for memory functions.

[0032] Inductor element 20 may be disposed on and electrically connected to element layer 12. Specifically, inductor element 20 may include coil structure 22 and magnetic material 24 covering coil structure 22. Inductor element 20 also includes an insulator 26 separating coil structure 22 from magnetic material 24. In some embodiments, coil structure 22 includes a metallic material (e.g., copper), magnetic material 24 includes Fe, Co, Ni, etc., and insulator 26 includes a polymeric material such as polyimide, PBO, etc. In some alternative embodiments, the materials of coil structure 22 and magnetic material 24 may be interchanged. For example, coil structure 22 may contain Fe, Co, Ni, etc., and magnetic material 24 may contain copper. Additionally, interconnect structures (not shown) may be formed between element layer 12 and inductor element 20 to electrically couple element layer 12 and inductor element 20. Additionally, inductor element 20 may be embedded in interconnect structures to form part of interconnect structures. Interconnect structures may include multiple dielectric layers and metal wires and vias in the dielectric layers. For example, the dielectric layer may include an intermetallic dielectric (IMD) layer, which may be formed of a low-k dielectric material with a dielectric constant (k value) of less than about 3.5, less than about 3.0, or less than about 2.5. In other embodiments, the dielectric layer may include a non-low-k passivation layer, such as a silicon nitride layer, a silicon oxide layer, an undoped silicate glass (USG) layer, and / or a polymer layer.

[0033] An internal RDL structure 18 may be configured on the inductor element 20. Specifically, the internal RDL structure 18 may include one or more dielectric layers 14 and one or more conductive features 16 (sometimes referred to as a redistribution layer or redistribution line) embedded in the dielectric layers 14. More or fewer dielectric layers and conductive features may be formed in the internal RDL structure 18 as needed. In some embodiments, the dielectric layer 14 may be or may include an organic material such as a polymer, which may be a photosensitive polymer such as PBO, polyimide, etc. The dielectric layer 14 may also be formed of or include inorganic materials, such as silicon oxide, silicon nitride, etc. In some embodiments, the conductive features 16 may be or may include a metallic material such as copper.

[0034] Conductive connectors 28 may be disposed on the internal RDL structure 18. In some embodiments, conductive connectors 28 include solder areas, metal pillars, metal pads, metal bumps (sometimes referred to as microbumps), etc. The material of conductive connectors 28 may include non-solder materials, which may be formed or comprise copper, nickel, aluminum, gold, their multilayers, their alloys, etc. Conductive connectors 28 may be electrically connected to the internal RDL structure 18.

[0035] Inductor contacts 15 can be disposed adjacent to inductor element 20 and electrically connected to the internal RDL structure 18 and inductor element 20. In some embodiments, inductor contacts 15 include solder areas, metal pillars, metal pads, metal bumps (sometimes referred to as microbumps), etc. The material of inductor contacts 15 may include non-solder materials, which may be formed or comprise copper, nickel, aluminum, gold, their multilayers, their alloys, etc. Since inductor element 20 occupies a large area, the number of inductor contacts 15 at the same level as inductor element 20 cannot be increased. In this case, a smaller number of inductor contacts 15 may not be able to withstand the large current from inductor element 20, thus easily causing electromigration (EM) problems. Therefore, the internal RDL structure 18 can be disposed between inductor contacts 15 and conductive connectors 28 to distribute large current to a larger number of conductive connectors 28, thereby preventing EM problems. In some embodiments, the number of conductive connectors 28 is greater than the number of inductor contacts 15.

[0036] like Figure 4A As shown, the first die 10 also includes a planarization layer 25 for an encapsulating substrate 11, an element layer 12, an inductor element 20, and an inductor contact 15, the planarization layer 25 contacting the upper surface 18u of the internal RDL structure 18. In some embodiments, the planarization layer 25 may be or may include an organic material such as a polymer, which may be a photosensitive polymer such as PBO, polyimide, etc. Alternatively, the planarization layer 25 may also be formed of or include inorganic materials, such as silicon oxide, silicon nitride, etc. Notably, in some embodiments, the inductor element 20 is spaced from the upper surface 18u of the internal RDL structure 18 by a non-zero distance. That is, a portion of the planarization layer 25 may extend between the inductor element 20 and the upper surface 18u of the internal RDL structure 18, such that the inductor element 20 does not contact the upper surface 18u of the internal RDL structure 18. Furthermore, the planarization layer 25 may provide a flat surface for forming the internal RDL structure 18.

[0037] The first die 10 also includes a plurality of substrate through-holes (TSVs) 13 penetrating the substrate 11 to electrically connect the element layer 12. When TSVs are formed in a silicon substrate, TSVs 13 are sometimes referred to as silicon vias. In some embodiments, TSVs 13 comprise copper, nickel, solder, alloys thereof, etc. Each TSV 13 may be surrounded by a dielectric isolation liner formed of a dielectric material such as silicon oxide, silicon nitride, etc. The isolation liner electrically and physically isolates the respective TSVs 13 from the substrate 11. TSVs 13 may extend from the element layer 12 to an intermediate level between the top and bottom surfaces of the substrate 11. In some alternative embodiments, TSVs 13 may penetrate the element layer 12 to contact the interconnect structure between the element layer 12 and the inductor element 20. In some other embodiments, TSVs 13 may penetrate the element layer 12 to contact inductor contacts 15 adjacent to the inductor element 20.

[0038] It should be noted that in some embodiments, the conductive feature 16 of the internal RDL structure 18 crosses the inductor element 20, such as... Figure 4A As shown. That is, the conductive feature 16 of the internal RDL structure 18 can extend from one side of the inductor element 20 to the opposite side of the inductor element 20, such that a portion of the conductive feature 16 is located directly below (or directly above, if the first die 10A is flipped upside down) the inductor element 20. Furthermore, from the plan view of the internal RDL structure 18, the conductive connectors 28 can be arranged in an array directly below (or directly above, if the first die 10A is flipped upside down) the inductor element 20, such as... Figure 5A As shown.

[0039] However, the embodiments disclosed herein are not limited thereto. In some alternative embodiments, the conductive features 16 of the internal RDL structure 18 are arranged laterally around the inductor element 20 in a ring-like manner, such that the conductive features 16 of the internal RDL structure 18 are not positioned directly below (or directly above, if the first die 10A is flipped upside down) the inductor element 20, such as... Figure 4B As shown. In the example first die 10B, from the plan view of the internal RDL structure 18, the conductive connectors 28 can be arranged in an array directly below (or directly above, if the first die 10A is flipped upside down) the inductor element 20, as shown. Figure 5B As shown. In this embodiment, the region 21 of the internal RDL structure 18 located vertically between the conductive connector 28 and the inductor element 20 is filled only with dielectric material and has no conductive features, thereby reducing unwanted electrical coupling. The conductive connector 28 can also support the region 21 of the internal RDL structure 18 to maintain mechanical strength.

[0040] In some other embodiments, the conductive features 16 of the internal RDL structure 18 are arranged laterally around the inductor element 20 in a ring-like manner, such that the conductive features 16 of the internal RDL structure 18 are not positioned directly below (or directly above, if the first die 10A is flipped upside down) the inductor element 20. Figure 4C As shown. In the example first die 10C, from the plan view of the internal RDL structure 18, the conductive connectors 28 also laterally surround the inductor element 20 in a ring-like arrangement, as shown. Figure 5C As shown. In this embodiment, region 23 of the internal RDL structure 18 is filled only with dielectric material, and no conductive features or conductive connectors are located in region 23 (i.e., directly below the inductor element 20), thereby further avoiding unnecessary electrical coupling.

[0041] Figure 6 An example second die 50 according to some embodiments is shown. It should be understood that the second die 50 represents some possible structures for a second die and may include one or more features such as vias, interconnect paths, capacitors, etc. The second die 50 may include a substrate 54, which may be a semiconductor substrate, such as a silicon substrate. The substrate 54 may also be a dielectric substrate formed of a dielectric material such as silicon oxide or silicon nitride. According to some embodiments, regardless of whether the substrate 54 is formed of a semiconductor or dielectric material, no vias extending therein are formed. According to an alternative embodiment, vias 56 extending into the substrate 54 are formed.

[0042] In some embodiments, the second die 50 does not contain active components, such as transistors and diodes. The second die 50 may or may not contain passive components, such as capacitors, transformers, inductors, resistors, etc. In some alternative embodiments, the second die 50 includes passive components. For example, the second die 50 may be an IPD die including a capacitor 58 (which may be a deep trench capacitor) formed in the second die 50. The second die 50 may also be an IPD die including resistors.

[0043] The second die 50 may act as a bridging die (sometimes referred to as a local silicon interconnect (LSI)) and may include an interconnect structure 60 above the substrate 54. The interconnect structure 60 also includes a dielectric layer and metal lines and vias within the dielectric layer. The dielectric layer may include an inter-metal dielectric (IMD) layer. According to some embodiments, some dielectric layers are formed of low-k dielectric materials with a dielectric constant (k value) less than 3.8, and the k value may be less than about 3.0 or about 2.5. The low-k dielectric layer may be formed of carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The formation of metal lines and vias may include single-damascene and dual-damascene processes. A bonding structure 62, such as metal pillars or metal pads, is formed on the surface of the second die 50. The second die 50 may include a bridging element 61, which includes metal lines and vias. Each bridging element 61 connects two bonding structures, allowing two or more package components (e.g., component dies) to be electrically interconnected in subsequent processes using the bridging element 61.

[0044] Return to reference Figure 3 According to some embodiments, the bonding of the first die 10 and the second die 50 to the RDLs 46 can be performed by solder bonding or metal-to-metal direct bonding. For example, the first die 10 can be bonded to the RDLs 46 of the first RDL structure 48 via a conductive connector 28, while the second die 50 can be bonded to the RDLs 46 of the first RDL structure 48 via a solder area 64. After bonding, an underfiller 66 is dispensed into the gap between the first die 10, the second die 50, and their corresponding underlying first RDL structure 48, and then cured. According to some embodiments, the underfiller 66 may include a substrate and filler particles in the substrate, the substrate may include polymers, resins, epoxy resins, etc. The filler particles may be dielectric particles such as silica, alumina, boron nitride, etc., and may be spherical.

[0045] Reference Figure 7 An encapsulation 68 is formed to encapsulate the first die 10, the second die 50, and the via 45. The encapsulation 68 fills the voids between the first die 10, the second die 50, and the via 45. The encapsulation 68 may include a molding compound, a molding underfill, epoxy resin, and / or resin. After encapsulation, the top surface of the encapsulation 68 is higher than the top surface of the via 45 and the top surfaces of the second die 50 and the first die 10. The encapsulation 68 may include a substrate and filler particles in the substrate. The substrate may be a polymer, resin, epoxy resin, etc. The filler particles may be dielectric particles such as silica, alumina, boron nitride, etc., and may be spherical.

[0046] A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, is then performed to thin the encapsulation 68, the first die 10, and the second die 50 until the top surface of the via 45 is exposed. Additionally, a portion of the substrate 11 of the first die 10 is removed to expose the top surface of the TSVs 13, and a portion of the substrate 54 of the second die 50 is also removed to expose the top surface of the through-hole 56. In this case, after the planarization process, the top surfaces of the TSVs 13 and the through-hole 56 are substantially flush with the top surface of the encapsulation 68. The vias 45 may also be referred to as insulating through-holes (TIVs) because they penetrate the encapsulation 68.

[0047] Figure 8 The formation and patterning of a dielectric layer 70 according to some embodiments are illustrated. The dielectric layer 70 may be part of a subsequently formed second RDL structure 78 (e.g., Figure 9 (As shown). The dielectric layer 70 may be or may include organic materials such as polymers, which may be photosensitive polymers such as PBO, polyimide, etc. The dielectric layer 70 may also be formed of or include inorganic materials, such as silicon oxide, silicon nitride, etc. The dielectric layer 70 may be formed using processes such as lamination, coating (e.g., spin coating), chemical vapor deposition (CVD), etc.

[0048] The dielectric layer 70 is patterned using acceptable photolithography and etching techniques to form an opening 72, in which TIVs 45, TIVs 13 of the first die 10, and through-holes 56 of the second die 50 are exposed.

[0049] Figure 8 and Figure 9 The formation of a second RDL structure 78 over the first die 10 and the second die 50 is illustrated. According to some embodiments, the second RDL structure 78 includes one or more dielectric layers 74. In some embodiments, the dielectric layer 74 is formed of a non-photosensitive material, such as a molding compound, a molding underfill, silicon oxide, silicon nitride, etc. On the other hand, the dielectric layer 74 may be formed of a photosensitive material such as PBO, polyimide, etc. In some embodiments, the dielectric layer 74 may be formed using processes such as lamination, coating (e.g., spin coating), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0050] RDLs 76 can be formed in the dielectric layer 74. In some embodiments, the RDLs 76 include copper, etc., and are electrically connected to TIVs 45, TSVs 13 of the first die 10, and through-holes 56 of the second die 50. In one embodiment, the RDLs 76 can be formed by depositing a seed layer, followed by placing photoresist on top of the seed layer and patterning it with the desired pattern of the RDLs 76, and using, for example, a plating process to form a conductive material (e.g., copper, etc.) in the patterned openings of the photoresist. The photoresist can then be removed and the seed layer etched to form the RDLs 76. In some alternative embodiments, each RDLs 76 can be formed by a damascene process. As an example of a damascene process, a dielectric layer 74 is formed, and then the dielectric layer 74 is etched according to a defined photoresist pattern to form openings. Then, a copper seed layer is conformally deposited on the surface of the dielectric layer 74 and in the openings, followed by the formation of conductive material (e.g., copper) in the openings of the RDLs 76 using a plating step or deposition process. A planarization process is then performed to remove any excess conductive material and the seed layer. Some surface conductive features 76BP are formed, which may be part of the RDLs 76 or may be formed separately as under-bump metals (UBMs). In some embodiments, the second RDL structure 78 is electrically connected to the first RDL structure 48 via TIVs 45, TSVs 13 of the first die 10, and through-holes 56 of the second die 50.

[0051] In the subsequent process, such as Figure 10 As shown, a carrier exchange process is performed. In this process, the second RDL structure 78 is first bonded to the carrier 41 via a release film 43. The carrier 41 is formed of a transparent material and can be a glass carrier, ceramic carrier, etc. The release film 43 can be formed of an LTHC coated material. The carrier 40 is then separated from the first RDL structure 48. In the desorption process, a light beam (which can be a laser beam) is projected onto the release film 42, and the beam passes through the transparent carrier 40. The release film 42 is thus decomposed. The carrier 40 can detach from the release film 42, thereby desorbing (detaching) the encapsulation structure 100 from the carrier 40.

[0052] Figure 11The formation of UBMs 88 and conductive connectors 90 according to some embodiments is illustrated. UBMs 88 may be formed of or include multiples of nickel, copper, titanium, or the like. Conductive connectors 90 are then formed on the UBMs 88. Forming the conductive connectors 90 may include placing solder balls on exposed portions of the UBMs 88 and then reflowing the solder balls, thereby creating a solder area for the conductive connectors 90. According to alternative embodiments of this disclosure, forming the conductive connectors 90 includes performing a plating process to form a solder layer and then reflowing the solder layer. The conductive connectors 90 may also include non-solder metal pillars, or may have a composite structure including a solder cap on top of the metal pillars and non-solder metal pillars, which may also be formed by plating. Throughout the description, the structure located above the release film 43 may be referred to as the interposer 92. In some alternative embodiments, the second die 50 may be omitted, and only one or more first dies 10 may be embedded in the interposer 92.

[0053] Reference Figure 12A Multiple encapsulation components 94 are bonded to the interposer layer 92. Figure 12B A detailed view of an example package assembly 94 when it is an integrated circuit die is shown. The package assembly 94 can be formed in a wafer that may include different component regions, which are subsequently monomerized to form multiple integrated circuit dies. The package assembly 94 can be processed according to a suitable manufacturing process to form an integrated circuit. For example, the package assembly 94 includes a semiconductor substrate 152, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 152 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 152 has an active surface, sometimes referred to as the front side (e.g., Figure 12B The surface facing upwards) and the non-active surface sometimes referred to as the back side (e.g., Figure 12B (Surface facing downwards).

[0054] Component (represented by a transistor) 154 may be formed on the front surface of semiconductor substrate 152. Component 154 may be an active component (e.g., a transistor, diode, etc.), a capacitor, a resistor, etc. Interlayer dielectric (ILD) 156 is located above the front surface of semiconductor substrate 152. ILD 156 surrounds and may cover component 154. ILD 156 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0055] Conductive plug 158 may extend through ILD 156 to electrically and physically couple element 154. For example, when element 154 is a transistor, conductive plug 158 may couple the gate and source / drain regions of the transistor. The source / drain regions may refer individually or collectively to the source or drain, depending on the context. Conductive plug 158 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. Interconnect structure 160 is located above ILD 156 and conductive plug 158. Interconnect structure 160 interconnects with element 154 to form an integrated circuit. Interconnect structure 160 may be formed by, for example, a metallization pattern in a dielectric layer on ILD 156. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 160 is electrically coupled to element 154 through conductive plug 158.

[0056] Package assembly 94 also includes pads 162, such as aluminum pads, for external connection. Pads 162 are located on the active side of package assembly 94, such as in and / or on interconnect structure 160. One or more passivation films 164 are located on package assembly 94, such as on portions of interconnect structure 160 and portions of pads 162. Openings extend through passivation films 164 to pads 162. Die connectors 166, such as conductive pillars (e.g., formed of a metal such as copper), extend through openings in passivation films 164 and are physically and electrically coupled to a corresponding one in pad 162. Die connectors 166 may be formed, for example, by plating. Die connectors 166 are electrically coupled to corresponding integrated circuits of package assembly 94.

[0057] Optionally, solder areas (e.g., solder balls or solder bumps) can be configured on pad 162. Solder balls can be used to perform chip probe (CP) testing on package assembly 94. CP testing can be performed on package assembly 94 to determine if it is a known good die (KGD). Therefore, only package assembly 94 (i.e., KGD) will be subsequently processed and packaged, while dies that fail the CP test will not be packaged. After testing, the solder areas can be removed in subsequent processing steps.

[0058] The dielectric layer 169 may or may not be located on the active side of the package assembly 94, for example, on the passivation film 164 and the die connector 166. The dielectric layer 169 laterally encapsulates the die connector 166 and is laterally connected to the package assembly 94. Initially, the dielectric layer 169 may bury the die connector 166 such that the top surface of the dielectric layer 169 is above the top surface of the die connector 166. In some embodiments where solder regions are disposed on the die connector 166, the dielectric layer 169 may also bury the solder regions. Alternatively, the solder regions may be removed before the dielectric layer 169 is formed.

[0059] The dielectric layer 169 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; or a combination thereof. The dielectric layer 169 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the die connector 166 is exposed on the dielectric layer 169 during the formation of the package assembly 94. In some embodiments, the die connector 166 remains buried and is exposed during subsequent processes for packaging the package assembly 94. Exposing the die connector 166 may remove any solder areas that may be present on the die connector 166.

[0060] In some embodiments, package component 94 may include package components 94A and 94B with different functions. Package component 94A may include computing or logic dies, such as central processing units (CPUs), application processors (APs), systems-on-a-chip (SoCs), application-specific integrated circuits (ASICs), etc. Package component 94B may include memory dies, such as dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, high bandwidth memory (HBM) dies, microelectromechanical systems (MEMS) dies, hybrid memory cube (HMC) dies, etc. However, the embodiments disclosed herein are not limited thereto. In some alternative embodiments, package components 94A and 94B may have the same function. For example, both package components 94A and 94B include HBM dies. Although two types of package components 94 are shown, fewer or more types of package components 94 may be used.

[0061] After bonding the encapsulation component 94 to the interposer 92, an underfiller 96 is dispensed into the gap between the encapsulation component 94 and the underlying interposer 92. The encapsulation component 94 is then encapsulated in an encapsulation body 98, which may include molding compounds, molding underfillers, etc. The encapsulation body 98 may include a substrate and filler particles within the substrate. The substrate may be a polymer, resin, epoxy resin, etc. The filler particles may be dielectric particles such as silica, alumina, boron nitride, etc., and may be spherical.

[0062] Reference Figure 13 The encapsulation structure 100 is desorbed (detached) from the carrier 41. For example, desorption can be achieved by projecting a light beam (which could be a laser beam) onto the transparent carrier 41, and the beam passes through the transparent carrier 41. The release film 43 is thus broken down. The carrier 41 detaches from the release film 43, thereby desorbing (detaching) the encapsulation structure 100 from the carrier 41. The resulting encapsulation structure 100, as... Figure 13 As shown. The encapsulation structure 100 is then placed on tape 102, which can be secured to the frame 104. According to some embodiments, the encapsulation structure 100 is individualized in a sawing process and separated into multiple encapsulations 100A having the same structure as each other.

[0063] Figure 14 The diagram illustrates the bonding of IPD die 114 and package substrate 106 to package structure 100. IPD die 114 can be a capacitor die, inductor die, resistor die, etc. Package substrate 106 may include an organic dielectric layer and is sometimes referred to as an organic package substrate. Package substrate 106 can also be a cored package substrate including a core, or a coreless package substrate without a core. For example, package substrate 106 may include a dielectric core 108 and plated through-holes (PTHs, i.e., conductive tubes) 110 therein. Package substrate 106 may include wiring structures 105 and 107 formed using the dielectric layer, and conductive wiring layers within the dielectric layer. Wiring structures 105 and 107 are formed on opposite sides of the dielectric core 108 and may provide additional electrical wiring within package substrate 106.

[0064] According to an alternative embodiment, the package substrate 106 is situated within an uncut wafer and is bonded to the package structure 100 via wafer-to-wafer bonding or die-to-wafer bonding (where package 100A is in die form). According to an alternative embodiment, the package substrate 106 is a discrete substrate and is bonded to the package structure 100 via die-to-die bonding. The package substrate 106 does not contain active components such as transistors or diodes. This bonding can be achieved via conductive terminals 112. The conductive terminals 112 are formed by initially forming a solder layer through processes such as vapor deposition, plating, printing, solder transfer, and ball bonding. Once the solder layer is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. The package substrate 106 may also include conductive connectors 116, which may be ball grid array (BGA) connectors, solder balls, etc. The conductive connectors 116 can be used to input electrical signals to the package structure 100. The conductive connector 116 may include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof.

[0065] Underfill 118 is dispensed into the gap between the packaging substrate 106 and the interposer 92, for example, around the conductive terminals 112 and the IPD die 114. Alternatively, underfill 118 is dispensed onto the sidewalls of the packaging substrate 106. According to some embodiments, underfill 118 may include a substrate and filler particles within the substrate, the substrate may include polymers, resins, epoxy resins, etc. The filler particles may be dielectric particles such as silica, alumina, boron nitride, etc., and may be spherical. Underfill 118 can physically isolate the IPD die 114 from the packaging substrate 106.

[0066] According to some embodiments, a first die 10 and a second die 50 are embedded in an interposer 92. The first die 10 and the second die 50 are electrically and signal-connected to a package assembly 94. The first die 10 may include a component layer 12 and an inductor element 20 electrically connected to each other. Figure 4A and Figure 14 As shown, the electrical signal input through conductive connector 116, package substrate 106, and conductive terminal 112 is transmitted to the component layer 12 with PMIC via the second RDL structure 78 and TSVs 13, where the electrical signal undergoes a first voltage regulation. After the first voltage regulation, the electrical signal is further transmitted via the interconnect structure to the inductor element 20 for a second voltage regulation. This dual voltage regulation provides better voltage regulation of the signal before it is transmitted to the overlying multiple package components 94.

[0067] Additionally, the internal RDL structure 18 is configured to redistribute electrical signals (e.g., current) from inductor contacts 15 to conductive connections 28. In some embodiments, the number of conductive connections 28 is greater than the number of inductor contacts 15. Therefore, the internal RDL structure 18 can redistribute large currents from a smaller number of inductor contacts 15 to a larger number of conductive connections 28, thereby preventing electromigration (EM) failures. In this case, more conductive connections 28 can be arranged in an array, circular, or ring configuration to effectively support and provide voltage output to the upper package assembly 94 (e.g., SoC and / or HBM). Compared to conventional IVR dies mounted on a package substrate, the first die 10, having a PMIC element layer 12 and inductor elements 20, is embedded in an interposer layer 92, closer to the upper package assembly 94 than a conventional IVR chip. In this embodiment, the shortened distance prevents unnecessary power consumption and parasitic capacitance, resulting in better voltage regulation of the electrical signals before transmission to the upper package assembly 94. Furthermore, the first die 10 and the component layer 12 are embedded in the interposer layer 92, allowing active components (e.g., logic and / or memory components) in the component layer 12 to communicate with the upper package assembly 94 (e.g., SoC and / or HBM) via a vertical conductive path instead of through a lateral RDL structure. This results in faster transmission speeds between the first die 10 and the overlying package assembly 94, thereby improving the performance of the package structure 100.

[0068] Figure 15 A package structure 200 according to an alternative embodiment is shown. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments discussed below) indicate those formed by the same process. Figures 1 to 14 The same components are used in the embodiments shown. Therefore, the process steps and applicable materials will not be described again here.

[0069] Figure 15 The package structure 200 shown is... Figure 14 The difference in the package structure 100 shown is that the first die 10 and the second die 50 are replaced with a die stack structure 30, and the die stack structure 30 is encapsulated by the encapsulant 68 and integrated in the interposer layer 92.

[0070] Figure 16AAn example die stack structure 30A according to some embodiments is shown. The die stack structure 30A may include a second die 32 stacked on a first die 10. The first die 10 is similar to example first dies 10A, 10B, or 10C, and therefore its configuration, materials, and formation methods will not be described further herein. In some embodiments, the second die 32 may be stacked on the first die 10 in a face-to-back configuration. That is, the active surface (or front side) of the second die 32 may face the non-active surface (or back side) of the first die 10. However, the embodiments disclosed herein are not limited thereto. In some other embodiments, the second die 32 may be stacked on the first die 10 in a face-to-face or back-to-back configuration.

[0071] In some embodiments, the second die 32 may include a substrate 31 and a plurality of TSVs 33 extending through the substrate 31. The second die 32 may be bonded to the first die 10 via a hybrid bonding method or a direct bonding method. Generally, hybrid bonding methods include dielectric-to-dielectric bonding and metal-to-metal (copper-to-copper) bonding. In some embodiments, dielectric-to-dielectric bonding is fusion bonding or oxide-to-oxide bonding. Specifically, a bonding dielectric layer 19 may be formed on the substrate 11, and another bonding dielectric layer 39 may be formed on the substrate 31. The second die 32 may be picked up and placed onto the first die 10 such that the first die 10 contacts the second die 32. Additionally, the TSVs 33 of the second die 32 are substantially aligned and in direct contact with the corresponding TSVs 13 of the first die 10, and the bonding dielectric layer 39 is in direct contact with at least a portion of the bonding dielectric layer 19. In some embodiments, to facilitate hybrid bonding between the first die 10 and the second die 32, the bonding surfaces may be surface-treated. This surface treatment may include, for example, surface cleaning and activation.

[0072] After cleaning the bonding surfaces, activation of the bonding surfaces of bonding dielectric layers 19 and 39 can be performed to produce high bonding strength. For example, plasma activation can be performed to treat the top surfaces of bonding dielectric layers 19 and 39. After the activated top surfaces of bonding dielectric layers 19 and 39 come into contact with each other, a hybrid bonding step is performed. The hybrid bonding step may include a heat treatment process for dielectric bonding and a heat annealing process for conductor bonding. In some embodiments, the temperature of the heat annealing process for conductor bonding is higher than the temperature of the heat treatment process for dielectric bonding. After performing the heat annealing process for conductor bonding, bonding dielectric layer 19 is bonded to the overlying bonding dielectric layer 39, while TSVs 33 are bonded to the underlying TSVs 13.

[0073] In some embodiments, one or more dies can be stacked on the first die 10 to form a multifunctional die stack structure 30. In this case, the horizontal footprint in the interposer 92 can be effectively reduced to accommodate more dies, die stack structures, and / or other components. Furthermore, the multifunctional die stack structure 30 can reduce unnecessary communication with the overlying package assembly 94, increasing operating speed and thus improving the performance of the package structure 200. In addition, the first die 10 and the stacked second dies 32 are KGD (knock-down die) and can be further processed and packaged, while dies that fail the CP (prototype completion) test are not packaged. This improves the yield and production capacity of the package structure 200.

[0074] Figure 16B An example die stack structure 30B according to some embodiments is shown. The die stack structure 30B differs from the die stack structure 30A in that a second die 32 can be bonded to a first die 10 via solder bonding. Specifically, the second die 32 can be bonded to the first die 10 via a solder region 36. In some embodiments, forming the solder region 36 may include placing solder balls on exposed portions of TSVs 13 and then reflowing the solder balls. According to an alternative embodiment of this disclosure, forming the solder region 36 includes performing a plating process to form a solder layer and then reflowing the solder layer. The solder region 36 may also include non-solder metal pillars, or may have a composite structure including a solder cap above the metal pillars and non-solder metal pillars, which may also be formed by plating.

[0075] Figure 17 A package structure 300 according to an alternative embodiment is shown. Unless otherwise stated, the same reference numerals in this embodiment (and embodiments discussed later) indicate those formed by the same process. Figures 1 to 14 The same components are used in the embodiments shown. Therefore, the process steps and applicable materials will not be described again here.

[0076] Figure 17 The package structure 300 shown is... Figure 14 The difference in the package structure 100 shown is that the first die 10 and the second die 50 are replaced with a package assembly 80, and the package assembly 80 is encapsulated by an encapsulant 68 and integrated in an interposer 92.

[0077] Figure 18 An example package assembly 80 according to some embodiments is shown. The package assembly 80 may include a bottom die 84, an inductor element 20, an active component die 85, a passive component die 86, an internal RDL structure 18, and a plurality of conductive connectors 28.

[0078] In some embodiments, the bottom die 84 may include a substrate 81, a component layer 82 on the substrate 81, and a plurality of TSVs 83 extending through the substrate 81 to contact the component layer 82. Inductor elements 20, active component dies 85, and passive component dies 86 may be arranged side-by-side on the bottom die 84. In some embodiments, the active component die 85 may be or include computing dies, logic dies, memory dies, etc. The passive component die 86 may be or include IPD dies containing capacitors, IPD dies containing resistors, interconnect dies for bridging two component dies, etc. The active component dies 85 and passive component dies 86 may have different functions and may be bonded to the bottom die 84 by solder bonding or metal-to-metal direct bonding. The active component dies 85 and passive component dies 86 may be configured face-to-face, face-to-back, or back-to-back to be bonded to the bottom die 84.

[0079] The internal RDL structure 18 can be disposed on the inductor element 20, the active component die 85, and the passive component die 86. Conductive connectors 28 can be disposed on the internal RDL structure 18. The package assembly 80 also includes a planarization layer 25 encapsulating the bottom die 84, the inductor element 20, the active component die 85, and the passive component die 86. Underfill 66 is dispensed into the gap between the package assembly 80 and the underlying first RDL structure 48, and then cured.

[0080] It is worth noting that the internal RDL structure 18 is configured to redistribute electrical signals (e.g., current) from the inductor contacts 15 to the conductive connections 28. In some embodiments, the number of conductive connections 28 is greater than the number of inductor contacts 15. Therefore, the internal RDL structure 18 can redistribute large currents from a smaller number of inductor contacts 15 to a larger number of conductive connections 28, thereby preventing electromigration (EM) failures. Alternatively, one or more dies can be laterally stacked on the bottom die 84 to form a multifunctional package assembly 80. In this case, the horizontal footprint of the interposer 92 can be effectively reduced to accommodate more dies, package assemblies, and / or other components. In addition, the multifunctional package assembly 80 can reduce unnecessary communication with the overlying package assembly 94 to increase operating speed, thereby improving the performance of the package structure 300. Furthermore, the bottom die 84, active component die 85, and passive component die 86 are KGD (knock-down die) and can be further processed and packaged, while dies that fail the CP (protocol) test are not packaged. This improves the yield and production capacity of the packaging structure 300.

[0081] According to some embodiments, a package structure includes an interposer layer, the interposer layer including at least a first die sandwiched between a first redistributable layer (RDL) structure and a second RDL structure. The first die includes: a component layer disposed on a substrate; an inductor component disposed on the component layer; an inner RDL structure disposed on the inductor component; a plurality of conductive connectors disposed on the inner RDL structure; and inductor contacts disposed adjacent to the inductor component and electrically connecting the inner RDL structure and the inductor component. The number of the plurality of conductive connectors is greater than the number of inductor contacts.

[0082] In some embodiments, conductive features of the internal RDL structure traverse the inductor element. In some embodiments, the conductive features of the internal RDL structure laterally surround the inductor element in a ring arrangement, such that the conductive features are not positioned directly above the inductor element. In some embodiments, a plurality of conductive connectors laterally surround the inductor element in a ring arrangement in a planar view of the internal RDL structure. In some embodiments, a plurality of conductive connectors are arranged in an array on the inductor element in a planar view of the internal RDL structure. In some embodiments, the first die further includes: a plurality of substrate through-holes (TSVs) penetrating the substrate to electrically connect the element layer and the second RDL structure; and a planarization layer encapsulating the substrate, the element layer, the inductor element, and the inductor contacts to contact the bottom surface of the internal RDL structure. In some embodiments, the internal RDL structure is configured to redistribute electrical signals from the inductor contacts to the plurality of conductive connectors. In some embodiments, the interposer further includes: a second die, configured parallel to the first die; a plurality of through-insulating vias (TIVs) laterally surrounding the first die and the second die; and a first encapsulation laterally encapsulating the first die, the second die, and the plurality of TIVs. In some embodiments, the interposer further includes: a second die, vertically stacked on the first die to form a die stack structure; a plurality of through-insulating vias (TIVs) laterally surrounding the die stack structure; and a first encapsulation laterally encapsulating the die stack structure and the plurality of TIVs. In some embodiments, it further includes: one or more package components disposed on the first RDL structure; a second encapsulation laterally encapsulating one or more package components; a plurality of conductive terminals disposed on the second RDL structure; and a package substrate bonded to the interposer via the plurality of conductive terminals.

[0083] According to some embodiments, a packaging structure includes an interposer layer, the interposer layer including a first packaging assembly sandwiched between a first RDL structure and a second RDL structure. The first packaging assembly includes: a bottom die; an inductor element, an active component die, and a passive component die arranged side-by-side on the bottom die; an inner RDL structure disposed on the inductor element, the active component die, and the passive component die; and a plurality of conductive connectors disposed on the inner RDL structure to electrically connect the inner RDL structure and the first RDL structure.

[0084] In some embodiments, the first package assembly further includes: an inductor contact disposed adjacent to the inductor element and vertically sandwiched between the bottom die and the inner RDL structure, wherein the inner RDL structure is configured to redistribute electrical signals from the inductor contact to a plurality of conductive connections. In some embodiments, the bottom die includes: a substrate; an element layer disposed on the substrate; and a plurality of TSVs extending through the substrate to electrically connect the element layer and the second RDL structure. In some embodiments, the interposer further includes: a plurality of TIVs laterally surrounding the first package assembly; and a first encapsulation laterally encapsulating the first package assembly and the plurality of TIVs. In some embodiments, it further includes: one or more second package assemblies disposed on the first RDL structure; a second encapsulation laterally encapsulating one or more second package assemblies; a plurality of conductive terminals disposed on the second RDL structure; and a package substrate bonded to the interposer via the plurality of conductive terminals. In some embodiments, the inductor element includes: a coil structure and a magnetic material covering the coil structure.

[0085] According to some embodiments, a method of forming a package structure includes: forming a first die on a first RDL structure; forming a second RDL structure on the first die to form an interposer layer; and forming a plurality of conductive terminals on the second RDL structure. The first die includes: a component layer formed on a substrate; an inductor component formed on the component layer; an inner RDL structure formed on the inductor component; a plurality of conductive connectors formed on the inner RDL structure; and an inductor contact formed adjacent to the inductor component and electrically connecting the inner RDL structure and the inductor component, wherein the inner RDL structure is configured to redistribute electrical signals from the inductor contact to the plurality of conductive connectors.

[0086] In some embodiments, forming the interposer layer further includes: arranging the second die parallel to the first die; forming a plurality of TIVs laterally surrounding the first die and the second die; and forming a first encapsulation to laterally encapsulate the first die, the second die, and the plurality of TIVs. In some embodiments, forming the interposer layer further includes: vertically stacking the second die on top of the first die to form a die stack structure; forming a plurality of TIVs laterally surrounding the die stack structure; and forming a first encapsulation to laterally encapsulate the die stack structure and the plurality of TIVs. In some embodiments, it further includes: forming one or more encapsulation components on the first RDL structure; and forming a second encapsulation to laterally encapsulate one or more encapsulation components.

[0087] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or to achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this invention, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this invention.

Claims

1. A packaging structure, characterized in that, include: An intermediate layer, including a first die sandwiched between a first redistributable layer (RDL) structure and a second RDL structure, wherein the first die comprises: The component layer is disposed on the substrate; Inductor elements are disposed on the element layer; An internal RDL structure is disposed on the inductor element; Multiple conductive connectors are disposed on the internal RDL structure; and An inductor contact is disposed next to the inductor element and electrically connects the internal RDL structure to the inductor element.

2. The packaging structure according to claim 1, characterized in that, The conductive characteristics of the internal RDL structure extend across the inductor element.

3. The packaging structure according to claim 1, characterized in that, The conductive features of the internal RDL structure are arranged laterally around the inductor element in a ring-like manner, such that the conductive features are not positioned directly above the inductor element.

4. The packaging structure according to claim 1, characterized in that, The first die also includes: Multiple substrate through-holes (TSVs) penetrate the substrate to electrically connect the element layer to the second RDL structure; and A planarization layer encapsulates the substrate, the element layer, the inductor element, and the inductor contact to contact the bottom surface of the internal RDL structure.

5. The packaging structure according to claim 1, characterized in that, The internal RDL structure is configured to redistribute electrical signals from the inductor contacts to the plurality of conductive connectors, wherein the number of the plurality of conductive connectors is greater than the number of the inductor contacts.

6. The packaging structure according to claim 1, characterized in that, The intermediary layer also includes: The second die is arranged in parallel with the first die; Multiple through-insulation vias (TIVs) laterally surround the first die and the second die; and The first encapsulation body laterally encapsulates the first die, the second die, and the plurality of TIVs.

7. The packaging structure according to claim 1, characterized in that, The intermediary layer also includes: The second die is vertically stacked on top of the first die to form a die stack structure; Multiple through-insulation vias (TIVs) laterally surround the die stack structure; and The first encapsulation body laterally encapsulates the die stack structure and the plurality of TIVs.

8. A packaging structure, characterized in that, include: An intermediary layer, including a first encapsulation component sandwiched between a first RDL structure and a second RDL structure, wherein the first encapsulation component includes: Bottom core; Inductor elements, active component chips, and passive component chips are arranged side by side on the bottom chip; An internal RDL structure is disposed on the inductor element, the active component die, and the passive component die; and Multiple conductive connectors are disposed on the internal RDL structure to electrically connect the internal RDL structure to the first RDL structure.

9. The packaging structure according to claim 8, characterized in that, The first encapsulation component further includes: An inductor contact is disposed next to the inductor element and vertically sandwiched between the bottom die and the internal RDL structure, wherein the internal RDL structure is configured to redistribute electrical signals from the inductor contact to the plurality of conductive connectors.

10. The packaging structure according to claim 8, characterized in that, The bottom die includes: Substrate; Component layers, disposed on a substrate; and Multiple TSVs extend through the substrate to electrically connect the element layer to the second RDL structure.

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