High-speed sampling system of laser particle analyzer

Abstract

The utility model discloses a high-speed sampling system of a laser particle analyzer. Comprising a plurality of analog-to-digital converters, an FPGA, a DDR3, a single-chip microcomputer and an upper computer, the input end of each analog-to-digital converter is electrically connected with a sampling sensor, the output end of each analog-to-digital converter is electrically connected with the data input end of the FPGA through an SPI, and the control end of each analog-to-digital converter is electrically connected with the control signal output end of the FPGA; the DDR3 is electrically connected with a data output end of the FPGA, and the DDR3 is used for caching data of the FPGA; the single chip microcomputer is electrically connected with the FPGA; the upper computer is in communication connection with the single-chip microcomputer. According to the high-speed sampling system of the laser particle analyzer, the plurality of analog-to-digital converters are used for direct parallel synchronous sampling, and a connecting structure of an analog switch is omitted, so that the sampling rate of particle size information of the system can be remarkably improved, time sequences of data of different channels are ensured to be consistent, the data transmission efficiency is improved, and the high-speed sampling system has good flexibility and expansibility.

Description

Technical Field

[0001] This utility model relates to the field of particulate matter measurement equipment technology, and in particular to a high-speed sampling system for a laser particle size analyzer. Background Technology

[0002] In recent years, with rapid economic development, laser particle size analyzers have been increasingly widely used in industries such as pharmaceuticals, chemicals, materials science, and environmental monitoring. Particularly in the pharmaceutical field, laser particle size analyzers play a crucial role in the research and development and production of active pharmaceutical ingredients (APIs). However, because the sample volume of APIs used in testing is typically small, and the time spent through the measurement window is limited, extremely high requirements are placed on the system for sampling rate, accuracy, and data consistency to ensure that complete and representative data can be collected within a short measurement period.

[0003] Against this backdrop, laser particle size analyzers not only need to meet the requirements of high-speed sampling and high precision for pharmaceutical raw materials, but also need to possess high repeatability to ensure the stability of multiple measurements. These technical requirements subsequently extended to other fields such as chemical engineering and materials science, setting even higher standards for the detection accuracy and data consistency of smaller particle sizes. Furthermore, to handle the real-time analysis of massive amounts of data, laser particle size analyzers also need powerful data processing capabilities to support the synchronous and consistent processing of multi-channel high-speed sampling. This increased demand has not only driven the further development of particle analysis technology but also provided strong technical support for precision manufacturing and scientific research.

[0004] Traditional laser particle size analyzer sampling systems typically employ a single analog-to-digital converter (such as AD4001 or AD4002) paired with multiple analog switches (such as ADG508A or MAX358) for time-division switching to achieve multi-channel data acquisition. While this configuration offers advantages in terms of low cost and simple structure, it has significant shortcomings in the following aspects:

[0005] Real-time performance: When a single analog-to-digital converter processes multiple signals, the switching time is relatively long, which limits the overall data acquisition speed.

[0006] Sampling frequency: Due to the limited speed of a single ADC, it is difficult to achieve high-frequency data acquisition, which affects the ability to capture rapidly changing processes.

[0007] Data transmission speed: Low-speed data transmission interfaces limit the efficiency of real-time processing and analysis of large amounts of data.

[0008] Test repeatability: Switching delays between analog switches and noise interference may reduce the consistency and repeatability of test results.

[0009] In conclusion, to meet the high-precision and high-repeatability testing requirements of modern industry and scientific research, as well as the micro-measurement needs in the development of active pharmaceutical ingredients, the development of a novel, higher-performance laser particle size analyzer sampling system has become particularly urgent. This will help improve product quality, promote the development of related industries, and provide more reliable technical support for scientific research. Utility Model Content

[0010] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a high-speed sampling system for a laser particle size analyzer, which can use eight high-performance AD7689 ADCs for parallel data acquisition, and precisely control the sampling synchronization of each ADC through FPGA. Combined with DDR3 cache, SPI interface, DMA transfer and Ethernet communication, it realizes a high-efficiency, high-speed and high-precision particle size data acquisition system.

[0011] A high-speed sampling system for a laser particle size analyzer according to an embodiment of the present invention includes:

[0012] Several analog-to-digital converters, the input terminals of which are electrically connected to the sampling sensor;

[0013] The output terminal of the analog-to-digital converter is electrically connected to the data input terminal of the FPGA via SPI, and the control terminal of the analog-to-digital converter is electrically connected to the control signal output terminal of the FPGA.

[0014] DDR3, which is electrically connected to the data output terminal of the FPGA, is used to cache the data of the FPGA;

[0015] A microcontroller, which is electrically connected to the FPGA;

[0016] A host computer is connected to the microcontroller for communication.

[0017] According to some embodiments of this utility model, the microcontroller is electrically connected to the data output terminal of the FPGA, and the output data of the FPGA is transmitted to the microcontroller via DMA.

[0018] According to some embodiments of this utility model, it also includes:

[0019] An Ethernet interface is provided, which is electrically connected to the microcontroller and is also connected to the host computer via a network cable.

[0020] According to some embodiments of this utility model, the number of analog-to-digital converters is 8.

[0021] According to some embodiments of the present invention, the analog-to-digital converter is an 8-channel analog-to-digital converter.

[0022] According to some embodiments of the present invention, the FPGA is also used to dynamically detect the transmission status of the Ethernet interface.

[0023] The high-speed sampling system for laser particle size analyzer according to embodiments of this utility model has at least the following beneficial effects: By directly connecting multiple multi-channel analog-to-digital converters (ADCs) in parallel with the FPGA, the system sampling rate is significantly improved, reaching 64 times that of traditional single-channel sampling. No analog switches are needed, achieving zero-delay switching of channel data and avoiding crosstalk and distortion in traditional designs. Furthermore, the FPGA controls the CS signal to synchronously sample the multi-channel ADCs, eliminating time delays between channels and ensuring the timing consistency of the 64 channels of data. By employing DDR3 and DMA data transmission methods in conjunction with an Ethernet interface, efficient data transmission is achieved, avoiding data congestion and loss, resulting in a high data transmission rate. The use of an Ethernet interface facilitates system integration and remote data monitoring, giving the system good scalability and improving its flexibility and expandability.

[0024] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0026] Figure 1 This is a schematic diagram of the module connection of the high-speed sampling system of the laser particle size analyzer according to an embodiment of the present invention.

[0027] Figure reference numerals: Analog-to-digital converter 100, FPGA 200, DDR3 300, Microcontroller 400, Ethernet interface 410, Host computer 500. Detailed Implementation

[0028] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0029] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0030] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0031] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0032] In the description of this utility model, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this utility model. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0033] The high-speed sampling system of the laser particle size analyzer according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0034] Reference Figure 1 This utility model proposes a high-speed sampling system for a laser particle size analyzer, comprising:

[0035] Several analog-to-digital converters 100 are provided, and the input terminals of the analog-to-digital converters 100 are electrically connected to the sampling sensor.

[0036] The output of FPGA200 and analog-to-digital converter 100 is electrically connected to the data input of FPGA200 via SPI, and the control terminal of analog-to-digital converter is electrically connected to the control signal output of FPGA200.

[0037] DDR3 300 is electrically connected to the data output terminal of FPGA200, and DDR3 300 is used to cache the data of FPGA200;

[0038] Microcontroller 400, which is electrically connected to FPGA 200;

[0039] The host computer 500 communicates with the microcontroller.

[0040] Specifically, in this embodiment, there are eight analog-to-digital converters (ADCs) 100, namely ADC1 to ADC8. Preferably, all ADCs 100 are 8-channel ADCs, such as the AD7689 model. The input terminals of all ADCs 100 are electrically connected to the sampling sensor to receive the granularity information acquired by the sampling sensor and convert the granularity information from analog to digital, transmitting it to the FPGA 200 via SPI. The output terminals of all ADCs 100 are directly and electrically connected in parallel to the data input terminals of the FPGA 200 via SPI, transmitting the digital granularity information to the FPGA 200 via SPI. Simultaneously, the control signal output terminal of the FPGA 200 is electrically connected to the control terminal of the ADCs 100, controlling the CS signal of each ADC 100 through the FPGA 200. When the system enters the sampling phase, the FPGA 200 controls all ADCs 100 to simultaneously acquire data through the control signal output terminal. DDR3 Microcontroller 400 is electrically connected to the data output terminal of FPGA200 and is used to temporarily store and buffer the granularity information data received by FPGA200. The microcontroller is an STM32 microcontroller. The data input terminal of microcontroller 400 is electrically connected to the data output terminal of FPGA200, where the data output terminal of FPGA200 is an SPI interface. The host computer 500 is a computer with data calculation and processing functions. It has control software installed on it and is wirelessly or wiredly connected to microcontroller 400 through Ethernet interface 410. It is used to obtain the granularity information stored in DDR3 300 via Ethernet.

[0041] Specifically, during operation, the system first enters a multi-ADC synchronous sampling process: the FPGA200 starts up and sets all eight analog-to-digital converters 100 to a ready-to-sample state by controlling the CS (Chip Select) signal of each analog-to-digital converter 100; then the system enters the sampling phase, the FPGA200 synchronously pulls down the CS signals of the eight analog-to-digital converters 100, triggering each analog-to-digital converter 100 to collect granular information data at the same time, ensuring that the data sampling time of the 64 channels is completely consistent; after the analog-to-digital converters 100 complete sampling, the data is transmitted to the FPGA200 via SPI, and the FPGA200 sequentially receives the sampled data from the eight analog-to-digital converters 100 and temporarily stores it in its internal register. The process then proceeds to the FPGA200 control and data caching flow: After receiving data from all analog-to-digital converters 100, the FPGA200 performs data verification and transfers the verified data to the DDR3 300 cache. Subsequently, the FPGA200 manages the data storage location, using a circular queue to process the DDR3 300 cache to avoid data overwriting and loss. At the same time, the FPGA200 monitors the storage status of the DDR3 300 to ensure that the cache does not overflow. After data storage, the FPGA200 prepares the next round of sampling control signals and waits for the current buffer data to be transferred before triggering the next sampling. The system then proceeds to the DDR3 300 cache and SPI (DMA) data transfer process. Specifically, the FPGA200 divides the received sampled data into blocks and stores them in the DDR3 300 cache area, managing them in a partitioned manner to ensure seamless data transfer. Subsequently, the system uses DMA technology to transfer the data from the DDR3 300 cache to the microcontroller 400 via the FPGA200's SPI interface. DMA does not rely on the CPU during transfer, reducing the processor's workload and ensuring real-time performance and continuity even at high sampling rates. If the amount of sampled data is large or the cache area is nearly full, the system will temporarily suspend the transfer of new data until space is freed up in the cache, ensuring data integrity. Finally, the data transmission process begins at Ethernet interface 410. When the data in the buffer reaches the transmission threshold, the microcontroller 400 on the control board sends a data transmission request to the host computer 500 via Ethernet interface 410. Ethernet interface 410 automatically allocates the data transmission rate based on bandwidth. The microcontroller 400 on the control board transmits the buffered data to the host computer 500 in batches, while simultaneously monitoring the transmission status to ensure no data loss. During transmission, the FPGA 200 dynamically monitors the Ethernet transmission status, preparing for the next batch of data upload after the previous transmission is completed, ensuring seamless data transmission and system efficiency. Upon receiving the data, the host computer 500 analyzes, stores, and visualizes it, and provides feedback on the current system operating status through the control software.

[0042] By unifying the sampling timing of the analog-to-digital converter 100 with the FPGA200, multi-channel complete synchronization is achieved. Eliminating inter-channel delays enables real-time acquisition of multi-channel signals, improving data accuracy and meeting stringent sampling time requirements, providing reliable support for high-precision granular measurement. The multi-ADC design eliminates the need for analog switches, achieving zero-delay channel data switching and avoiding crosstalk and distortion common in traditional designs. Direct CS signal control of sampling time ensures high synchronization and a high signal-to-noise ratio for the 64-channel data acquisition. The system design utilizes DDR3 300 cache combined with SPI (DMA) technology, ensuring that acquired data is directly stored in the high-bandwidth cache, unaffected by transmission speed limitations. The circular queue structure of the DDR3 300 memory further enhances high-frequency read and write performance, while the combination of SPI and DMA enables non-blocking data transmission. The high-bandwidth support of the Ethernet interface 410 ensures uninterrupted and data-free data transmission to the host computer 500, meeting high-frequency real-time transmission requirements, particularly suitable for complex testing environments. The Ethernet interface 410 design provides convenient remote data access and real-time monitoring. With its 100Mbit high bandwidth, the system can quickly and stably transmit large amounts of data to the host computer 500, adapting to the high-frequency data transmission requirements in complex sampling scenarios. Meanwhile, the reliability and anti-interference capabilities of Ethernet further ensure the stability and flexibility of the transmission, meeting the high data volume and high-precision sampling environment requirements of the laser particle size analyzer.

[0043] Reference Figure 1 Furthermore, in some embodiments of this utility model, the microcontroller 400 is electrically connected to the data output terminal of the FPGA 200, and the output data of the FPGA 200 is transmitted to the microcontroller 400 via DMA.

[0044] Specifically, in this embodiment, the system uses DMA technology to transfer data in DDR3 300 to the control module through the SPI interface of FPGA200. DMA does not rely on the CPU during the transfer process, reducing the burden on the processor, so that the system can still ensure real-time performance and continuity at high sampling rates.

[0045] Reference Figure 1 Furthermore, in some embodiments of this utility model, it also includes:

[0046] Ethernet interface 410 is electrically connected to the microcontroller and communicates with the host computer 500 via a network cable.

[0047] Specifically, in this embodiment, when the data in the STM32's buffer reaches the transmission threshold, the microcontroller 400 on the control board sends a data transmission request to the host computer 500 via the Ethernet interface 410. The Ethernet interface 410 automatically allocates the data transmission rate based on the bandwidth, and the microcontroller 400 on the control board transmits the data in the buffer to the host computer 500 in batches, while simultaneously monitoring the transmission status to ensure no data loss. With a high bandwidth of 100Mbit, the system can quickly and stably transmit large amounts of data to the host computer 500, adapting to the high-frequency data transmission requirements in complex sampling scenarios. At the same time, the reliability and anti-interference capabilities of Ethernet further ensure the stability and flexibility of the transmission, meeting the high data volume and high-precision sampling environment requirements of the laser particle size analyzer.

[0048] Reference Figure 1 Furthermore, in some embodiments of this utility model, the number of analog-to-digital converters is eight.

[0049] Specifically, in this embodiment, there are eight analog-to-digital converters 100, namely AD7689-1 to AD7689-8.

[0050] Reference Figure 1 Furthermore, in some embodiments of this utility model, the analog-to-digital converter is an 8-channel analog-to-digital converter.

[0051] Specifically, in this embodiment, all analog-to-digital converters 100 are 8-channel analog-to-digital converters. By directly connecting multiple multi-channel analog-to-digital converters (ADCs) to the FPGA 200 in parallel, the system sampling rate is significantly improved, reaching 64 times that of traditional single-channel sampling.

[0052] Reference Figure 1 Furthermore, in some embodiments of this utility model, the FPGA200 is also used to dynamically detect the transmission status of the Ethernet interface 410.

[0053] Specifically, in this embodiment, during the transmission process, the FPGA200 dynamically detects the Ethernet transmission status and prepares for the next batch of data upload after the previous transmission is completed, so as to ensure the seamless connection of the entire data transmission process and the efficiency of the system.

[0054] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A high-speed sampling system for a laser particle size analyzer, characterized in that, include: Several analog-to-digital converters, the input terminals of which are electrically connected to the sampling sensor; The output terminal of the analog-to-digital converter is electrically connected to the data input terminal of the FPGA via SPI, and the control terminal of the analog-to-digital converter is electrically connected to the control signal output terminal of the FPGA. DDR3, which is electrically connected to the data output terminal of the FPGA, is used to cache the data of the FPGA; A microcontroller, which is electrically connected to the FPGA; A host computer is connected to the microcontroller for communication.

2. The high-speed sampling system for laser particle size analyzer according to claim 1, characterized in that, The microcontroller is electrically connected to the data output terminal of the FPGA, and the output data of the FPGA is transmitted to the microcontroller via DMA.

3. The high-speed sampling system for laser particle size analyzer according to claim 1, characterized in that, Also includes: An Ethernet interface is provided, which is electrically connected to the microcontroller and is also connected to the host computer via a network cable.

4. The high-speed sampling system for laser particle size analyzer according to claim 1, characterized in that, The number of analog-to-digital converters is 8.

5. The high-speed sampling system for laser particle size analyzer according to claim 4, characterized in that, The analog-to-digital converter is an 8-channel analog-to-digital converter.

6. The high-speed sampling system for laser particle size analyzer according to claim 3, characterized in that, The FPGA is also used to dynamically detect the transmission status of the Ethernet interface.

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