Storage chip module and serial interface hard disk
By vertically arranging the bare die storage layers in the storage chip module and using a single-channel data bus for access, the problem of multi-channel interference in SATA hard drives is solved, achieving efficient data transmission and reliable circuit wiring, thereby improving storage capacity and transmission rate.
Patent Information
- Application Number
- CN202520426970.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-03-12
AI Technical Summary
Existing SATA hard drives are prone to interference between their multi-channel data buses, resulting in complex circuit wiring and unstable data access.
The memory chip module employs vertically arranged storage layers of each bare die, with each layer containing a storage unit. It is coupled to the controller via a single data bus, enabling single-channel parallel access and simplifying circuit wiring and control scheduling.
It increases storage capacity and transmission rate, reduces bit error rate and error correction burden, simplifies circuit wiring and control scheduling, and improves the reliability of data access.
Smart Images
Figure CN223842634U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, specifically to a storage chip module and a serial interface hard disk. Background Technology
[0002] Since its introduction, the SATA (Serial Advanced Technology Attachment) protocol has evolved to SATA III (6Gbps), with a theoretical maximum transfer rate of 600MB / s. However, the capacity of a single SATA hard drive die is generally low. To improve overall capacity and performance, multiple small-capacity dies need to be stacked in parallel, and the SATA hard drive controller accesses these dies through multiple channels. Therefore, the controller and the multiple dies of the memory chip need to be coupled through multiple channels (i.e., multiple data buses). However, when multiple channels access different dies simultaneously, interference can easily occur between these data buses. More importantly, the memory chip needs to have more pins to couple with these data buses, as well as more complex circuit wiring and control scheduling, affecting the reliability of data access. Utility Model Content
[0003] In view of this, this application provides a storage chip module and a serial interface hard disk, which can improve the problems of mutual interference and complex circuit wiring and control scheduling that are prone to occur when storage chips are coupled with multiple channels.
[0004] This application provides a memory chip module, comprising:
[0005] Supporting substrate;
[0006] A connector, which is coupled to the carrier substrate, and the connector uses a serial interface protocol;
[0007] The controller is mounted on the support base.
[0008] At least one memory chip is disposed on the carrier substrate. Each memory chip includes at least one bare die, and each bare die includes multiple memory layers. The multiple memory layers are arranged perpendicularly to each other, and each memory layer has a number of memory cells.
[0009] A data bus is provided within the carrier substrate, and the controller is coupled to each of the memory chips via the data bus to access the memory cells of the corresponding memory layer.
[0010] Optionally, the memory chip module includes a memory chip, and the memory chip includes multiple bare dies; the memory chip is provided with multiple transmission lines, the data bus is connected to the multiple transmission lines respectively, and the multiple bare dies are coupled to the corresponding transmission lines respectively through leads.
[0011] Optionally, the memory chip module includes a first memory chip and a second memory chip. The first memory chip includes at least one first die, and the second memory chip includes at least one second die. The first memory chip has at least one first transmission line, the data bus is connected to at least one first transmission line, and at least one first die is coupled to the corresponding first transmission line through a lead. The second memory chip has at least one second transmission line, the data bus is connected to at least one second transmission line, and at least one second die is coupled to the corresponding second transmission line through a lead.
[0012] Optionally, the memory chip module includes multiple memory chips, each memory chip including a bare die; each memory chip is provided with a transmission line, and the data bus is coupled to the corresponding transmission line respectively.
[0013] Optionally, the plurality of bare die stacks are disposed within the memory chip.
[0014] Optionally, the plurality of memory chips are respectively disposed on the carrier substrate.
[0015] Optionally, the carrier substrate is a circuit board, and the controller and each memory chip are respectively coupled to the circuit board.
[0016] Optionally, the memory chip module further includes an enable line, through which the controller is coupled to the memory chip.
[0017] Optionally, the memory chip module further includes an enable line, through which the controller is coupled to the bare die.
[0018] This application provides a serial interface hard disk, including the storage chip module as described in any of the preceding claims.
[0019] As described above, in the memory chip module and serial interface hard disk of this application, stacking all the memory cells of each bare die of the memory chip can increase the storage capacity and storage density, improve the parallelism of data access, and greatly increase the transmission rate, for example, up to 2000MB / s, thereby reducing the transmission latency. Furthermore, the controller is coupled to each memory chip through a data bus, that is, parallel access is achieved through a single channel, which can avoid mutual interference between multiple channels, reduce the bit error rate and error correction burden, and at the same time help to simplify circuit wiring and control scheduling strategies, and improve the reliability of data access. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of a memory chip module according to the first embodiment of this application;
[0021] Figure 2 yes Figure 1 The diagram shows the bare die coupling structure of the memory chip module.
[0022] Figure 3 This is a schematic diagram of the structure of a memory chip module according to the second embodiment of this application;
[0023] Figure 4 yes Figure 3 The diagram shows the bare die coupling structure of the memory chip module.
[0024] Figure 5 This is a schematic diagram of the structure of a memory chip module according to the third embodiment of this application;
[0025] Figure 6 yes Figure 5 The diagram shows the bare die coupling structure of the memory chip module.
[0026] The memory chip module 1 includes a carrier substrate 11, a first surface 11a, a second surface 11b, a controller 12, a memory chip 13, a bare die 131, a data bus 14, an enable line 120, a transmission line 132, a lead 133, a connector 15, a housing 16, a first memory chip 13a, a second memory chip 13b, a first bare die 131a, a second bare die 131b, a first transmission line 132a, and a second transmission line 132b. Detailed Implementation
[0027] To address the aforementioned problems in the prior art, this application proposes that for any memory chip, multiple memory layers of each bare die are arranged perpendicularly to each other, and each memory layer has several memory cells to ensure transmission rate. The controller is coupled to each memory chip through a data bus, that is, the controller and each memory chip achieve parallel access through a single channel, thereby reducing interference and simplifying circuit wiring and control scheduling strategies.
[0028] In the memory chip module and serial interface hard disk of this application, the shape, quantity, size and other forms of various components such as memory chips and bare dies can be determined according to actual needs and are not limited in this application.
[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.
[0030] First Embodiment
[0031] Figure 1 This is a schematic diagram of the structure of a memory chip module according to the first embodiment of this application. Figure 1 As shown, the memory chip module 1 includes a carrier substrate 11, a controller 12, a memory chip 13, a data bus 14, and a connector 15.
[0032] The support substrate 11 has a first surface 11a and a second surface 11b that are arranged opposite to each other along its own thickness direction. According to the placement of the support substrate 11 in the actual scene, the first surface 11a can be called the upper surface 11a, and the second surface 11b can be called the lower surface 11b.
[0033] The memory chip 13 is disposed on the carrier substrate 11 and combined with it. Figure 1 and Figure 2 As shown, the memory chip 13 includes multiple bare dies 131, each bare die 131 including multiple memory layers, such as 32 memory layers, 64 memory layers, or other larger numbers of memory layers. These memory layers are arranged perpendicularly to each other, and each memory layer has a number of memory cells. The multiple memory cells of a single bare die 131 can be accessed in parallel, and access includes at least one of reading, writing, and erasing data. The memory chip 13 is a 3D NAND (Non-volatile Memory Device) flash memory chip.
[0034] The memory chip module 1 can be configured according to actual needs, including the number of memory chips 13, the number of bare dies 131 contained in a single memory chip 13, and the number of memory cells contained in a single bare die 131. For example, in Figure 2 In the example, a single memory chip 13 has only four bare dies 131, which is for illustrative purposes only. The controller 12 is coupled to each memory chip 13 via a data bus 14 to access the memory cells of the corresponding memory layer. This data bus 14 is located within the carrier substrate 11.
[0035] Combination Figure 1 and Figure 2As shown, the memory chip module 1 also includes an enable line 120, which is a physical circuit line. The controller 12 is coupled to the memory chip 13 through the enable line 120. The controller 12 can send a CE signal (Chip Enable signal, i.e., a signal that determines whether the memory chip 13 responds to external operations) to the memory chip 13 through the enable line 120. The memory chip 13 that receives the CE signal is determined to be able to respond to the relevant instructions transmitted by the data bus 14. The controller 12 can issue relevant instructions containing target data through the data bus 14. The memory chip 13 selects the corresponding bare die 131. The memory chip module 1 transmits the target data between the selected bare die 131 and the data bus 14 to achieve access. In other examples, the controller 12 can be directly coupled to the bare die 131 in the memory chip 13 through the enable line 120. The CE signal can select not only the memory chip 13 to be accessed, but also the bare die 131 to be accessed.
[0036] Since multiple bare dies 131 are disposed within a single memory chip 13, the area occupied within the memory chip module 1 is relatively small. Optionally, the multiple bare dies 131 of the memory chip 13 can be stacked within the memory chip 13, thereby reducing the horizontal dimension of the memory chip 13 and the space occupied by the carrier substrate 11. It should be noted that the memory chip 13 itself has a circuit board, and the multiple bare dies 131 contained in the memory chip 13 can be stacked on the circuit board of the memory chip 13 itself and then disposed on the carrier substrate 11 after molding.
[0037] In the memory chip module 1, the multiple storage layers of each bare die 131 of the memory chip 13 are arranged perpendicularly to each other, and each storage layer has several storage cells, which can improve storage capacity and storage density, improve the parallelism of data access, and greatly increase the transmission rate, for example, it can reach 2000MB / s, thereby reducing transmission latency. Furthermore, the controller 12 is coupled to the memory chip 13 through a data bus 14, that is, parallel access is achieved through a single channel. The connector 15 is coupled to the carrier substrate 11, and the connector 15 adopts a serial interface protocol, which can be implemented as a serial interface for the memory chip module 1, so that the memory chip module 1 can be plugged into other devices through the serial interface and access data according to the operating requirements of other devices. Taking the storage chip module 1 as a SATA hard drive as an example, the maximum transfer rate of the SATA hard drive is 600MB / s. It uses 3D NAND flash memory chips, and the maximum capacity of a single bare die 131 can reach 256GB and the transfer rate can reach more than 2000MB / s. Even with a single channel, it can meet the maximum transfer rate of 600MB / s. This application can avoid mutual interference between multiple channels, reduce the bit error rate and error correction burden, and at the same time help to simplify circuit wiring and control scheduling strategies, and improve the reliability of data access.
[0038] The individual bare dies 131 contained in a flash memory chip can also be referred to as flash memory bare dies. In practical scenarios, the storage cell type of a flash memory bare die can be any of the following: SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), or QLC (Quad-Level Cell).
[0039] The memory chip 13 is a separate component, such as Figure 2 As shown, it can be provided with multiple transmission lines 132. The data bus 14 is connected to multiple transmission lines 132 respectively. Each bare die 131 is coupled to the corresponding transmission line 132 through lead 133, so that the multiple bare dies 131 contained in the memory chip 13 are coupled to the controller 12.
[0040] The substrate 11 can be a circuit board.
[0041] Taking the substrate 11 as a circuit board as an example, the memory chip module 1 can be implemented as a module with data access function. The controller 12 and the memory chip 13 are respectively coupled to the circuit board. The circuit board includes, but is not limited to, PCB (Printed Circuit Board) type circuit boards, which have multiple layers of traces (i.e., copper plating) inside. Adjacent traces are insulated from each other by the circuit board material, and traces of different layers are coupled to each other through vias and conductive pillars set in the vias, that is, to achieve so-called interlayer coupling. Based on this, the data bus 14 can be a preset trace set in the circuit board. The specific form of the data bus 14 can be determined according to the adaptability of the circuit board's trace design. In addition, the controller 12 and the memory chip 13 can be mounted on the circuit board using SMT (Surface Mount Technology), that is, mounted on the first surface 11a of the carrier substrate 11 and coupled to the data bus 14 of the carrier substrate 11. This bare die 131 can also be called a memory bare die. Correspondingly, the memory chip module 1 can be regarded as a module integrating 3D NAND, such as a SATA hard drive. The controller 12 of the SATA hard drive can be divided into a front-end controller and a back-end controller. The front-end controller is connected to the host so that the host can control the memory chip module 1, and the back-end controller is connected to the 3D NAND flash memory to realize data interaction with the 3D NAND flash memory.
[0042] On the carrier substrate 11, the controller 12 and each memory chip 13 can be spaced apart. Spaced apart means that there is a minimum distance of non-zero between the two entities, that is, they do not contact each other.
[0043] Continue reading Figure 1 The memory chip module 1 may also include a housing 16, which encloses the carrier substrate 11. Here, the controller 11 and the memory chip 13 are encapsulated within the same housing 16, thus protecting the entire memory chip module 1. It should be noted that... Figure 1 In the demonstration, only the housing 16 covering the carrier base 11 is shown. This is to show that the carrier base 11 can be at least partially exposed so that the memory chip module 1 can be coupled to other devices via the connector 15.
[0044] Second Embodiment
[0045] Figure 3 This is a schematic diagram of the structure of the memory chip module according to the second embodiment of this application. Figure 4 yes Figure 3 The diagram shows the bare die coupling structure of the memory chip module. Components with the same name are identified using the same reference numerals in this application. See also... Figure 3 and Figure 4As shown, based on the description of the first embodiment above, the difference lies in that the memory chip module 1 of this embodiment includes multiple memory chips 13, and each memory chip 13 is provided with multiple bare dies 131. The two memory chips 13 shown in the figure (i.e., the first memory chip 13a and the second memory chip 13b) and the fact that each memory chip 13 includes two bare dies 131 are only illustrative examples and do not constitute a limitation on the scope of protection of this application. Any memory chip 13 includes, but is not limited to, a 3D NAND flash memory chip, and correspondingly, the memory bare die 131 can also be referred to as a flash memory bare die.
[0046] The first memory chip 13a includes at least one first die 131a, and the second memory chip 13b includes at least one second die 131b. Figure 4 The example shown is based on the first memory chip 13a, which includes two first bare dies 131a, and the second memory chip 13b, which includes two second bare dies 131b.
[0047] In this embodiment, the first memory chip 13a and the second memory chip 13b are coupled to the controller 12 through only one data bus 14, thereby achieving single-channel coupling. Figure 4 As shown, the first memory chip 13a has at least one first transmission line 132a, each first transmission line 132a can be correspondingly coupled to a first bare die 131a, the data bus 14 is connected to at least one first transmission line 132a, and at least one first bare die 131a is coupled to the corresponding first transmission line 132a through a lead 133; the second memory chip 13b has at least one second transmission line 132b, each second transmission line 132b can be correspondingly coupled to a second bare die 131b, the data bus 14 is connected to at least one second transmission line 132b, and at least one second bare die 131b is coupled to the corresponding second transmission line 132b through a lead 133.
[0048] All memory chips 13 in memory chip module 1 share the data bus 14, and all bare dies 131 contained in each memory chip 13 also share the data bus 14, which helps to simplify circuit wiring and control scheduling strategies.
[0049] The controller 12 can send CE signals to each memory chip 13 through each enable line 120, combined with Figure 4 As shown, each memory chip 13 is coupled to an enable line 120, and the controller 12 sends a CE signal to the corresponding memory chip 13 through the enable line 120. Figure 3 and Figure 4In one example, two CE signals can be sent in parallel. When the first memory chip 13a receives a CE signal, it is determined that it can respond to the relevant instructions transmitted by the data bus 14. The controller 12 can issue relevant instructions containing target data through the data bus 14. The first memory chip 13a selects the corresponding first die 131a. The memory chip module 1 transmits the target data with the selected first die 131a through the data bus 14, thereby realizing access to the first memory chip 13a. Similarly, when the second memory chip 13b receives another CE signal, it is determined that it can respond to the relevant instructions transmitted by the data bus 14. The controller 12 can issue relevant instructions containing target data through the data bus 14. The second memory chip 13b selects the corresponding second die 131b. The memory chip module 1 transmits the target data with the selected second die 131b through the data bus 14, thereby realizing access to the second memory chip 13b.
[0050] In other examples, controller 12 can be directly coupled to each bare die 131 within any memory chip 13 via enable line 120. The CE signal can select not only the memory chip 13 to be accessed, but also the bare die 131 to be accessed.
[0051] Although this second embodiment also places multiple bare dies 131 within a single memory chip 13, resulting in a smaller area occupied within the memory chip module 1, if the memory chip module 1 of this second embodiment has the same storage capacity as that of the first embodiment, for example, if the number of bare dies 131 contained is the same, then the transmission rate of this second embodiment is higher than that of the first embodiment.
[0052] Third Embodiment
[0053] Figure 5 This is a schematic diagram of the structure of the memory chip module according to the third embodiment of this application. Figure 6 yes Figure 5 The diagram shows the bare die coupling structure of the memory chip module. (See also...) Figure 5 and Figure 6 As shown, based on the description of any of the foregoing embodiments, the difference is that the memory chip module 1 of this embodiment includes a plurality of memory chips 13, and each memory chip 13 is provided with only one bare die 131. The four memory chips 13 shown in the figure, which are disposed on the upper and lower surfaces of the carrier substrate 11, are only illustrative examples and do not constitute a limitation on the scope of protection of this application.
[0054] In this embodiment, the multiple memory chips 13 of the memory chip module 1 are also coupled to the controller 12 through a data bus 14, thereby achieving single-channel coupling. Figure 6As shown, each memory chip 13 is provided with a transmission line 132, and the data bus 14 is coupled to the corresponding transmission line 132. The bare die 131 of each memory chip 13 is coupled to the data bus 14 through the transmission line 132.
[0055] The controller 12 can send CE signals to each memory chip 13 through each conduction line 120, combined with Figure 6 As shown, each memory chip 13 is coupled to an enable line 120, and the controller 12 sends a CE signal to the corresponding memory chip 13 through the enable line 120. Figure 5 and Figure 6 In one example, four CE signals can be sent in parallel. Any memory chip 13 and its die 131 that receives a CE signal are determined to be responsive to the relevant instructions transmitted via the data bus 14. The controller 12 can then issue relevant instructions containing target data via the data bus 14. The memory chip module 1 transmits the target data between itself and the selected memory chip 13's die 131 via the data bus 14, thereby achieving access. Similarly, in other examples, the controller 12 can be directly coupled to the die 131 within the memory chip 13 via the enable line 120.
[0056] If the storage capacity of the storage chip module 1 in this third embodiment is the same as that in the first and second embodiments, for example, if the number of bare dies 131 included is the same, then the transmission rate of this third embodiment is higher than that in the first and second embodiments. Furthermore, if any bare die 131 in this third embodiment is damaged, it can be reused by replacing the corresponding storage chip 13.
[0057] This application also provides a serial interface hard disk, including the storage chip module 1 of any of the foregoing embodiments, and thus can produce the beneficial effects that the storage chip module 1 of the corresponding embodiment can produce.
[0058] This application does not limit the specific type of the serial interface hard drive. For example, it can be a SATA hard drive. In addition, the carrier base 11 of the aforementioned storage chip module 1 can be part of the circuit board of the serial interface hard drive, or it can be independent of the circuit board of the serial interface hard drive. The carrier base 11 of the storage chip module 1 can be called a sub-circuit board, and the circuit board of the serial interface hard drive can be called a main circuit board. The sub-circuit board and the main circuit board are coupled together. The positional relationship between the two is not limited in this application. For example, the sub-circuit board can be smaller, the main circuit board can be larger, and the sub-circuit board is stacked on the main circuit board.
[0059] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.
[0060] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the technical solutions of the corresponding embodiments, and are not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limitations on this application.
[0061] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.
Claims
1. A memory chip module, characterized in that, include: Supporting substrate; A connector, which is coupled to the carrier substrate, and the connector uses a serial interface protocol; The controller is mounted on the support base. At least one memory chip is disposed on the carrier substrate. Each memory chip includes at least one bare die, and each bare die includes multiple memory layers. The multiple memory layers are arranged perpendicularly to each other, and each memory layer has a number of memory cells. A data bus is provided within the carrier substrate, and the controller is coupled to each of the memory chips via the data bus to access the memory cells of the corresponding memory layer.
2. The memory chip module according to claim 1, characterized in that, The memory chip module includes a memory chip, and the memory chip includes multiple bare dies; The memory chip has multiple transmission lines, the data bus is connected to the multiple transmission lines respectively, and the multiple bare dies are coupled to the corresponding transmission lines respectively through leads.
3. The memory chip module according to claim 1, characterized in that, The memory chip module includes a first memory chip and a second memory chip, wherein the first memory chip includes at least one first bare die and the second memory chip includes at least one second bare die. The first memory chip is provided with at least one first transmission line, the data bus is connected to at least one first transmission line, and at least one first bare die is coupled to the corresponding first transmission line through a lead; The second memory chip is provided with at least one second transmission line, the data bus is connected to at least one second transmission line, and at least one second bare die is coupled to the corresponding second transmission line through a lead.
4. The memory chip module according to claim 1, characterized in that, The memory chip module includes multiple memory chips, and each memory chip includes a bare die. Each of the memory chips is provided with a transmission line, and the data bus is coupled to the corresponding transmission line.
5. The memory chip module according to claim 2, characterized in that, The plurality of bare die stacks are disposed within the memory chip.
6. The memory chip module according to claim 3 or 4, characterized in that, The plurality of memory chips are respectively disposed on the carrier substrate.
7. The memory chip module according to claim 1, characterized in that, The carrier substrate is a circuit board, and the controller and each memory chip are respectively coupled to the circuit board.
8. The memory chip module according to claim 1, characterized in that, Also includes: An enable line is provided, through which the controller is coupled to the memory chip.
9. The memory chip module according to claim 1, characterized in that, Also includes: An enable line is provided, through which the controller is coupled to the bare die.
10. A serial interface hard disk, characterized in that, The memory chip module includes any one of claims 1 to 9.