Laminated chip inductor

Abstract

The laminated chip inductor comprises a base body and two outer electrodes, the base body comprises a first coil and a second coil which are arranged in a winding mode, the first coil and the second coil are stacked in the first direction, and the winding directions of the first coil and the second coil are opposite; the two outer electrodes are arranged on the two sides of the base body in the second direction respectively, the first coil and the second coil are electrically connected to the two outer electrodes, the first coil and the second coil are arranged in parallel, and the first direction is perpendicular to the second direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inductors, in particular to a laminated chip inductor. BACKGROUND

[0002] An inductor is a common electronic component, which mainly plays a role of filtering, oscillation, delay, wave trapping, signal screening, noise filtering, current stabilization and electromagnetic wave interference suppression in a circuit. According to different structures, inductors can be divided into wound inductors, thin film inductors and laminated chip inductors.

[0003] In order to make the inductor applicable to a large current circuit, in the design of a laminated inductor, a plurality of coils with consistent winding modes are generally connected in parallel to reduce the L value (inductance). However, there is a potential difference between the coils connected in parallel, which will generate a parasitic capacitance at high frequencies, so that the SRF value (Self-Resonant Frequency) is reduced, resulting in that the inductor cannot be used normally. SUMMARY

[0004] To solve at least one of the above technical problems, the present application provides a laminated chip inductor, which helps to reduce the parasitic capacitance between two coils, reduce the L value and improve the Q value, prevent the SRF value from being reduced, and the technical scheme adopted is as follows.

[0005] The laminated chip inductor provided by the present application comprises a substrate and two external electrodes, the substrate comprises a first coil and a second coil wound and arranged, the first coil and the second coil are stacked along a first direction, and the winding directions of the first coil and the second coil are opposite; two external electrodes are arranged on both sides of the substrate along a second direction, the first coil and the second coil are electrically connected to the two external electrodes, the first coil and the second coil are connected in parallel, and the first direction and the second direction are perpendicular to each other.

[0006] As an optional implementation, in some embodiments of the present application, the coil comprises at least two wound conductors stacked along the first direction, a plurality of wound conductors are sequentially electrically connected, the wound conductors located at the top layer and the bottom layer are each provided with a lead-out end, and the lead-out ends of the wound conductors located at the top layer and the bottom layer of the first coil and the second coil are electrically connected to the same external electrode.

[0007] The lead-out ends of the wound conductors located at the top layer of the first coil and the wound conductors located at the bottom layer of the second coil are electrically connected to the same external electrode.

[0008] As an optional implementation, in some embodiments of the present application, the shape of at least part of the winding conductor of the first coil is the same as the shape of at least part of the winding conductor of the second coil.

[0009] As an optional implementation, in some embodiments of the present application, the coil further comprises a connecting channel arranged in the base body along the first direction, the connecting channel electrically connecting two adjacent winding conductors.

[0010] As an optional implementation, in some embodiments of the present application, the first coil is arranged above the second coil along the first direction, and the distance between the winding conductor at the bottom layer of the first coil and the winding conductor at the top layer of the second coil is 5 μm-80 μm.

[0011] As an optional implementation, in some embodiments of the present application, the ratio of the number of turns of the first coil to the number of turns of the second coil is 0.25-4.

[0012] As an optional implementation, in some embodiments of the present application, the ratio of the winding area of the first coil to the winding area of the second coil is 0.5-2.

[0013] As an optional implementation, in some embodiments of the present application, the material of the coil is metal silver.

[0014] As an optional implementation, in some embodiments of the present application, the base body comprises a plurality of insulating layers arranged in a stack along the first direction, and the winding conductor is printed on the insulating layers.

[0015] As an optional implementation, in some embodiments of the present application, the material of the insulating layer is ferrite or ceramic.

[0016] The embodiments of the present application have at least the following beneficial effects: by arranging the first coil and the second coil along the vertical direction of the inductor between the two outer electrodes, and connecting the two ends of the first coil and the second coil to the two outer electrodes respectively, and connecting the two coils in parallel between the two outer electrodes, the L value (inductance) between the two outer electrodes can be reduced. At the same time, since the resistance between the two outer electrodes is also reduced after the coils are connected in parallel, by controlling the reduction amplitude of the L value and the resistance value, the Q value (Quality Factor) of the inductor can be improved. Specifically, in the present application, on the basis of the parallel coils, by arranging the winding directions of the two coils to be opposite, i.e. by connecting the two coils in reverse parallel, the potential difference between the two coils can be reduced, thereby reducing the parasitic capacitance between the two coils, preventing the SRF value (Self-Resonant Frequency) from being reduced, ensuring that the inductor can be used normally in a high-frequency circuit, avoiding the performance of the inductor being affected, improving the adaptability and use performance of the inductor. BRIEF DESCRIPTION OF DRAWINGS

[0017] The present application will be further illustrated below in combination with the drawings and embodiments. It should be noted that the embodiments embodied in the following drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0018] Figure 1 A structure schematic diagram of the laminated chip inductor provided for the embodiments of the present application is shown in the following figure:

[0019] Figure 2 A coil arrangement schematic diagram of the laminated chip inductor provided for the embodiments of the present application is shown in the following figure:

[0020] Figure 3 A coil arrangement schematic diagram of the laminated chip inductor of Comparative Example 1 is shown in the following figure:

[0021] Figure 4 An A-A cross-sectional view of Figure 1

[0022] Figure 5 A coil arrangement cross-sectional view of the laminated chip inductor of Comparative Example 1 is shown in the following figure:

[0023] Figure 6 A coil winding area schematic diagram of the laminated chip inductor provided for the embodiments of the present application is shown in the following figure.

[0024] Reference signs: 100, laminated chip inductor; 10, base body; 11, first coil; 111, winding conductor; 112, lead-out end; 113, connection channel; 12, second coil; 13, insulating layer; 20, outer electrode. ​DETAILED DESCRIPTION

[0025] Embodiments of the present application will be described in detail below with reference to the drawings, in which like or similar elements always designate the same or similar elements or components having the same or similar functions throughout. The embodiments described below are merely exemplary and are used to explain the present application, and should not be construed as limiting the present application.

[0026] In the description of the present application, it needs to be understood that if the terms "center", "middle", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present application.

[0027] In the description of the present application, if the meaning of several is more than one, the meaning of multiple is more than two, greater than, less than, more than, etc. are understood as not including the number, above, below, within, etc. are understood as including the number. If it is described as first, second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features.

[0028] In the description of the present application, unless otherwise explicitly specified and limited, the terms "set", "mount", "connected", "connected" should be understood broadly, for example: it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] In the description of the present application, if the description of the terms "as an embodiment", "an embodiment", "some examples", "some embodiments", "illustrative embodiments", "example", "specific example", "some examples" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0030] Please refer toFigures 1 to 3 This application provides a multilayer chip inductor 100, including a substrate 10 and two external electrodes 20. The substrate 10 includes a first coil 11 and a second coil 12 wound together, stacked along a first direction, with the winding directions of the two coils opposite. The two external electrodes 20 are respectively disposed on both sides of the substrate 10 along a second direction. The first coil 11 and the second coil 12 are electrically connected to the two external electrodes 20, and the two coils are connected in parallel. The first direction and the second direction are perpendicular to each other. Figure 1 As shown, the direction along the height of the multilayer chip inductor 100 is designated as the first direction (z-direction), the direction along the length of the multilayer chip inductor 100 is designated as the second direction (x-direction), and the direction along the width of the multilayer chip inductor 100 is designated as the third direction (y-direction). By arranging two coils between the two external electrodes 20 along the vertical direction of the multilayer chip inductor 100, with the two ends of each coil connected to the two external electrodes 20 respectively, and the two coils connected in parallel between the two external electrodes 20, the inductance (L) between the two external electrodes 20 can be reduced. At the same time, since the resistance between the two external electrodes 20 also decreases after the coils are connected in parallel, the Q value (Quality Factor) of the multilayer chip inductor 100 can be improved by controlling the decrease in the L value and the resistance value. Specifically, in this application, based on the parallel connection of the first coil 11 and the second coil 12, by setting the winding direction of the two coils to be opposite, that is, by connecting them in reverse parallel, the current direction of the two coils is opposite, which can reduce the potential difference between the two coils, thereby reducing the parasitic capacitance between the two coils, preventing the SRF value (Self-Resonant Frequency) from decreasing, ensuring that the multilayer chip inductor 100 can be used normally in high-frequency circuits, avoiding the performance of the multilayer chip inductor 100 being affected, and improving the adaptability and performance of the multilayer chip inductor 100.

[0031] In some embodiments, the coil includes at least two wound conductors 111 stacked along a first direction. The multiple wound conductors 111 are sequentially electrically connected. Both the top and bottom wound conductors 111 have leads 112, which are respectively connected to two external electrodes 20. The lead 112 of the top wound conductor 111 of the first coil 11 and the lead 112 of the bottom wound conductor 111 of the second coil 12 are electrically connected to the external electrode 20 on the same side.

[0032] Exemplarily, the laminated chip inductor 100 has a first side and a second side along the second direction, when the lead end 112 of the top layer winding conductor 111 of the first coil 11 is connected with the external electrode 20 arranged on the first side, the lead end 112 of the bottom layer winding conductor 111 of the first coil 11 is connected with the external electrode 20 arranged on the second side, the lead end 112 of the top layer winding conductor 111 of the second coil 12 is connected with the external electrode 20 arranged on the second side, and the lead end 112 of the bottom layer winding conductor 111 of the second coil 12 is connected with the external electrode 20 arranged on the first side; or when the lead end 112 of the top layer winding conductor 111 of the first coil 11 is connected with the external electrode 20 arranged on the second side, the lead end 112 of the bottom layer winding conductor 111 of the first coil 11 is connected with the external electrode 20 arranged on the first side, the lead end 112 of the top layer winding conductor 111 of the second coil 12 is connected with the external electrode 20 arranged on the first side, and the lead end 112 of the bottom layer winding conductor 111 of the second coil 12 is connected with the external electrode 20 arranged on the second side. It can be understood that when the connection positions of the lead end 112 of the top layer winding conductor 111 and the lead end 112 of the bottom layer winding conductor 111 with the external electrode 20 are fixed, a plurality of intermediate winding conductors 111 can be sequentially connected between the top layer winding conductor 111 and the bottom layer winding conductor 111 according to the shape of the winding conductor 111, and the number of the intermediate winding conductors 111 to be connected can be adaptively adjusted according to the number of turns of the coil and the specific shape of the intermediate winding conductor 111.

[0033] In some embodiments, the shape of at least part of the winding conductor 111 of the first coil 11 is the same as the shape of at least part of the winding conductor 111 of the second coil 12. By setting the shape of at least part of the winding conductor 111 of the first coil 11 to be the same as the shape of at least part of the winding conductor 111 of the second coil 12, the number of mold openings of each device of the capacitor can be reduced, which is beneficial to reduce the manufacturing difficulty of the capacitor, thereby further reducing the manufacturing cost of the capacitor.

[0034] Optionally, the top layer of the winding conductor 111 of the first coil 11 has the same shape as the top layer of the winding conductor 111 of the second coil 12, and the bottom layer of the winding conductor 111 of the first coil 11 has the same shape as the bottom layer of the winding conductor 111 of the second coil 12; for example, the top layer of the winding conductor 111 and the bottom layer of the winding conductor 111 can be arranged to have the same shape. Optionally, the first coil 11 or the second coil 12 further comprises a plurality of intermediate winding conductors 111 arranged between the top layer of the winding conductor 111 and the bottom layer of the winding conductor 111, and the plurality of intermediate winding conductors 111 can have the same shape or different shapes; the first coil 11 and the second coil 12 can have the same shape or different shapes. For example, when the first coil 11 and the second coil 12 are respectively composed of a plurality of winding conductors 111 and have the same number of turns, the first coil 11 can be reversely connected to obtain the second coil 12.

[0035] Optionally, the winding conductor 111 of the coil has an elliptical arc shape. The laminated chip inductor 100 has a first plane perpendicular to the first direction, and the orthogonal projection of the adjacent two winding conductors 111 on the first plane can form a closed ellipse. For example, the elliptical arc shape of the adjacent two winding conductors 111 can form a mirror-symmetrical or central-symmetrical structure. Of course, in other examples, the winding conductor 111 can have other shapes, and the orthogonal projection of the adjacent plurality of winding conductors 111 on the second plane can form a closed figure, and the specific shape of the winding conductor 111 is not limited herein.

[0036] In some embodiments, the coil further comprises a connecting channel 113 arranged in the base body 10 along the first direction, and the connecting channel 113 electrically connects the adjacent two winding conductors 111. By connecting the plurality of winding conductors 111 of the coil by using the connecting channel 113, the plurality of winding conductors 111 can be sequentially connected, so that the plurality of layers of winding conductors 111 are connected as a whole, and the use performance of the laminated chip inductor 100 is ensured. Specifically, the winding conductor 111 is provided with a connecting end for connecting the adjacent winding conductor 111, and the connecting end is provided with a through hole which is formed into the connecting channel 113 and filled with a conductive material. For example, the plurality of connecting channels 113 in the coil have the same shape and height.

[0037] In some embodiments, the first coil 11 is arranged above the second coil 12 in the first direction, and the spacing h between the bottom-layer winding conductor 111 of the first coil 11 and the top-layer winding conductor 111 of the second coil 12 is 5-80 μm. By controlling the spacing h in this range, on the one hand, the manufacturing process and steps of the substrate 10 can be increased without changing the number of layers of the winding conductor 111, and on the other hand, a better Q value and a lower L value can be obtained, thereby improving the performance of the multilayer chip inductor 100.

[0038] Please refer to Table 1 and Table 4, Table 1 shows the different values of the spacing h of the winding conductor 111 between the two coils in Examples 1-5. Among them, Examples 1-5 are the same in other structural settings except the spacing h. Table 4 shows the test results of L value, Q value and SRF value for different examples or comparative examples, wherein the L value and Q value are tested by Agilent 4991 impedance analyzer, and the SRF is tested by mesh tester 5071C. The setting mode of Comparative Example 1 is that the winding directions of the two coils are the same (as shown in Figure 3 and Figure 5 The setting mode of Comparative Example 2 is that there is only one coil, and the rest of the structural settings are the same as Example 1.

[0039] Table 1

[0040] Serial number Pitch h / pm Example 1 30 Example 2 5 Example 3 60 Example 4 80 Example 5 120

[0041] According to Table 1 and Table 4, compared with Comparative Example 1, by controlling the spacing h in the range of 5-80 μm (for example, Examples 1-4), the effect of reducing the L value can be achieved, and the effects of improving the Q value and SRF value can be achieved. When the spacing h is more than 80 μm (for example, Example 5), the Q value will be reduced, and it can be observed that the Q value of Example 5 is lower than that of Comparative Example 1 and close to that of Comparative Example 2. It can be seen that the spacing h controlled in the range of 5-80 μm can obtain more ideal test results of L value, Q value and SRF value.

[0042] In some embodiments, the turns ratio of the first coil 11 to the second coil 12 is 0.25-4. By controlling the turns ratio of the first coil 11 to the second coil 12 in the above range, the L value can be reduced, the L value can be adjusted in a larger range, and the flexibility of the design of the multilayer chip inductor 100 can be improved. When the turns ratio of the first coil 11 to the second coil 12 is more than 4 or less than 0.25, the performance of the multilayer chip inductor 100 is basically the same as that of a single coil, that is, it is difficult to achieve the purpose of reducing the L value and improving the Q value by connecting the two coils in parallel, and the coil material will be wasted.

[0043] Please refer to Table 2 and Table 4, Table 2 shows the different winding turns of the winding conductor 111 of the first coil 11 and the second coil 12 and the corresponding turns ratio in the embodiments 1, 6-8. In the embodiments 1, 6-8, the turns of the winding conductor 111 of the second coil 12 are all 1, and the turns of the winding conductor 111 of the first coil 11 are increased in turn, and the rest of the structure setting modes are the same. Table 4 shows the results of L value, Q value and SRF value tests for different embodiments or comparative examples. The setting mode of comparative example 1 is that the winding modes of the two coils are opposite, and the rest of the structure setting modes are the same as those of embodiment 1. The setting mode of comparative example 2 is that there is only one coil, and the rest of the structure setting modes are the same as those of embodiment 1.

[0044] Table 2

[0045]

[0046] According to Table 2 and Table 4, compared with comparative example 1, controlling the turns ratio of the first coil 11 and the second coil 12 in the range of 0.25-4 (such as embodiments 1, 6, 7) helps to improve the SRF value. When the turns ratio of the first coil 11 and the second coil 12 exceeds 4 (such as embodiment 8), compared with comparative example 2, the decrease of L value is not obvious. It can be seen that controlling the turns ratio of the first coil 11 and the second coil 12 in the above range helps to save coil material while achieving the decrease of L value.

[0047] In some embodiments, the winding area ratio of the first coil 11 and the second coil 12 is 0.5-2. By controlling the winding area ratio of the first coil 11 and the second coil 12 in the above range, it is helpful to further reduce the facing area between the winding conductors 111, thereby reducing the parasitic capacitance and improving the SRF and Q value. When the area difference between the first coil 11 and the second coil 12 is too large, that is, the winding area ratio of the first coil 11 and the second coil 12 exceeds 2 or is less than 0.5, the performance of the multilayer chip inductor 100 is basically the same as that of setting a single coil, and it is difficult to achieve the purpose of reducing L value and improving Q value by parallel connection of two coils, and it also causes waste of coil material. Because the winding area of the winding conductor 111 is limited by the preparation process and device specifications, therefore, under the premise of unchanged device specifications, if the winding area is too small, it will cause large blank area in the dielectric layer, resulting in low utilization and material waste; and if the winding area is too large even beyond the area of the device itself, the structure cannot be realized. Therefore, the winding area ratio of the first coil 11 and the second coil 12 is in the range of 0.5-2, which can ensure that the structure can be realized without wasting materials and improve the SRF and Q value.

[0048] Please refer to Table 3 and Table 4, Table 3 shows the different winding areas and area ratios of the winding conductors 111 of the first coil 11 and the second coil 12 in Embodiment 1, Embodiment 9 to Embodiment 11, wherein the winding area of the second coil 12 in Embodiment 1, Embodiment 9 to Embodiment 11 is 0.228mm 2 The rest of the structures are set in the same way. Among them, the winding area can be referred to Figure 6 The winding area is represented by the shaded part in the figure. Figure 6 Table 4 shows the results of L value, Q value and SRF value tests for different embodiments or comparative examples. The setting of Comparative Example 1 is that the winding ways of the two coils are opposite, and the rest of the structures are set in the same way as Embodiment 1. The setting of Comparative Example 2 is that there is only one coil, and the rest of the structures are set in the same way as Embodiment 1.

[0049] Table 3

[0050]

[0051] According to Table 3 and Table 4, compared with Comparative Example 1, controlling the winding area ratio of the first coil 11 and the second coil 12 in the range of 0.5-2 (such as Embodiment 1, Embodiment 9, Embodiment 10) helps to improve the SRF value. When the winding area ratio is less than 0.5 (such as Embodiment 11), the Q value is close to that of Comparative Example 2, and the effect of improving the Q value is not obvious. It can be seen that controlling the winding area ratio of the first coil 11 and the second coil 12 in the range of 0.5-2 helps to ensure the realization of the structure of the multilayer chip inductor 100 and improve the SRF and Q values.

[0052] Table 4

[0053]

[0054]

[0055] In some embodiments, the material of the coil is metal silver. Metal silver has good conductivity and low resistance, and the thermal effect is not obvious, which helps to make the multilayer chip inductor 100 obtain good performance.

[0056] In some embodiments, the substrate 10 includes a plurality of insulating layers 13 stacked in the first direction, and the winding conductors 111 are printed on the insulating layers 13. By setting the insulating layers 13 and using the stacked insulating layers 13, a continuous winding coil structure can be realized by multiple layers of winding conductors 111, and the insulating effect between each layer is realized to realize the function of the inductor coil.

[0057] In some embodiments, the material of the insulating layer 13 is ferrite or ceramic. Ferrite or ceramic has good insulation performance, which ensures the reliability of the practicality of the multilayer chip inductor 100.

[0058] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the above embodiments and various changes can be made by those skilled in the art within the scope of knowledge acquired from the present disclosure, without departing from the spirit of the present application. In addition, the embodiments of the present application and the features in the embodiments can be combined with each other in the case where there is no conflict.

Claims

1. A stacked chip inductor, characterized by: Comprising a substrate, the substrate comprising a first coil and a second coil arranged in a winding manner, the first coil and the second coil being stacked along a first direction, winding directions of the first coil and the second coil being opposite; two outer electrodes, the two outer electrodes being arranged on two sides of the substrate along a second direction, the first coil and the second coil being electrically connected to the two outer electrodes, the first coil and the second coil being arranged in parallel, the first direction being perpendicular to the second direction.

2. The stacked inductor of claim 1, wherein: The coil comprises at least two winding conductors stacked along the first direction, the winding conductors being electrically connected in sequence, the winding conductors on a top layer and on a bottom layer are each provided with a lead-out end, the two lead-out ends being respectively connected to the two outer electrodes. The lead-out end of the winding conductor on the top layer of the first coil and the lead-out end of the winding conductor on the bottom layer of the second coil are electrically connected to the outer electrode on the same side.

3. The stacked inductor of claim 2, wherein: The shape of at least part of the winding conductors of the first coil and the shape of at least part of the winding conductors of the second coil are the same.

4. The stacked inductor of claim 2, wherein: The coil further comprises a connecting channel, the connecting channel being arranged in the substrate along the first direction, the connecting channel electrically connecting two adjacent winding conductors.

5. The stacked inductor of any one of claims 1 to 4, wherein: The first coil is arranged above the second coil along the first direction, a distance between the winding conductor on the bottom layer of the first coil and the winding conductor on the top layer of the second coil is 5-80 μm.

6. The stacked inductor of any one of claims 1 to 4, wherein: A turn ratio of the first coil to the second coil is 0.25-4.

7. The stacked inductor of any one of claims 1 to 4, wherein: A winding area ratio of the first coil to the second coil is 0.5-2.

8. The stacked inductor of any one of claims 1 to 4, wherein: The material of the coil is metal silver.

9. The stacked inductor of any one of claims 1 to 4, wherein: The substrate comprises a plurality of insulating layers arranged in a stacking manner along the first direction, the winding conductors being printed on the insulating layers.

10. The stacked inductor of claim 9, wherein: The material of the insulating layer is ferrite or ceramic.

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