Interference electric therapeutic apparatus and driving circuit thereof

Abstract

The utility model discloses an interference electro-therapeutic apparatus and a drive circuit thereof. The interference electro-therapeutic apparatus comprises an FPGA chip with at least two built-in DDS function modules and at least two paths of conversion output circuits. In each path of conversion output circuit, the voltage regulation circuit outputs periodically changing reference voltage to the DAC chip; each first output end of the FPGA chip is used for outputting different serial digital signals; each first output end of the FPGA chip is connected with the input end of the DAC chip in one conversion output circuit; the output end of the DAC chip is connected with the input end of the operational amplifier chip; the output end of the operational amplifier chip is connected with the input end of the power amplifier chip; and the output end of the power amplifier chip is electrically connected with the treatment electrode. According to the invention, on the basis of realizing common output of multiple paths of different electric signals, the circuit structure is further simplified, the implementation is easy, and the complexity and the use cost of the product structure of the interference therapeutic instrument can be reduced.

Description

Technical Field

[0001] This utility model relates to the field of interference current therapy technology, and in particular to a driving circuit for an interference current therapy device and the interference current therapy device itself. Background Technology

[0002] Interference current (also known as cross-current) therapy is a method of treating diseases by introducing two or more different medium-frequency alternating currents into the human body in a cross-sectional manner. The interference field is created at the intersection of the electric lines, generating low-frequency modulated pulsed currents in deep tissues. An interference current therapy device is a physiotherapy device used to implement interference current therapy.

[0003] Based on the working principle of the above-mentioned interference current therapy, it can be seen that the interference current therapy device needs to output at least two different medium-frequency alternating currents simultaneously during the actual physiotherapy process, which makes the circuit structure of the interference current therapy device relatively complex. Utility Model Content

[0004] The purpose of this invention is to provide a driving circuit and an interference electrotherapy device, which can simplify the circuit structure of the interference electrotherapy device to a certain extent and reduce the cost of using the interference electrotherapy device.

[0005] To solve the above-mentioned technical problems, this utility model provides a driving circuit for an interferential electrotherapy device, including an FPGA chip with at least two DDS functional modules built in and at least two conversion output circuits.

[0006] Each of the aforementioned conversion output circuits includes a DAC chip, a voltage regulation circuit, an operational amplifier chip, and a power amplifier chip.

[0007] The output terminal of the voltage regulation circuit is connected to the reference voltage input terminal of the DAC chip, and is used to output a periodically changing reference voltage to the DAC chip;

[0008] Each first output terminal of the FPGA chip is used to output different serial digital signals; each first output terminal of the FPGA chip is connected to the input terminal of the DAC chip in one of the conversion output circuits; the output terminal of the DAC chip is connected to the input terminal of the operational amplifier chip; the output terminal of the operational amplifier chip is connected to the input terminal of the power amplifier chip; and the output terminal of the power amplifier chip is electrically connected to the treatment electrode.

[0009] In one optional embodiment of this application, the voltage regulation circuit further includes a first RC filter circuit, a voltage follower, and a first resistor;

[0010] Each second output terminal of the FPGA chip is connected to the input terminal of the RC filter circuit in one of the conversion output circuits; the output terminal of the first RC filter circuit is connected to the positive input terminal of the voltage follower; the inverting input terminal and the output terminal of the voltage follower are connected through the first resistor; the output terminal of the voltage follower is connected to the reference voltage input terminal of the DAC chip.

[0011] Each second output terminal of the FPGA chip is used to output a PWM signal whose duty cycle varies according to a set period; the first RC filter circuit is used to modulate the PWM signal into a DC signal.

[0012] In an optional embodiment of this application, the non-inverting input terminal of the operational amplifier chip is connected to the output terminal of the DAC chip through a second resistor; the inverting input terminal of the operational amplifier chip is connected to the output terminal of the voltage follower through a third resistor; and the output terminal and the inverting input terminal of the operational amplifier chip are connected through a fourth resistor.

[0013] The third resistor and the fourth resistor have the same resistance value.

[0014] In an optional embodiment of this application, a second RC filter circuit is further provided between the output terminal of the power amplifier chip and the power amplifier chip.

[0015] In one optional embodiment of this application, the conversion output circuit further includes an isolation transformer;

[0016] The output terminal of the power amplifier chip is connected to the primary coil of the isolation transformer; the treatment electrode is connected to the secondary coil of the isolation transformer.

[0017] In an optional embodiment of this application, a filter circuit is further provided between the output terminal of the power amplifier chip and the primary coil of the isolation transformer.

[0018] In one optional embodiment of this application, the filtering circuit includes an LC filter circuit and an RC filter circuit connected in series between the output terminal of the power amplifier chip and the primary coil of the isolation transformer.

[0019] In one optional embodiment of this application, the number of the conversion output circuits is an integer multiple of three;

[0020] Among them, every three of the aforementioned conversion output circuits form a conversion output circuit group;

[0021] The first output terminal of the FPGA chip outputs three different serial digital signals to the same group of conversion output circuits, so that the analog electrical signals output by the same group of conversion output circuits are different in at least one of the three parameters: frequency, amplitude, and phase.

[0022] An interferential electrotherapy device includes at least two pairs of therapeutic electrodes and a driving circuit for the interferential electrotherapy device as described in any of the preceding claims.

[0023] The output terminals of one conversion output circuit in the drive circuit of each pair of therapeutic electrodes and the interferential current therapy device are electrically connected.

[0024] In one optional embodiment of this application, the logarithm of the treatment electrode is 3N, where N is a positive integer;

[0025] Furthermore, every three pairs of the treatment electrodes form an electrode group; the three pairs of treatment electrodes in the same group are used to synchronously output electrical signals.

[0026] This utility model provides an interferential electrotherapy device and its driving circuit. The interferential electrotherapy device includes an FPGA chip with at least two built-in DDS functional modules and at least two conversion output circuits. Each conversion output circuit includes a DAC chip, a voltage regulation circuit, an operational amplifier chip, and a power amplifier chip. The output terminal of the voltage regulation circuit is connected to the reference voltage input terminal of the DAC chip, and is used to output a periodically changing reference voltage to the DAC chip. Each first output terminal of the FPGA chip is used to output different serial digital signals. Each first output terminal of the FPGA chip is connected to the input terminal of the DAC chip in one of the conversion output circuits. The output terminal of the DAC chip is connected to the input terminal of the operational amplifier chip. The output terminal of the operational amplifier chip is connected to the input terminal of the power amplifier chip. The output terminal of the power amplifier chip is electrically connected to the treatment electrode.

[0027] In the driving circuit of this application, an FPGA chip with multiple built-in DDS functional modules is used instead of multiple DDS chips, which is equivalent to integrating multiple DDS functional modules into the same FPGA chip, thereby reducing the number of chips to a certain extent and simplifying the driving circuit structure. Based on this, the multiple first output terminals of the FPGA chip output different serial digital signals to each conversion output circuit, and a voltage regulation circuit outputs a periodically changing reference voltage to the DAC chip. The DAC chip in each conversion output circuit converts the corresponding serial digital signal into a corresponding analog electrical signal, which is then processed sequentially by an operational amplifier chip and a power amplifier chip before being output to the corresponding therapeutic electrode. This allows each conversion output circuit to output different therapeutic electrodes, thereby enabling multiple different electrical signals to jointly form mutually interfering currents within the human body, achieving the purpose of physiotherapy. This application simplifies the driving circuit structure by achieving the joint output of multiple different electrical signals, making it easy to implement and reducing the complexity and cost of the interference therapy device. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the drive circuit of the interferential current therapy device provided in the embodiments of this application;

[0030] Figure 2 Timing diagram of two analog electrical signals provided for embodiments of this application;

[0031] Figure 3 This is a schematic diagram of the framework structure of the driving circuit of the interferential current therapy device provided in the embodiments of this application. Detailed Implementation

[0032] The core of this utility model is to provide an interference electrotherapy device and its driving circuit, which helps to simplify the circuit structure and thus simplify the product structure of the interference therapy device.

[0033] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] like Figure 1 As shown, Figure 1 This is a schematic diagram of the drive circuit of the interferential current therapy device provided in the embodiments of this application.

[0035] In one specific embodiment of this application, the driving circuit of the interferential electrotherapy device may include:

[0036] An FPGA chip 1 with at least two DDS function modules and at least two conversion output circuits 2 are built in.

[0037] Each of the conversion output circuits 2 includes a DAC chip, a voltage regulation circuit, an operational amplifier chip U1, and a power amplifier chip U2.

[0038] The output of the voltage regulation circuit is connected to the reference voltage input of the DAC chip, and is used to output a periodically changing reference voltage to the DAC chip.

[0039] Each first output terminal of FPGA chip 1 is used to output different serial digital signals; each first output terminal of FPGA chip 1 is connected to the input terminal of DAC chip in one-way conversion output circuit 2; the output terminal of DAC chip is connected to the input terminal of operational amplifier chip U1; the output terminal of operational amplifier chip U1 is connected to the input terminal of power amplifier chip U2; the output terminal of power amplifier chip U2 is electrically connected to the therapeutic electrode.

[0040] It should be noted that the DDS function module built into the FPGA chip 1 in this application is a module capable of implementing the functions of a DDS chip. DDS is the abbreviation for Direct Digital Synthesizer. A typical DDS chip consists of a phase accumulator and a phase-amplitude converter, and works in conjunction with a DAC (Digital-to-Analog Converter) chip. That is, a digital code of a sine wave is generated and applied to the DAC chip to finally synthesize a sine wave signal. However, the amplitude of the sine wave is not linear, but changes periodically. Unlike the DDS chip working with a DAC chip, this application uses the FPGA chip 1 to work in conjunction with the DAC chip. The FPGA chip 1 directly writes a waveform digital table, and based on this waveform digital table, outputs a serial digital signal with the same digital code as the DDS chip. After conversion by the DAC chip, the corresponding analog signal can be directly obtained.

[0041] like Figure 2 As shown, Figure 2 The figure shows the timing diagram of the two analog electrical signals output by the two-way conversion output circuit 2; these analog electrical signals are also known as intermediate frequency current signals. Figure 2 The amplitudes of the two analog signals change periodically, and there is a phase difference between analog signal A and analog signal B.

[0042] It is understandable that, as long as there is a corresponding waveform digital table, any waveform, frequency, and amplitude signal can be written in the FPGA through an encoding program; and this encoding program is based on conventional computer technology. In this application, only an FPGA chip 1 with this function is used in combination with a DAC chip to realize the output of multiple current signals required in the interference electrotherapy device, without involving any improvement to the computer program.

[0043] Based on this, according to the physiotherapy principle of the interference point therapy device, in actual physiotherapy, it is necessary to output two or more different intermediate frequency currents simultaneously to act on the human body. Therefore, the FPGA chip 1 in this application should have two built-in DDS function modules, that is, the FPGA chip 1 can output at least two different serial digital signals, and each serial digital signal is input into the DAC chip in the conversion output circuit 2, and is amplified and modulated by each operational amplifier chip U1 and power amplifier chip U2 in sequence, and finally at least two different current signals can be output to act on the human body.

[0044] In practical applications, an interferential electrotherapy device needs to output at least two current signals to the same location on the human body. If multiple different locations on the human body need to be treated simultaneously, obviously more current signals need to be output simultaneously. If each current signal is output through a DDS chip in conjunction with a DAC chip, then a large number of DDS chips will be required for so many current signals. This not only makes the drive circuit structure of the entire interferential electrotherapy device complex, but also increases the cost of using the interferential electrotherapy device to a certain extent.

[0045] Based on this, this application directly uses FPGA chip 1 instead of DDS chip. Taking advantage of the fact that a single FPGA chip 1 can integrate a larger number of DDS functional modules, the drive circuit structure in the interference electrotherapy device is greatly simplified.

[0046] Based on the above discussion, such as Figure 1 As shown, the FPGA chip 1 in this embodiment has multiple first output terminals, namely Figure 1 The pins P11, P21, and P31 in the FPGA chip 1 are used for outputting serial digital signals. Each first output terminal of the FPGA chip 1 can output a serial digital signal, and each serial digital signal is different from the others. The DAC chip in each conversion output circuit 2, combined with the reference voltage input by the voltage adjustment circuit, performs digital-to-analog conversion on the serial digital signal output by the FPGA chip 1 to form an analog signal. The analog signal is then amplified by the operational amplifier chip U1 and the power amplifier chip U2 to output a medium-frequency electrical signal that meets the physiotherapy requirements. Because the serial digital signals output by the FPGA chip 1 to each conversion output circuit 2 are different, the medium-frequency electrical signals (i.e., analog electrical signals) output by each conversion output circuit 2 are ultimately different in at least one of amplitude, frequency, and phase, thus meeting the physiotherapy requirements of the interference electrotherapy device.

[0047] In addition, such as Figure 2 As shown, the amplitude of the intermediate frequency current signal output by each conversion output circuit 2 changes periodically. For the DAC chip, the amplitude of its output analog signal is determined by the voltage value input to its reference voltage input terminal, that is, by the voltage value output by the voltage regulation circuit.

[0048] In one optional embodiment of this application, the voltage regulation circuit may specifically include:

[0049] The first RC filter circuit 21, voltage follower U3, and first resistor R1;

[0050] Each second output terminal of FPGA chip 1 is connected to the input terminal of the RC filter circuit in one-way conversion output circuit 2; the output terminal of the first RC filter circuit 21 is connected to the positive input terminal of voltage follower U3; the inverting input terminal and output terminal of voltage follower U3 are connected through the first resistor R1; the output terminal of voltage follower U3 is connected to the reference voltage input terminal of DAC chip.

[0051] Each second output terminal of FPGA chip 1 is used to output a PWM signal whose duty cycle changes according to a set period; the first RC filter circuit 21 is used to modulate the PWM signal into a DC signal.

[0052] Reference Figure 1 In this embodiment, each second output terminal of FPGA chip 1 (e.g. Figure 1 Pins P12, P22, and P32 are all used to output PWM signals. In addition, the first RC filter circuit 21 includes a fifth resistor R5 and a first capacitor C1C1. After the PWM signal is filtered by the first RC filter circuit 21, the PWM signal can be converted into a DC signal. Obviously, the amplitude of the DC signal is directly determined by the duty cycle of the PWM signal and is proportional to the duty cycle of the PWM signal. Therefore, when the DC signal is input to the non-inverting input terminal of the voltage follower U3, the inverting input terminal and the output terminal of the voltage follower U3 are connected through the fourth resistor R4.

[0053] Based on the operating characteristics of voltage follower U3, its output terminal can output a voltage value of the same amplitude as the reference voltage of the DAC chip. Since the duty cycle of the PWM signal determines the amplitude of the DC signal input to voltage follower U3, which in turn determines the reference voltage input to the DAC chip, the second output terminal of FPGA chip 1 outputs a PWM signal that changes according to a set period. This causes the reference voltage of the DAC chip to change dynamically, thereby meeting the amplitude requirements of the analog electrical signals output by each conversion output circuit 2.

[0054] In addition, Figure 1In the circuit diagram shown, the first RC filter circuit 21 contains only a fifth resistor R5 and a first capacitor C1. The first end of the fifth resistor R5 is connected to the second output terminal of the FPGA chip 1, and the second ends of both the fifth resistor R5 and the first capacitor C1 are connected to the non-inverting input terminal of the voltage follower U3, while the second end of the first capacitor C1 is grounded. However, in practical applications, to ensure the filtering effect of the first RC filter circuit 21, it can contain multiple RC filter circuits connected in series between the FPGA chip 1 and the voltage follower U3. Each RC filter circuit contains a capacitor and a resistor, so that the PWM signal is filtered by the first RC filter circuit 21 to form a DC signal.

[0055] Based on the above embodiments, in one specific implementation of this embodiment, each conversion output circuit 2 may further include:

[0056] The non-inverting input terminal of op-amp chip U1 is connected to the output terminal of DAC chip through the second resistor R2; the inverting input terminal of op-amp chip U1 is connected to the output terminal of voltage follower U3 through the third resistor R3; the output terminal and inverting input terminal of op-amp chip U1 are connected through the fourth resistor R4.

[0057] Among them, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are the same.

[0058] Reference Figure 1 The conversion output circuit 2 in the middle can be determined as follows: (1); where, , These correspond to the resistance values ​​of the third resistor R3 and the fourth resistor R4, respectively. ; The reference voltage output at the output terminal of voltage follower U3; This is the input voltage at the inverting input terminal of the operational amplifier chip U1; This is the output voltage at the output terminal of the operational amplifier chip U1.

[0059] Based on the "virtual open" characteristic of operational amplifier chip U1, that is, the current at the positive input terminal of operational amplifier chip U1 is 0, we can obtain ; This refers to the output voltage at the output terminal of the DAC chip. This is the input voltage at the non-inverting input terminal of the operational amplifier chip U1.

[0060] Based on the "virtual short" characteristic of operational amplifiers, that is, the voltage at the non-inverting input terminal of operational amplifier chip U1 is equal to the voltage at its negative input terminal, we can obtain... Therefore, we can obtain .

[0061] Therefore, combined , and Equation (1) above can be derived to determine: (2).

[0062] Based on the output voltage relationship of the DAC chip, it can be determined that and The following conditions must be met: (3); where D is the digital signal output from the first output terminal of FPGA chip 1; n is the resolution of DAC chip.

[0063] Combination Figure 2 and Figure 3 You can get: (4); Obviously, formula (4) is the relationship between the analog signal output by the DAC chip and the digital signal output by the first output terminal of the FPGA chip 1.

[0064] Based on the above embodiments, in the conversion output circuit 2 of this embodiment, a second RC filter circuit 22 is further provided between the output terminal and the input terminal of the power amplifier chip U2.

[0065] like Figure 1 As shown, the second RC filter circuit 22 includes a sixth resistor R6 and a second capacitor C2. The first end of the sixth resistor R6 is connected to the output terminal of the operational amplifier chip U1, and the second end of the sixth resistor R6 and the first end of the second capacitor C2 are both connected to the input terminal of the power amplifier chip U2. The second end of the second capacitor C2 is grounded. The second RC filter circuit 22 can filter the noise output by the operational amplifier chip U1 to a certain extent and ensure the smoothness of the analog signal.

[0066] Based on this, the conversion output circuit 2 in this embodiment may further include an isolation transformer T;

[0067] The output terminal of the power amplifier chip U2 is connected to the primary coil of the isolation transformer T; the treatment electrode is connected to the secondary coil of the isolation transformer T.

[0068] In this embodiment, the cooperation between the power amplifier chip U2 and the isolation transformer T can jointly improve the current output capability of the drive circuit. In addition, the power amplifier chip U2 has a protection circuit that can realize protection functions such as overvoltage, overcurrent, overheating, and short circuit, thereby improving the working performance of the drive circuit.

[0069] In addition, in another specific implementation of this embodiment, a filter circuit 23 is provided between the output terminal of the power amplifier chip U2 and the primary coil of the isolation transformer T.

[0070] Reference Figure 1In this embodiment, the filter circuit 23 includes an LC filter circuit and an RC filter circuit connected in series between the output terminal of the power amplifier chip U2 and the primary coil of the isolation transformer T.

[0071] It is understood that in this embodiment, the first and second output terminals of the power amplifier chip U2 are electrically connected to the two ends of the primary coil of the isolation transformer T, respectively. Therefore, a first inductor L1 is provided between the first output terminal of the power amplifier chip U2 and the first output terminal of the primary coil, with its first end connected to the first output terminal of the power amplifier chip U2. The second end of the first inductor L1 is connected to the first end of the third capacitor C3 and the first end of the fifth capacitor C5. The second end of the third capacitor C3 is grounded, and the second end of the fifth capacitor C5 and the first end of the seventh resistor R7 are both connected to the first end of the primary coil. Between the second output terminal of the power amplifier chip U2 and the second end of the primary coil, a second inductor L2 is provided, with its first end connected to the second output terminal of the power amplifier chip U2. The second end of the second inductor L2 is connected to the first end of the fourth capacitor C4 and the first end of the sixth capacitor C6. The second end of the fourth capacitor C4 is grounded, and the second end of the sixth capacitor C6 and the second end of the seventh resistor R7 are both connected to the second end of the primary coil.

[0072] As mentioned earlier, the FPGA chip 1 in this application can be connected to a multi-channel conversion output circuit 2; when performing physiotherapy on each position of the human body, at least two channels of intermediate frequency current need to be output to achieve the physiotherapy. Therefore, as Figure 3 As shown, in one specific embodiment of this application, the number of the conversion output circuits 2 can be an integer multiple of three;

[0073] Among them, every three-way conversion output circuit group 20 forms a conversion output circuit group 20;

[0074] The first output terminal of FPGA chip 1 outputs three different serial digital signals to the same set of conversion output circuits 2, so that the analog electrical signals output by the same set of conversion output circuits 2 are different in at least one of the three parameters: frequency, amplitude and phase.

[0075] In this embodiment, a three-way conversion output circuit group 20 is formed into a conversion circuit group. Thus, the three-way conversion output can be short-circuited to output three different analog electrical signals. When the three analog electrical signals are used to treat the same position of the human body at the same time, three-dimensional mid-frequency current therapy can be achieved on the same position of the human body.

[0076] like Figure 3 As shown, the FPGA chip 1 in this embodiment can be connected to N sets of conversion output circuit groups 20. Thus, in practical applications, the interference electrotherapy device can achieve synchronous physiotherapy on different body positions of the same patient, or synchronous physiotherapy on different patients.

[0077] In summary, the driving circuit of this application utilizes an FPGA chip with multiple built-in DDS functional modules instead of multiple DDS chips, effectively integrating multiple DDS functional modules onto a single FPGA chip. This reduces the number of chips and simplifies the driving circuit structure. Furthermore, the FPGA chip's multiple first output terminals output different serial digital signals to each conversion output circuit. A voltage regulation circuit outputs a periodically changing reference voltage to the DAC chip. Each conversion output circuit's DAC chip converts the corresponding serial digital signal into a corresponding analog electrical signal, which is then processed sequentially by an operational amplifier chip and a power amplifier chip before being output to the corresponding therapeutic electrode. This allows each conversion output circuit to output different therapeutic electrodes, resulting in multiple different electrical signals interacting to create interfering currents within the body, thus achieving the therapeutic effect. This application simplifies the driving circuit structure by achieving the simultaneous output of multiple different electrical signals, making it easier to implement and reducing the complexity and cost of the interference therapy device.

[0078] This application also provides an embodiment of an interferential electrotherapy device, which includes:

[0079] At least two pairs of treatment electrodes and a drive circuit for the interferential electrotherapy device as described in any of the preceding items;

[0080] The output terminal of one conversion output circuit in the drive circuit of each pair of treatment electrodes and interferential current therapy device is electrically connected.

[0081] It is understood that in the driving circuit of the interferential current therapy device of this embodiment, the output terminal of each conversion output circuit should be connected to a pair of treatment electrodes; specifically as follows: Figure 1 As shown, the two treatment electrodes are connected to the two ends of the secondary coil of the isolation transformer T. Therefore, the number of treatment electrodes should be the same as the number of output conversion circuits.

[0082] Optionally, the number of treatment electrodes is 3N, where N is a positive integer;

[0083] Furthermore, each group of three pairs of treatment electrodes forms an electrode group; the three pairs of treatment electrodes in the same group are used to synchronously output electrical signals.

[0084] It is understood that in this embodiment, every three pairs of treatment electrodes are used to synchronously output three different medium-frequency current signals to the same location on the human body, so as to realize three-dimensional current therapy on that part of the human body.

[0085] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0086] This article uses specific examples to illustrate the principles and implementation methods of this utility model. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made to this utility model without departing from the principles of this utility model, and these improvements and modifications also fall within the protection scope of the claims of this utility model.

Claims

1. A drive circuit for an interferential electrotherapy apparatus, characterized in that, The FPGA chip comprises at least two DDS function modules and at least two conversion output circuits; Each of the conversion output circuits comprises a DAC chip, a voltage regulating circuit, an operational amplifier chip and a power amplifier chip; The output end of the voltage regulating circuit is connected with the reference voltage input end of the DAC chip, and is used for outputting a periodically changed reference voltage to the DAC chip; Each first output end of the FPGA chip is used for outputting a different serial digital signal; each first output end of the FPGA chip is connected with the input end of the DAC chip in one of the conversion output circuits; the output end of the DAC chip is connected with the input end of the operational amplifier chip; the output end of the operational amplifier chip is connected with the input end of the power amplifier chip; and the output end of the power amplifier chip is connected with a treatment electrode.

2. The drive circuit of the interferential electric therapeutic apparatus according to claim 1, wherein The voltage regulating circuit further comprises a first RC filter circuit, a voltage follower and a first resistor; Each second output end of the FPGA chip is connected with the input end of the RC filter circuit in one of the conversion output circuits; the output end of the first RC filter circuit is connected with the positive input end of the voltage follower; the negative input end and the output end of the voltage follower are connected through the first resistor; and the output end of the voltage follower is connected with the reference voltage input end of the DAC chip; Each second output end of the FPGA chip is used for outputting a PWM signal with a duty cycle changing according to a set period; and the first RC filter circuit is used for modulating the PWM signal into a direct current signal.

3. The drive circuit of the interferential electrotherapeutic apparatus according to claim 2, wherein the drive circuit is configured to generate the first and second drive signals with a frequency of 10 to 100 kHz. The same direction input end of the operational amplifier chip is connected with the output end of the DAC chip through a second resistor; the reverse input end of the operational amplifier chip is connected with the output end of the voltage follower through a third resistor; and the output end and the reverse input end of the operational amplifier chip are connected through a fourth resistor; The third resistor and the fourth resistor have the same resistance.

4. The drive circuit of the interferential electric therapeutic apparatus according to claim 1, wherein A second RC filter circuit is further arranged between the output end of the power amplifier chip and the power amplifier chip.

5. The drive circuit of the interferential electrotherapeutic apparatus according to claim 1, wherein The conversion output circuit further comprises an isolation transformer; The output end of the power amplifier chip is connected with the primary coil of the isolation transformer; and the treatment electrode is connected with the secondary coil of the isolation transformer.

6. The drive circuit of the interferential electrotherapeutic apparatus according to claim 5, wherein the first and second drive circuits are connected to the first and second electrodes, respectively. A filter circuit is further arranged between the output end of the power amplifier chip and the primary coil of the isolation transformer.

7. The drive circuit of the interferential electrotherapeutic apparatus according to claim 6, wherein the drive circuit is configured to generate the first and second drive signals with a frequency of 10 to 100 kHz. The filter circuit comprises an LC filter circuit and an RC filter circuit connected in series between the output end of the power amplifier chip and the primary coil of the isolation transformer.

8. The drive circuit of the interferential electric therapeutic apparatus according to claim 1, wherein, The number of the conversion output circuits is an integer multiple of three; Each three of the conversion output circuits form a group of conversion output circuits; The first output end of the FPGA chip outputs three different serial digital signals output by the same group of conversion output circuits, so that at least one of the frequency, amplitude and phase of the analog electric signals output by the same group of conversion output circuits is different.

9. An interferential electrotherapy device, characterized in that, The drive circuit of the interference electric therapeutic instrument comprises at least two pairs of treatment electrodes and the drive circuit of the interference electric therapeutic instrument according to any one of claims 1 to 8. The output ends of each pair of the therapeutic electrodes and one of the driving circuit and the conversion output circuit of the interference electric therapeutic instrument are electrically connected.

10. The interferential electrotherapeutic device according to claim 9, characterized in that, The number of the pairs of therapeutic electrodes is 3N, where N is a positive integer. Each three pairs of the therapeutic electrodes form one electrode group, and the three pairs of therapeutic electrodes in the same group are used for synchronous output of electric signals.

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