Nanostructure devices

Abstract

A nanostructure device includes a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructures are stacked in the first region. The second nanostructures are stacked in the second region. The first gate structure surrounds the first nanostructure stack. The first gate structure includes a first gate dielectric and a first gate metal. The first gate dielectric has at least two first corner regions. A first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure includes a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric has at least two second corner regions. A transition metal nitride layer is on the second gate dielectric. A second gate metal is on the transition metal nitride layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a nanostructure device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. ICs have progressed from a technology using individual discrete components to a technology that uses a variety of very small components. Improvements in IC materials and design have resulted in increasing functionality at a lower cost per bit of information transferred. These improvements in IC design have resulted in ever smaller components that are packed with increasing density. SUMMARY

[0003] A nanostructure device includes a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructure stack is in a first region. The second nanostructure stack is in a second region. The first gate structure surrounds the first nanostructure stack. The first gate structure includes a first interface layer, a first gate dielectric, and a first gate metal. The first gate dielectric is on the first interface layer, has at least two first corner regions, and is in first upper corners of a first topmost nanostructure of the first nanostructure stack. The first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure includes a second interface layer, a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric is on the second interface layer, has at least two second corner regions, and is in second upper corners of a second topmost nanostructure of the second nanostructure stack. The transition metal nitride layer is on the second gate dielectric. The second gate metal is on the transition metal nitride layer.

[0004] A nanostructure device includes a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructure stack is located in a first region. The second nanostructure stack is located in a second region. The first gate structure surrounds the first nanostructure stack. The first gate structure includes a first gate dielectric and a first gate metal. The first gate dielectric has at least two first corner regions located at a first upper corner of a first top nanostructure of the first nanostructure stack. The first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure includes a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric has at least two second corner regions located at a second upper corner of a second top nanostructure of the second nanostructure stack. The transition metal nitride layer is on the second gate dielectric. The second gate metal is on the transition metal nitride layer. The first thickness of the first gate dielectric in the first corner region is less than the second thickness of the first gate dielectric outside the first corner region.

[0005] A nanostructure device includes a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructure stack is located in a first region. The second nanostructure stack is located in a second region. The first gate structure surrounds the first nanostructure stack. The first gate structure includes a first gate dielectric and a first gate metal. The first gate dielectric has at least two first corner regions located at the first upper corner of the first topmost nanostructure of the first nanostructure stack. The first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure includes a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric has at least two second corner regions located at the second upper corner of the second topmost nanostructure of the second nanostructure stack. The transition metal nitride layer is on the second gate dielectric. The second gate metal is on the transition metal nitride layer. The first thickness of the first gate dielectric in the first corner region is less than the second thickness of the second gate dielectric in the second corner region. Attached Figure Description

[0006] The various features disclosed herein can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of discussion.

[0007] FIGS. 1A-1B This is a cross-sectional side view schematic diagram of a portion of an IC device according to some embodiments of the present disclosure;

[0008] FIG. 2A ,FIG. 2B , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 4C , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 9C , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11 , FIG. 12A , FIG. 12B , FIG. 12C , FIG. 12D , FIG. 12E , FIG. 12F , FIG. 12G , FIG. 12H , FIG. 12I , FIG. 12J , FIG. 12K , FIG. 12L , FIG. 12M , FIG. 12N , FIG. 12O , FIG. 12P , FIG. 12Q and FIG. 13 These are views of various embodiments of various manufacturing stages of the various sample IC devices disclosed herein;

[0009] FIG. 14 This is a flowchart of a method for forming an IC device according to various embodiments;

[0010] FIG. 15 This is a flowchart of a method for forming an IC device according to various embodiments.

[0011] [Symbol Explanation]

[0012] 10: Device

[0013] 20, 20A, 20B, 20C: Nanostructured Devices

[0014] 21, 21A, 21B, 21C: First semiconductor layer

[0015] 22: Channels / Nanostructures / Nanosheets

[0016] 22A, 22B, 22C: Semiconductor Channels / Channels

[0017] 23: Second semiconductor layer

[0018] 24: nanostructure

[0019] 25: stack / lattice

[0020] 32: fin

[0021] 36: isolation structure / isolation region

[0022] 40: dummy gate structure

[0023] 41: gate spacer / spacing layer

[0024] 41A: first spacing layer

[0025] 41B: second spacing layer

[0026] 41F: fin spacer

[0027] 43: gate dielectric layer

[0028] 45: dummy gate layer

[0029] 47: masking layer

[0030] 47A: first masking layer

[0031] 47B: second masking layer

[0032] 59: source / drain opening

[0033] 74: internal spacer

[0034] 74L: internal spacing layer

[0035] 82, 82N, 82P: source / drain feature / source / drain region

[0036] 110: substrate

[0037] 110A: first semiconductor layer

[0038] 118: silicide layer

[0039] 120: source / drain contact

[0040] 130: interlayer dielectric / ILD

[0041] 131: etch stop layer / ESL

[0042] 200: gate structure / replacement gate / active gate

[0043] 210: interface layer / IL

[0044] 220: first gate dielectric layer

[0045] 240: second interface layer / second IL

[0046] 290: metal core layer

[0047] 400: patterned mask / BARC layer

[0048] 410: second patterned mask layer / BARC

[0049] 510: seam

[0050] 600: gate dielectric layer / dielectric layer

[0051] 600C: corner region / corner portion

[0052] 600X: corner region

[0053] 600X’: void

[0054] 610: first region

[0055] 620: second region

[0056] 700: second work function layer / work function barrier / work function layer

[0057] 710: capping layer

[0058] 710’: thin capping layer

[0059] 710”: dummy plug

[0060] 720: transition metal nitride layer / layer

[0061] 720’: patterned layer

[0062] 800: bottom insulator

[0063] 810: middle region

[0064] 820: dielectric layer

[0065] 830R: right end region

[0066] 830L: left end region

[0067] 900: work function adjustment layer / work function metal layer / work function layer 1000: method

[0068] 1100, 1200, 1300, 1400, 1500, 1600, 1700: operations

[0069] 2000: method

[0070] 2100, 2200, 2300, 2400: operations

[0071] CD1: distance

[0072] D1 : first gap

[0073] D2: second gap

[0074] D3: third gap

[0075] D4: fourth gap

[0076] L1 : first diagonal line

[0077] L2: second diagonal line

[0078] L3: horizontal line

[0079] X: direction / axis

[0080] Y: direction / axis

[0081] Z: direction / axis

[0082] Θ1 : first angle

[0083] Θ2: second angle DETAILED DESCRIPTION

[0084] The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Some of these embodiments or examples are described in terms of components or in examples that can illustrate the concepts of the disclosure. This or that configuration, or example, is described in the following description and / or shown in the figures. It will of course be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can need to be made in order to achieve the design specific to a given implementation. These implementation-specific decisions can include specific

[0085] In addition, for the purpose of convenience and brevity, the disclosure can be described in terms of spatially relative terms such as "below," "under," "lower," "above," "upper," and the like, which can describe one element or feature's relationship to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0086] Terms, such as “approximately,” “substantially,” and the like, that refer to relative degrees of similarity or difference in the context of the description are to be interpreted as would be understood by one of ordinary skill in the art in light of the state of the art.

[0087] The terms “first,” “second,” “third,” etc. can be used herein to describe a sequential order, or a consecutive order of events or elements, but can be interchanged or varied in some contexts. For example, a second layer can be formed on (e.g., sequentially after) a first layer. But in some cases, the first layer can be referred to as a “second layer,” a “third layer,” a “fourth layer,” etc., and the second layer can be referred to as a “first layer,” a “third layer,” a “fourth layer,” etc.

[0088] The term “surrounding” can be used herein to describe a structure that completely or partially encloses another element or structure in, for example, three dimensions. For example, a first structure can “surround” a second structure on four lateral sides (e.g., left, right, front, and back), but not on two vertical sides (e.g., top and bottom). In other examples, a first structure can partially surround a second structure, for example, by surrounding three sides (e.g., top, front, and back), while leaving other sides (e.g., left, right, and bottom) exposed.

[0089] The present disclosure relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), etc.

[0090] Dielectric layers such as Hf02, Si02, and Zr02assist in the turn-on of field effect transistors. The quality of the dielectric layer can include thickness, vacancies, foreign atom contamination, etc., which can have a beneficial or detrimental effect on the threshold voltage (Vt), channel resistance (Rch), ring performance (RO%), time-dependent-dielectric-breakdown (TDDB), maximum voltage degradation, etc. of the FET. Some of the detrimental effects can occur after the FET is operated for ten years or more. For a nanostructured device such as a nanosheet FET, the dielectric at the nanosheet corners can be subjected to dry bombardment, which can cause a stress concentration effect and a degradation of the film quality. Then, a subsequent wet chemical etch or cleaning for metal removal can damage the underlying dielectric film. For example, N-type metal patterning can cause bottom anti-reflective coating (BARC) etching through plasma bombardment on the dielectric layer, which degrades the film quality. In another example, metal etching by wet chemicals can have low selectivity to the dielectric layer due to the degradation of the film quality.

[0091] Embodiments of the present disclosure can effectively reduce or eliminate damage to the dielectric layer by including a high-selectivity wet etch process that etches the metal without removing the dielectric layer. The corners of the nanosheet can be a hotspot for damage, which is a challenge for reliability testing. In the wet etch process, a higher H202concentration can slightly increase the selectivity of the metal to the dielectric film. In another example, adding a light acid such as HC1 can improve the quality of the dielectric film by reducing damage to the dielectric film. These embodiments can provide advantages such as increased static random access memory (SRAM) yield due to reduced leakage current, improved dielectric quality, increased mobility, and increased ring oscillator performance (e.g., RO%), increased device lifetime, and reduced voltage degradation, etc.

[0092] Nanoscale transistor structures can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) can be used to pattern the structures. Generally, double patterning or multiple patterning processes combine lithography processes with self-alignment processes, which in turn enable the creation of patterns having, for example, smaller pitches than are obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the nanoscale structures.

[0093] FIG. 1A and FIG. 1B is a cross-sectional schematic view of a portion of a nanostructure device 10 according to various embodiments. FIG. 1A shows a view in the X-Z plane. FIG. 1B shows a view in the Y-Z plane orthogonal to the X-Z plane. The following detailed description FIG. 1A and FIG. 1B to provide a context for understanding technical features and benefits of various embodiments depicted in FIGS. 2A-13 Depending on the context, a source / drain region can refer to a source or a drain, either alone or collectively.

[0094] Referring to FIG. 1A , the nanostructure devices 20A, 20B can be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). For example, the nanostructure device 20A can be a PFET and the nanostructure device 20B can be a NFET. The nanostructure devices 20A, 20B are formed on and / or in a substrate 110 and generally include gate structures 200, also referred to as “nanostructures,” that straddle and / or encircle semiconductor channels 22A, 22B, 22C, the nanostructure devices 20A, 20B being located over semiconductor fins 32 that protrude from and are separated by isolation structures 36 (see FIG. 1B ). The semiconductor channels 22A, 22B, 22C can be collectively referred to as channels 22. The gate structures 200 control current flow through the channels 22A, 22B, 22C.

[0095] The nanostructure devices 20A, 20B are shown to include three channels 22A, 22B, 22C, which are laterally adjacent to source / drain features 82N, 82P, and the gate structures 200 overlie and enclose the nanostructure devices 20A, 20B. Generally, the number of channels 22 is two or more, such as three or four or more. The gate structures 200 control current flow to and from the source / drain features 82N, 82P through the channels 22A, 22B, 22C based on voltages applied at the gate structures 200 and at the source / drain features 82N, 82P.

[0096] In some embodiments, the fin structure 32 includes silicon. In some embodiments, the nanostructure device 20B includes an NFET, and its source / drain feature 82N includes phosphorous-silicon (SiP), SiAs, SiSb, SiPA, SiP:As:Sb, combinations thereof, or the like. In some embodiments, the nanostructure device 20A includes a PFET, and its source / drain feature 82P includes undoped or doped silicon-germanium (SiGe) to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or other appropriate semiconductor material. In general, the source / drain features 82N, 82P can include any combination of appropriate semiconductor material and appropriate dopant.

[0097] The channels 22A, 22B, 22C each include a semiconductor material, such as silicon or a silicon compound, such as silicon-germanium, or the like. The channels 22A, 22B, 22C are nanostructured (e.g., having dimensions in the range of a few nanometers) and can also each have an elongated shape, extending in the X-axis direction. In some embodiments, the channels 22A, 22B, 22C each have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The channels 22A, 22B, 22C can have a rectangular, round, square, circular, elliptical, hexagonal, or combination thereof cross-sectional profile.

[0098] In some embodiments, the lengths (e.g., measured in the X-axis direction) of the channels 22A, 22B, 22C can differ from one another, for example, due to tapering during the fin etching process (refer to FIG. 3A 、 FIG. 3B ). In some embodiments, the length of the channel 22C can be less than the length of the channel 22B, which can be less than the length of the channel 22A. The channels 22A, 22B, 22C can not have a uniform thickness (e.g., along the X-axis direction), for example, due to a channel trimming process to enlarge the spacing (e.g., measured in the Z-axis direction) between the channels 22A, 22B, 22C to increase the gate structure fabrication process window. For example, the middle portions of the channels 22A, 22B, 22C can be thinner than the two ends of the channels 22A, 22B, 22C. Such a shape can be collectively referred to as a“dog bone” shape.

[0099] In some embodiments, the spacing between the channels 22A, 22B, 22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 8 nanometers (nm) and about 12 nm, but can also exceed or be below the above range. In some embodiments, the thickness (e.g., measured in the Z-axis direction) of each channel 22A, 22B, 22C is in a range between about 5 nm and about 8 nm, but can also exceed or be below the range. In some embodiments, the width (e.g., measured in the Y-axis direction, orthogonal to the X-Z plane as shown) of each channel 22A, 22B, 22C is at least 8 nm, although in some embodiments, the width can be less than 8 nm.

[0100] The gate structures 200 are disposed above and between the channels 22A, 22B, 22C. In some embodiments, the gate structures 200 are disposed above and between the channels 22A, 22B, 22C, which are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structures 200 include an interfacial layer (IL) 210, one or more gate dielectric layers 600 on the interfacial layer 210, and a metal core layer 290 on the gate dielectric layers 600. Additional layers such as one or more work function adjustment layers 900 (refer to FIG. 2B) can be present on the gate dielectric layers 600 between the gate dielectric layers 600 and the metal core layer 290. FIG. 11 ) of the gate dielectric layers 600 and the metal core layer 290.

[0101] The interfacial layer 210 can be an oxide of the material of the channels 22A, 22B, 22C, formed on the exposed regions of the channels 22A, 22B, 22C and the top surface of the fin 32. The interfacial layer 210 can facilitate adhesion of the gate dielectric layers 600 to the channels 22A, 22B, 22C. In some embodiments, the interfacial layer 210 has a thickness of about 5 Angstroms (A) to about 50 A. In some embodiments, the interfacial layer 210 has a thickness of about 10 A. An interfacial layer 210 that is too thin can have voids or insufficient adhesion properties. An interfacial layer 210 that is too thick can consume gate fill windows, which are related to threshold voltage tuning and resistance. In some embodiments, the interfacial layer 210 for threshold voltage tuning can be doped with a dipole, such as lanthanum. ) of the gate dielectric layers 600 and the metal core layer 290. ) of the gate dielectric layers 600 and the metal core layer 290.

[0102] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 angstroms to about 100 angstroms.

[0103] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material such as Co, W, Ru, or combinations thereof. In some embodiments, the metal core layer 290 is or includes a Co-based, W-based, or Ru-based compound or alloy comprising one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, or combinations thereof. Between channels 22A, 22B, and 22C, one or more work function metal layers 900 circumferentially surround (in the cross-sectional view) the metal core layer 290, and an interface layer 210 circumferentially surrounds the gate dielectric layer 600.

[0104] like FIG. 1A As shown, the nanostructure devices 20A and 20B may further include source / drain contacts 120 formed above the source / drain features 82N and 82P. The source / drain contact 120 may include a core layer, which is a conductive material or comprises conductive materials, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or combinations thereof. One or more liner (or barrier layer) layers may surround the core layer. The liner (or barrier layer) may be, for example, SiN or TiN, which helps prevent or reduce material diffusion from or into the source / drain contact 120. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 50 nm.

[0105] A silicide layer 118 may be located at least between the source / drain features 82N, 82P and the source / drain contact 120 to reduce the resistance of the source / drain contact. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide layer 118 may have a thickness in the range of about 1 nm to about 10 nm. A thickness less than about 1 nm may result in insufficient reduction of contact resistance. A thickness greater than about 10 nm may result in an electrical short circuit of the nanostructure 22. In some embodiments, the silicide layer 118 is present below and in contact with the etch stop layer 131.

[0106] like FIG. 1B As shown, the nanostructure devices 20A and 20B may further include an interlayer dielectric (ILD) 130. The ILD 130 provides electrical isolation between the aforementioned nanostructure devices 20A and 20B, for example, located between adjacent pairs of source / drain contacts 120. An etch stop layer 131 may be formed prior to the formation of the ILD 130, and the etch stop layer 131 may be laterally positioned between the ILD 130 and the gate spacer 41 and vertically positioned between the ILD 130 and the source / drain features 82N and 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, or ZrAlO2. x HfAlO x HfSiOx, Al2O3, or other suitable materials. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1 nm to about 5 nm. In some embodiments, the etch stop layer 131 may contact the source / drain contact 120 in the absence of ILD 130 (e.g., ILD 130 is completely removed before forming the source / drain contact 120). Before forming the source / drain contact 120, the etch stop layer 131 may be trimmed, for example, in the X-axis direction to improve the filling quality of the source / drain contact 120.

[0107] Nanowire devices 20A, 20B include gate spacers 41 and inner spacers 74, where gate spacers 41 are disposed on sidewalls of metal core layer 290, gate dielectric layer 600, and IL 210 above channel 22A, and inner spacers 74 are disposed on sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, 22C. Inner spacers 74 can also be disposed between channels 22A, 22B, 22C. In some embodiments, inner spacers 74 are not present. FIG. 1A In the illustrated embodiment, gate spacers 41 include a first spacer layer 41 A and a second spacer layer 41B disposed on first spacer layer 41A. Both first spacer layer 41A and second spacer layer 41B can include a dielectric material, such as a low-k material such as SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, second spacer layer 41B is not present. The materials of first spacer layer 41A and second spacer layer 41B can be the same as or different from each other. In some embodiments, an upper portion of second spacer layer 41B (or first spacer layer 41A when second spacer layer 41B is not present) can be partially or completely removed to increase the aspect ratio of the openings that form source / drain regions 82N, 82P. FIG. 1A Embodiments in which an upper portion of second spacer layer 41B is not thinned are depicted.

[0108] FIG. 14 With FIG. 15 Method 1000, method 2000 are merely examples and are not intended to limit the present disclosure to anything that is specifically shown in methods 1000, 2000. Additional operations can be provided before, during, and after methods 1000, 2000, and some operations described can be replaced, eliminated, or moved to a different location and can be adapted to additional embodiments of the methods. For the sake of simplicity, the various operations are described in the order in which they occur, but the ordering of the operations can be changed so that particular embodiments include the use of out-of-order operations, including simultaneous performance of the operations by multiple components. For the sake of simplicity, the operations are not described in detail in this document, but rather reference is made to the descriptions of the embodiments of the workpieces and the methods of forming the workpieces. FIGS. 2A-13 Methods 1000, 2000 are described in terms of partial perspective and / or cross-sectional views of workpieces at different manufacturing stages of embodiments according to methods 1000, 2000. For the avoidance of doubt, in all of the figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction. It is noted that since the workpieces can be fabricated into semiconductor devices, the workpieces can be referred to as semiconductor devices as needed in context.

[0109] FIGS. 2A-13 are views of manufacturing intermediate stages of a FET (e.g., a nanowire FET) according to some embodiments.

[0110] In FIG. 2A and FIG. 2BIn some embodiments, a substrate 110 is provided. The substrate 110 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, arsenic phosphide gallium, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide indium phosphide; or combinations thereof. Other substrates can also be used, such as single-layer, multi-layer, or graded substrates.

[0111] In addition, in FIG. 2A and FIG. 2B a multilayer stack 25 (lattice 25) is formed over the substrate 110 from alternating layers of first semiconductor layers 21A, 21B, 21C (collectively, first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layers 21 can be formed from a first semiconductor material suitable for n-type nanometer FETs, such as silicon, silicon carbide, etc., and the second semiconductor layers 23 can employ a second semiconductor material suitable for p-type nanometer FETs, such as silicon germanium, etc. The first semiconductor layers 21, second semiconductor layers 23 of the multilayer stack 25 can be grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0112] In FIG. 2A and FIG. 2B three pairs of first semiconductor layers 21 and second semiconductor layers 23 are shown. In some embodiments, the multilayer stack 25 can include fewer or more pairs of first semiconductor layers 21 and second semiconductor layers 23. Although the multilayer stack 25 is shown as including a second semiconductor layer 23 as the bottommost layer, in some embodiments, the bottommost layer of the multilayer stack 25 can be a first semiconductor layer 21.

[0113] Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, which in turn patterns the first semiconductor layer 21 to form the channel region of the nanometer FET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etch selectivity enables the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, which in turn patterns the second semiconductor layer 23 to form the channel region of the nanometer FET.

[0114] In FIG. 3A and FIG. 3B corresponding to FIG. 14 operation 1100, the fins 32 are formed in the substrate 110 and the nanometer structures 22, 24 are formed in the multilayer stack 25. In some embodiments, the nanometer structures 22, 24 and fins 32 can be formed by etching trenches in the multilayer stack 25 and the substrate 110. The etching can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), etc., or combinations thereof. The etching can be an anisotropic etching process. The first nanometer structures 22A, 22B, 22C (also referred to below as "channels 22") are formed from the first semiconductor layer 21, while the second nanometer structures 24 are formed from the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanometer structures 22, 24 can be about 18 nm to about 100 nm. For simplicity of illustration, FIG. 3A and FIG. 3B shows a portion of the device 10 including two fins 32. FIG. 14 、 FIG. 15 The methods 1000, 2000 shown can be extended to any number of fins and are not limited to FIGS. 3A-13 the two fins 32 shown.

[0115] The fins 32 and nanometer structures 22, 24 can be patterned by any suitable method. For example, one or more lithography processes (including a double patterning or multiple patterning process) can be used to form the fins 32 and nanometer structures 22, 24. In general, a double patterning or multiple patterning process combines lithography and self-alignment processes to enable smaller pitches than using a single direct lithography process. As an example of a multiple patterning process, a sacrificial layer can be formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins 32.

[0116] FIG. 3A and FIG. 3B The fins 32 are shown with tapered sidewalls such that the width of each fin 32 and / or nanostructure 22, 24 continuously increases in a direction toward the substrate 110. In such embodiments, each nanostructure 22, 24 can have a different width and be shaped as a trapezoid. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the width of the fin 32 and nanostructure 22, 24 are substantially similar, and each nanostructure 22, 24 is shaped as a rectangle.

[0117] In FIG. 3A and FIG. 3B , an isolation region, feature or structure 36 (which can be a shallow trench isolation (STI) region, feature or structure) is formed adjacent to the fins 32. The isolation region 36 can be formed by depositing an insulating material over the substrate 110, fins 32 and nanostructures 22, 24 and between adjacent fins 32 and nanostructures 22, 24. The insulating material can be an oxide, such as silicon oxide, nitride, etc. or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc. or a combination thereof. In some embodiments, a liner (not shown separately) can be formed along the surfaces of the substrate 110, fins 32 and nanostructures 22, 24 first. Thereafter, a core material such as those discussed above can be formed over the liner.

[0118] The insulating material is subjected to a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. to remove excess insulating material over the nanostructures 22, 24. After the removal process is complete, the top surfaces of the nanostructures 22, 24 can be exposed and level with the insulating material.

[0119] Next, the insulating material is recessed to form the isolation region 36. After the recessing, the upper portions of the nanostructures 22, 24 and fins 32 can protrude from between adjacent isolation regions 36. The isolation region 36 can have a top surface that is flat as shown, convex, concave or a combination thereof. In some embodiments, the isolation region 36 is recessed by an acceptable etching process, such as oxide removal using dilute hydrofluoric acid (dHF) that is selective to the insulating material and leaves the fins 32 and nanostructures 22, 24 substantially unchanged.

[0120] FIGS. 2A-3BOne embodiment (e.g., final etch) of forming the fins 32 and the nanostructures 22, 24 is shown. In some embodiments, the fins 32 and / or the nanostructures 22, 24 are epitaxially grown in trenches in a dielectric layer (e.g., first etch). The epitaxial structure can include the above-described alternating semiconductor materials, such as the first semiconductor material and the second semiconductor material.

[0121] In FIG. 3A and FIG. 3B , appropriate well regions (not shown separately) can be formed in the fins 32, the nanostructures 22, 24, and / or the isolation regions 36. N-type impurity implantation can be performed in p-type regions of the substrate 110 using a mask, and p-type impurity implantation can be performed in n-type regions of the substrate 110. For example, n-type impurities can include phosphorus, arsenic, antimony, etc. For example, p-type impurities can include boron, boron fluoride, indium, etc. Annealing can be performed after implantation to repair implantation damage and activate the p-type and / or n-type impurities. In some embodiments, in situ doping during epitaxial growth of the fins 32 and the nanostructures 22, 24 can obviate separate implantation, although in situ doping and implantation doping can be used together.

[0122] In FIGS. 4A-4C , dummy gate structures 40 or sacrificial gate structures 40 are formed over the fins 32 and / or the nanostructures 22, 24, corresponding to the operations 1200 of FIG. 14 . The dummy gate layer or sacrificial gate layer 45 is formed over the fins 32 and / or the nanostructures 22, 24. The dummy gate layer 45 can be or include a material having a high etch selectivity with respect to the isolation regions 36. The dummy gate layer 45 can be a conductive, semiconductive, or non-conductive material, and can be or include amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 45 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. A mask layer 47 is formed over the dummy gate layer 45, and can include, for example, silicon nitride, silicon oxynitride, etc. In some embodiments, a gate dielectric layer 43 is formed between the dummy gate layer 45 and the fins 32 and / or the nanostructures 22, 24 prior to forming the dummy gate layer 45. In some embodiments, the mask layer 47 includes a first mask layer 47A in contact with the dummy gate layer 45 and a second mask layer 47B covering and in contact with the first mask layer 47A. The first mask layer 47A can be or include the same or different material as the second mask layer 47B.

[0123] A spacer layer 41 is formed above the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the spacer layer 41 may be or contain an insulating material, such as SiOCN, SiOC, SiCN, etc. (or refer to...) FIG. 1A , FIG. 1B The spacer layer 41 (of any material described) can have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The spacer layer 41 can be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, portions of the spacer material layer between the dummy gate structures 40 are removed using an anisotropic etching process. In some embodiments, such as FIG. 4B , FIG. 4C As shown in detail, spacer layer 41 includes a first spacer layer 41A in contact with nanostructure 22C, a gate dielectric layer 43, a dummy gate layer 45, a first masking layer 47A, and a second masking layer 47B. The second spacer layer 41B of spacer layer 41 may be in contact with the first spacer layer 41A. The first spacer layer 41A may be or include the same or different material as the second spacer layer 41B.

[0124] exist FIG. 5A and FIG. 5B In this process, an etching process is performed to etch the portions of the protruding fins 32 and / or nanostructures 22, 24 that are not covered by the dummy gate structure 40, thereby forming the source / drain opening 59. The recess process can be anisotropic, so the portion of the fins 32 directly beneath the dummy gate structure 40 and the spacer layer 41 is protected and substantially unetched. According to some embodiments, the top surface of the recessed fins 32 can be substantially coplanar with the top surface of the isolation region 36. For simplicity, FIG. 5A The illustration depicts three vertically stacked nanostructures 22, 24 after the etching process. Generally, etching processes can be used to form fewer or more vertically stacked nanostructures 22, 24 above the fin 32 than depicted. In some embodiments, after the etching process, for example, due to the removal of the upper portions of the first spacer layer 41A and the second spacer layer 41B during the etching process, and the exposure of the second masking layer 47B. FIG. 5B A fin spacer 41F is depicted, which is the portion of the first spacer layer 41A and / or the second spacer layer 41B located above the isolation region 36 adjacent to the corresponding fin 32.

[0125] FIGS. 6A-7B The formation of the internal spacer 74 is illustrated according to various embodiments.

[0126] exist FIG. 6A , FIG. 6BIn this process, a selective etching process is performed to recess the ends of the nanostructure 24 exposed by the openings of the spacer layer 41, while essentially leaving the nanostructure 22 unetched. Following the selective etching process, a groove is formed in the nanostructure 24 at the original location of the removed ends. Then, after forming the groove 64, an internal spacer layer 74L is formed to (partially or completely) fill the recess in the nanostructure 22 formed by the previous selective etching process. The internal spacer layer 74L can be a suitable dielectric material, such as silicon carbonitride (SiCN) or silicon carbonitride oxycarbonate (SiOCN), formed by a suitable deposition method such as PVD, CVD, or ALD. FIG. 7A and FIG. 7B In the process, after the internal spacer layer 74L is formed, an etching process, such as anisotropic etching, is performed to remove the portion of the internal spacer layer 74L disposed outside the recess, such as the portion on the sidewall of the nanostructure 22 and the fin 32. The remaining portion of the internal spacer layer 74L (e.g., the portion disposed within the recess in the nanostructure 24) forms the internal spacer 74.

[0127] exist FIG. 8A In this process, a first semiconductor layer 110A is formed in the source / drain opening 59. In some embodiments, the first semiconductor layer 110A is an undoped silicon layer that can be deposited or epitaxially grown on the exposed surface of the fin 32. Deposition may include one or more operations, such as ultra-high vacuum chemical vapor deposition (UHV-CVD) when using CVD, which can improve control over the deposition rate and purity of the first semiconductor layer 110A. In some embodiments, a silicon-containing precursor gas may be introduced into the processing chamber, and the reaction between the precursor gases forms a silicon material, which is then deposited into the source / drain opening 59. In some embodiments, the first semiconductor layer 110A has a horizontal upper surface, and the upper surface of the first semiconductor layer 110A is substantially coplanar with the upper surface of the fin 32.

[0128] FIG. 8A The diagram illustrates the formation of the bottom insulator 800 and the source / drain regions 82N, 82P (or may be referred to as "source / drain 82N, 82P") according to various embodiments. FIG. 8A The diagram illustrates the formation of p-type source / drain 82P and n-type source / drain 82N, which may differ in some respects. That is, a device including an n-type source / drain 82N preferably includes a bottom insulator 800, while a device including a p-type source / drain 82P preferably does not include a bottom insulator 800.

[0129] exist FIG. 8AIn the illustrated embodiment, source / drain regions 82N, 82P are formed. In the illustrated embodiment, source / drain regions 82P are epitaxially grown from epitaxial material. In some embodiments, source / drain regions 82P exert stress in respective channels 22A, 22B, 22C, thereby improving performance. Source / drain regions 82P are formed such that each dummy gate structure 40 is disposed between each adjacent pair of source / drain regions 82P. In some embodiments, spacer layer 41 separates source / drain regions 82P from dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the gate of the final formed device. Source / drain regions 82P can be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. Source / drain regions 82P can exert compressive stress in the channel region. Source / drain regions 82N, 82P can have surfaces that are raised from respective surfaces of first semiconductor layer 110A and can have facets. In some embodiments, adjacent source / drain regions 82P can be merged to form a single source / drain region 82P adjacent to two adjacent fins 32.

[0130] In the illustrated embodiment, after formation of source / drain regions 82P, optional bottom insulator 800 can be formed. Formation of bottom insulator 800 can include appropriate deposition operations, such as LPCVD, PECVD, ALD, etc. Bottom insulator 800 can be or include SiN or another suitable dielectric material. Bottom insulator 800 can have a thickness in a range from about 2 nm to about 4 nm. During formation of bottom insulator 800, dielectric layer 820 can be formed on the upper surfaces of source / drain regions 82P. Dielectric layer 820 can have the same composition (e.g., SiN) and thickness as bottom insulator 800. Bottom insulator 800 can be on first semiconductor layer 110A, e.g., in direct contact with the upper surface of first semiconductor layer 110A. Side surfaces of bottom insulator 800 can be in direct contact with side surfaces of the bottom-most of inner spacers of inner spacers 74.

[0131] After the bottom insulator 800 is formed, the source / drain regions 82N are epitaxially grown from the epitaxial material. Due to the bottom insulator 800, the source / drain regions 82N can be grown from the channels 22 rather than from the first semiconductor layer 110A. In some embodiments, the source / drain regions 82N exert stress in the respective channels 22A, 22B, 22C, thereby improving performance. The source / drain regions 82N are formed such that each dummy gate structure 40 is disposed between each adjacent pair of source / drain regions 82N. In some embodiments, the spacer layer 41 separates the source / drain regions 82N from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the gate of the final formed device. The source / drain regions 82N can be or include SiP, SiAs, SiSb, SiPA, SiP:As:Sb, etc. Due to the presence of the bottom insulator 800, the source / drain regions 82N can exert tensile stress in the channel regions. The source / drain regions 82N can have surfaces that protrude from the respective surfaces of the fins 32 and can have facets. In some embodiments, adjacent source / drain regions 82N can be merged to form a single source / drain region 82N adjacent to two adjacent fins 32.

[0132] In some embodiments, the bottom insulator 800 and the dielectric layer 820 can not be formed. In such embodiments, the source / drain regions 82N, 82P are grown from the first semiconductor layer 110A and the nanostructures 22 and are in direct contact with the first semiconductor layer 110A.

[0133] In FIG. 8B some embodiments, after the source / drain regions 82N, 82P are formed, an ILD 130 can be formed that covers the source / drain regions 82N, 82P and abuts the spacer layer 41. In some embodiments, an ESL 131 is formed prior to forming the ILD 130. The ESL 131 can be formed by depositing a conformal thin layer of a dielectric material that is different from the ILD 130, such as one or more of SiN, SiCN, SiC, SiOC, SiOCN, Hf02, Zr02, ZrAl02 x , HfAl02 x , HfSi02 x , AI2O3, or other suitable materials.

[0134] After depositing ESL131, ILD130 can be deposited using appropriate processes, such as blanket deposition processes including PVD, CVD, and ALD. The material for ILD130 can include silicon dioxide or low-k dielectric materials (e.g., materials with a dielectric constant (k value) lower than that of silicon dioxide (approximately 3.9)). Low-k dielectric materials can include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), and silicon oxycarbide (SiO2). x C y Spin-on-Glass (SOG) or combinations thereof. ILD130 can be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD or other deposition processes.

[0135] exist FIGS. 9A-10C In the process of forming the source / drain 82N, 82P, ESL131, and ILD130, an active gate structure 200 can be formed. A planarization process, such as chemical mechanical polishing (CMP), is performed on ILD130 and ESL131. During the planarization process, a portion of the first masking layer 47A, the second masking layer 47B, and the gate spacer 41 is also removed. After the planarization process, a dummy gate layer 45 is exposed. The top surfaces of ILD130 and ESL131 can be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacer 41.

[0136] Next, as FIGS. 9A-9C As illustrated, the dummy gate layer 45 is removed during the etching process, thereby forming an opening 92, corresponding to... FIG. 14 Operation 1400. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, wherein the dummy gate layer 45 is selectively etched without etching the spacer layer 41. When the dummy gate dielectric 43 is present, the dummy gate dielectric 43 may be used as an etch stop layer during the etching of the dummy gate layer 45. The dummy gate dielectric 43 may then be removed after the dummy gate layer 45 has been removed.

[0137] Nanostmctures 24 are removed to release nanostmctures 22. After nanostmctures 24 are removed, nanostmctures 22 form a plurality of nanosheets that extend horizontally (e.g., parallel to the major upper surface of substrate 110). In some embodiments, nanostmctures 24 are removed by a selective etching process that uses an etchant selective to the material of nanostmctures 24, such that nanostmctures 24 are removed without substantially etching nanostmctures 22. In some embodiments, the etching process is an isotropic etching process that uses an etching gas and an optional carrier gas, where the etching gas includes F2and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, or a combination thereof, among others.

[0138] In some embodiments, nanostmctures 24 are removed and nanostmctures 22 are patterned to form channel regions for both PFETs and NFETs. However, in some embodiments, nanostmctures 24 can be removed and nanostmctures 22 can be patterned to form channel regions for NFETs, and nanostmctures 22 can be removed and nanostmctures 24 can be patterned to form channel regions for PFETs. In some embodiments, nanostmctures 22 can be removed and nanostmctures 24 can be patterned to form channel regions for NFETs, and nanostmctures 24 can be removed and nanostmctures 22 can be patterned to form channel regions for PFETs. In some embodiments, nanostmctures 22 can be removed and nanostmctures 24 can be patterned to form channel regions for both PFETs and NFETs.

[0139] In some embodiments, nanosheets 22 are reshaped (e.g., thinned) by a further etching process to improve the fill window for the gate. Reshaping can be performed by an isotropic etching process that is selective to nanosheets 22. After reshaping, nanosheets 22 can exhibit a dog bone shape, where the middle portion of nanosheets 22 is thinner along the X direction than the peripheral portions of nanosheets 22.

[0140] Next, replacement gates 200 are formed. Replacement gates 200 can also be referred to as active gates 200 or gate structures 200. Gate structures 200 can be formed by a series of deposition operations (e.g., ALD cycles), where layers of gate structures 200 are deposited in openings, as described below with reference to FIG. 11 The formation of gate structures 200 is described in detail to provide context for understanding the embodiments described with reference to FIG. 11 The formation of gate structures 200 is described in detail to provide context for understanding the embodiments described with reference to FIGS. 12A-12Q The formation of gate structures 200 is described in detail to provide context for understanding the embodiments described with reference to

[0141] FIG. 11is a detailed view of a portion of the gate structure 200. The gate structure 200 generally includes an interface layer (IL, or "first IL" hereinafter) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 also includes at least a second interface layer 240 or a second work function layer 700.

[0142] Referring to FIG. 11 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 can include other suitable types of dielectric materials. The thickness of the first IL 210 is in a range between about 5 Angstroms and about 50 Angstroms.

[0143] Still referring to FIG. 11 The gate dielectric layer 600 is formed over the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using about 40 to 80 deposition cycles at a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4and / or H2O as a precursor. Such an ALD process can form a first gate dielectric layer 220 having a thickness in a range between about 10 Angstroms and about 100 Angstroms.

[0144] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which can refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k ~ 3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer 600 can include a non-high-k dielectric material such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one layer of high-k dielectric layers, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., that can be driven in through an anneal process to modify the threshold voltage of the nanostructure device 20A, 20B.

[0145] Further referring to FIG. 11An optional second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 can facilitate adhesion of the metal gate above the gate dielectric layer 600. In many embodiments, the second IL 240 also provides improved thermal stability for the gate structure 200, and serves to limit diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials. In one embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by ALD for about 40 to about 100 cycles at a temperature of about 400 °C to about 450 °C. In some embodiments, next, a thermal anneal is performed to form the second IL 240, where the second IL 240 can be or include TiSiNO. After the second IL 240 is formed by thermal anneal, atomic layer etching (ALE) with artificial intelligence (AI) control can be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle can include a first WCl5pulse, followed by an Ar purge, followed by a second O2pulse, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window, to further tune the plurality of threshold voltages by metal gate patterning.

[0146] In addition, in FIG. 11 In accordance with some embodiments, after the second IL 240 is formed and the high-k capping layer is removed, a work function barrier layer 700 is optionally formed on the gate structure 200. The work function barrier layer 700 can be or include a metal nitride, such as TiN, WN, MoN, TaN, etc. In a particular embodiment, the work function barrier layer 700 is TiN. The work function barrier layer 700 can have a thickness ranging from about 5 A to about 20 A. The work function barrier layer 700 provides additional threshold voltage tuning flexibility. Generally, the work function barrier layer 700 increases the threshold voltage of NFET transistor devices, and decreases the threshold voltage (magnitude) of PFET transistor devices.

[0147] In some embodiments, the work function metal layer 900 can include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer, and is formed on the work function barrier layer 700. The N-type work function metal layer can be or include an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The N-type work function metal layer can be formed by one or more deposition methods, such as CVD, PVD, ALD, electroplating, and / or other suitable methods, and has a thickness between about 10 A and 20 A. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or other suitable material, and has a thickness between about 10 A and 20 A. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type work function metal layer, which can cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed from a dielectric material that is capable of preventing oxygen permeation into the N-type work function metal layer, and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer can include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD, and has a thickness between about 10 A and about 20 A.

[0148] FIG. 11 A metal core layer 290 is further shown. In some embodiments, a glue layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can facilitate and / or enhance adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed using ALD from a metal nitride, such as TiN, TaN, MoN, WN, or other suitable material. In some embodiments, the glue layer has a thickness between about 10 A and about 25 A. The metal core layer 290 can be formed on the glue layer, and can include a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the metal core layer 290 can be deposited using methods such as CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, a seam 510 is formed vertically in the metal core layer 290 between the channels 22A, 22B, 22C, where the seam 510 can be an air gap. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. The seam 510 can be formed due to merging of films deposited on the sidewalls during conformal deposition. In some embodiments, there is no seam 510 between adjacent channels 22A, 22B, 22C.

[0149] In some embodiments, one or more metal layers including the metal core layer 290 and work function layer 700, 900 in a PFET device can include Ti, Al, Zn, W, Nb, Co, and the like, and the total thickness of the metal layer combination on the gate dielectric layer 600 can be in a range from about 0.5 nm to about 20 nm. In some embodiments, one or more metal layers including the metal core layer 290 and work function layer 700, 900 in a NFET device can include Ti and / or Al and the like, and the total thickness of the metal layer combination on the gate dielectric layer 600 can be in a range from about 0.5 nm to about 20 nm.

[0150] FIGS. 12A-12Q is a cross-sectional side view of forming a portion of the gate structure 200 of the IC device 10 according to various embodiments. The dielectric layer 600, such as Hf02, Si02, and Zr02, is advantageous to improve the on-state of the field effect transistor (e.g., the nanostructure transistor 20A). The quality of the dielectric layer 600 can include thickness, vacancies, foreign atom contamination, and the like, which can degrade the threshold voltage (Vt), channel resistance (Rch), ring performance (RO%), time dependent dielectric breakdown (TDDB), maximum voltage degradation, especially after long term operation (e.g., about ten years). In devices including the nanosheet described with reference to FIGS. 1A-11 In devices including the nanosheet described with reference to

[0151] In the embodiments described with reference to FIGS. 12A-12Q , the high selectivity wet etch process etches the metal (e.g., the work function layer 700, 900) while substantially not removing the dielectric layer 600.

[0152] In FIG. 12A , FIG. 12B , after forming the IL 210 and the high-k dielectric layer 600, a capping layer 710 can be formed on and around the channel 22A, 22B, 22C and the fin 32, corresponding to operation 1400 of FIG. 14 . The capping layer 710 can surround the channel 22 on all sides of the cross-sectional profile along the YZ plane as shown in FIG. 12A , and the capping layer 710 can partially surround the fin 32. The capping layer 710 can be or include a dielectric material, such as SiN, SiCN, SiC, SiOC, SiOCN, Hf02, Zr02, ZrAlO x , HfAlO x , HfSiO xAl2O3, etc. In some embodiments, the capping layer 710 is an Al2O3 layer. The capping layer 710 can be deposited by a suitable deposition process, such as PVD, CVD, ALD, etc. The thickness of the capping layer 710 can be in the range of about 1 nm to about 5 nm, for example, about 3 nm. After deposition, a first gap D1 can exist between adjacent side surfaces of the capping layer 710. The first gap D1 can be in the range of about 1 nm to about 6 nm, for example, about 3.5 nm. In subsequent processes, a thin layer of transition metal nitride, such as TiN or TaN, is deposited onto the channel 22. Forming the capping layer 710 helps prevent the transition metal nitride layer from filling the gap between vertically adjacent channels 22 (e.g., channels 22A and 22B).

[0153] exist FIG. 12C , FIG. 12D In this process, after the capping layer 710 is formed, a thin capping layer 710' is formed by thinning the capping layer 710. Thinning the capping layer 710 to form the thin capping layer 710' can facilitate increasing the polysilicon spacing, for example from about 3.5 nm (e.g., a first gap D1) to about 6.5 nm or greater (e.g., a second gap D2). In some embodiments, the second gap D2 is in the range of about 3 nm to about 10 nm, for example, about 6 nm. The second gap D2 is greater than the first gap D1. One or more etching operations may be included to thin the capping layer 710, which may be isotropic wet etching operations. The thin capping layer 710' may have a thickness in the range of about 1 nm to about 2 nm, for example, about 1.7 nm, and the thickness of the thin capping layer 710' is about or slightly greater than half the thickness of the capping layer 710. In some embodiments, the capping layer 710 is not thinned, i.e., the thin capping layer 710' is not formed.

[0154] exist FIG. 12E , FIG. 12FIn some embodiments, after optionally thinning the top cap layer 710 to form a thinned top cap layer 710', a patterned mask 400 is formed that protects the first region 610 of the device 10 while exposing the second region 620 of the device 10. In some embodiments, the patterned mask 400 is or includes a bottom antireflective coating (BARC) layer 400. Prior to forming the BARC layer 400, the surface of the device 10 can be cleaned to remove particles or unwanted material that can interfere with BARC deposition. Next, the BARC layer 400 can be deposited on the entire surface of the device 10 to cover the stack of nanosheets 22 and the gaps therebetween. The BARC layer 400 can be deposited by spin coating or chemical vapor deposition (CVD). After deposition, the BARC layer 400 can be baked to remove solvents and improve its performance. A photoresist layer can then be applied on top of the BARC layer 400. A pattern is then transferred to the photoresist layer by a lithography process, which involves exposing the photoresist layer to light reflected from a mask having a selected pattern. After exposure, the photoresist layer is developed, and then the exposed or unexposed areas are washed away (depending on whether a positive or negative photoresist is used), so that the pattern matching the mask is exposed to the underlying BARC layer 400. The exposed BARC areas are then etched away, for example, by a plasma etching process. The etching process selectively removes the portions of the BARC layer 400 where the photoresist has been washed away, to transfer the pattern from the photoresist to the BARC layer 400. After etching, the remaining photoresist layer is stripped, leaving a patterned BARC layer 400 corresponding to the selected design.

[0155] In some embodiments, the BARC layer 400 is formed by spin coating a BARC precursor solution onto the surface of the device 10. The BARC precursor solution can include a BARC precursor material, a solvent, and optionally a photoresist additive. The BARC precursor solution can be spin coated onto the surface of the device 10 using a spin coater. The spin coater can spin the device 10 at a selected speed, for example, 1000 rpm, to spread the BARC precursor solution over the surface of the device 10. The BARC precursor solution can then be baked to remove solvents and improve its performance. The BARC layer 400 can then be exposed to light reflected from a mask having a selected pattern. After exposure, the BARC layer 400 is developed, and then the exposed or unexposed areas are washed away (depending on whether a positive or negative BARC is used), so that the pattern matching the mask is exposed to the underlying surface of the device 10. The exposed areas of the BARC layer 400 are then etched away, for example, by a plasma etching process. The etching process selectively removes the portions of the BARC layer 400 where the photoresist has been washed away, to transfer the pattern from the photoresist to the BARC layer 400. After etching, the remaining photoresist layer is stripped, leaving a patterned BARC layer 400 corresponding to the selected design. FIG. 12E 、 FIG. 12F In some embodiments, the BARC layer 400 is formed by spin coating a BARC precursor solution onto the surface of the device 10. The BARC precursor solution can include a BARC precursor material, a solvent, and optionally a photoresist additive. The BARC precursor solution can be spin coated onto the surface of the device 10 using a spin coater. The spin coater can spin the device 10 at a selected speed, for example, 1000 rpm, to spread the BARC precursor solution over the surface of the device 10. The BARC precursor solution can then be baked to remove solvents and improve its performance. The BARC layer 400 can then be exposed to light reflected from a mask having a selected pattern. After exposure, the BARC layer 400 is developed, and then the exposed or unexposed areas are washed away (depending on whether a positive or negative BARC is used), so that the pattern matching the mask is exposed to the underlying surface of the device 10. The exposed areas of the BARC layer 400 are then etched away, for example, by a plasma etching process. The etching process selectively removes the portions of the BARC layer 400 where the photoresist has been washed away, to transfer the pattern from the photoresist to the BARC layer 400. After etching, the remaining photoresist layer is stripped, leaving a patterned BARC layer 400 corresponding to the selected design.

[0156] In some embodiments, the BARC layer 400 is formed by spin coating a BARC precursor solution onto the surface of the device 10. The BARC precursor solution can include a BARC precursor material, a solvent, and optionally a photoresist additive. The BARC precursor solution can be spin coated onto the surface of the device 10 using a spin coater. The spin coater can spin the device 10 at a selected speed, for example, 1000 rpm, to spread the BARC precursor solution over the surface of the device 10. The BARC precursor solution can then be baked to remove solvents and improve its performance. The BARC layer 400 can then be exposed to light reflected from a mask having a selected pattern. After exposure, the BARC layer 400 is developed, and then the exposed or unexposed areas are washed away (depending on whether a positive or negative BARC is used), so that the pattern matching the mask is exposed to the underlying surface of the device 10. The exposed areas of the BARC layer 400 are then etched away, for example, by a plasma etching process. The etching process selectively removes the portions of the BARC layer 400 where the photoresist has been washed away, to transfer the pattern from the photoresist to the BARC layer 400. After etching, the remaining photoresist layer is stripped, leaving a patterned BARC layer 400 corresponding to the selected design. FIG. 12G 、 FIG. 12HIn some embodiments, the thin cap layer 710' or the cap layer 710 is removed in the second region 620. The thin cap layer 710' or the cap layer 710 is then thinned to remove portions on the top surface of the topmost nanosheet 22C and on the side surfaces or sidewalls of the nanosheets 22A, 22B, 22C and the fin 32. This results in dummy plugs 710" formed between adjacent nanosheets 22 (e.g., nanosheets 22A, 22B) and between the bottommost nanosheet 22A and the fin 32. In the Y-axis direction, the width of the dummy plugs 710" can be less than the width of the nanosheets 22A, 22B, 22C.

[0157] Each dummy plug 710" can extend from the gate dielectric layer 600 on one nanosheet 22 to the gate dielectric layer 600 on another nanosheet 22 or to the fin 32 adjacent to that nanosheet. The dummy plug 710" can be in direct contact with the gate dielectric layer 600, and the dummy plug 710" can have exposed side surfaces. After the portions described above are removed to form the dummy plugs 710", there is a third gap D3 between adjacent sidewalls, as shown in FIG. 12H The third gap D3 can be in a range from about 5 nm to about 15 nm, such as about 10 nm. The third gap D3 is greater than the second gap D2 and the first gap Dl, which further increases the polysilicon pitch.

[0158] In some embodiments, removing the cap layer 710 and / or the thin cap layer 710' can result in a slight removal of some of the underlying dielectric layer 600. As such, after the etching operations described with reference to FIG. 12G FIG. 12H In the first region 610, the exposed regions of the gate dielectric layer 600 have a thickness that is slightly less than the thickness of the protected regions (e.g., regions in direct contact with the dummy plugs 710") of the gate dielectric layer 600 in the first region 610, and the exposed regions of the gate dielectric layer 600 have a thickness that is slightly greater than the thickness of the gate dielectric layer 600 in the second region 620, after the etching operations described with reference to

[0159] In FIG. 12I FIG. 12J In some embodiments, after the dummy plugs 710" are formed, a transition metal nitride layer 720 (or "layer 720"), such as a TiN layer, is formed on the gate dielectric layer 600, the dummy plugs 710", and the exposed surfaces of the substrate, corresponding to FIG. 14 ​​The layer 720 can be deposited on the surface by a suitable deposition operation, such as PVD, CVD, ALD, etc. The thickness of the layer 720 can be in a range from about 1 nm to about 5 nm, such as about 3 nm. After the layer 720 is deposited, there can be a fourth gap D4, which is smaller than the third gap D3 and in a range from about 2 nm to about 6 nm, such as about 4 nm. Due to the dummy plugs 710”, the transition metal nitride layer 720 in the first region 610 can not completely surround the nanosheets 22 and fill the gaps therebetween. In the second region 620, the transition metal nitride layer 720 can completely surround the nanosheets 22 and fill the gaps therebetween. The layer 720 in the first region 610 can be removed in a later operation. Having the dummy plugs 710” instead of the layer 720 in the gaps between the nanosheets 22 makes it easier to clean the material in the gaps before forming the layers of the gate structure 200. That is, it can be easier to remove the dummy plugs 710” from between the adjacent nanosheets 22 than to remove the transition metal nitride layer 720 from between the adjacent nanosheets 22.

[0160] In FIG. 12K , FIG. 12L , after the transition metal nitride layer 720 is formed, a second patterned mask layer 410 is formed covering the second region 620 while exposing the first region 610, corresponding to operation 1600 of FIG. 14 . In this way, the layer 720 in the first region 610 is exposed. In some embodiments, the second patterned mask layer 410 can be or include a BARC layer. Next, the layer 720 in the first region 610 is removed, and the patterned layer 720’ in the second region 620 is retained, to expose a portion of the gate dielectric layer 600 that is outside the dummy plugs 710”. The layer 720 can be removed by a suitable etching operation, such as a wet etching. As discussed with reference to FIG. 12G and FIG. 12H , due to the difference in the number and order of the etching operations performed on the gate dielectric layer 600 in the first region 610 and the presence of the dummy plugs 710”, the thickness of the gate dielectric layer 600 in the first region 610 can be non-uniform. For example, the thickness of the portion of the gate dielectric layer 600 that is in direct contact with the dummy plugs 710” can be slightly more than the thickness of the other portions of the gate dielectric layer 600 that are exposed from the dummy plugs 710”.

[0161] FIG. 12M , FIG. 12N , FIG. 12O and FIG. 12P are described with reference to FIG. 12K , FIG. 12L and FIG. 15Cross-sectional view of the single stack of nanostructures 22A, 22B, 22C of the first region 610 after the removal process of the described removal layer 720 and dummy plug 710".

[0162] In FIG. 12M , the layer 720 is exposed. For example, the layer 720 in the first region 610 is exposed and the second patterned mask 410 protects the layer 720 in the second region 620. When the transition metal nitride layer 720 is deposited on the gate dielectric layer 600, some mixing between the layer 720 and the gate dielectric layer 600 can occur, which can be referred to as natural mixing.

[0163] Next, in FIG. 12N , a plasma etch or plasma bombardment is performed to form the second patterned mask layer 410, corresponding to FIG. 15 the operation 2100. That is, a BARC layer can be formed on the first region 610 and the second region 620. Then, a patterned photoresist layer can be formed on the BARC layer. Next, the exposed portions of the BARC layer, for example, the portions in the first region 610, are removed by a plasma etch process, which can include plasma bombardment, in which a suitable gas is introduced and ionized in a vacuum chamber, thereby creating a plasma. When energy, typically from radio-frequency (RF) power, is applied, ionization occurs, resulting in positively charged ions and free electrons. The ions are then accelerated by the electric field to the BARC layer, where the ions make strong collisions with the surface of the BARC layer. These collisions can physically knock atoms (physical sputtering), and chemically react to form volatile byproducts, or cause radiation damage to the material. The intensity and effectiveness of the bombardment are influenced by factors such as the RF source power, chamber pressure, and etch duration. The plasma etch process can be selective and anisotropic, effectively removing the BARC layer while reducing damage to underlying or adjacent materials, which is beneficial for maintaining precise feature sizes.

[0164] Developers have learned that while plasma bombardment can reduce damage to underlying or adjacent materials (e.g., the gate dielectric layer 600), there can still be room for improvement. That is, as shown in FIG. 12N , in at least the corner regions 600X of the gate dielectric layer 600 surrounding the uppermost channel 22C, deep mixing between the gate dielectric layer 600 and the transition metal nitride layer 720 can occur. In some cases, deep mixing can also occur in the corner regions of the gate dielectric layer 600 immediately below the uppermost channel 22C and surrounding the channel 22B.

[0165] In FIG. 12O , one or more wet etch operations are performed to remove the layer 720 and the dummy plug 710”, resulting in the shown and corresponding to FIG. 14the structure of the operations 1700. In the corner region 600X, voids 600X' can be formed by removing material of the gate dielectric layer 600 during the wet etching operations. The voids 600X' can cause threshold voltage (Vt), channel resistance (Rch), ring performance (RO%), time dependent dielectric breakdown (TDDB), maximum voltage degradation. It is known to developers that performing one or more etches using a basic etchant or a first etchant, such as an etchant including NH4OH:H202:H20 in a ratio of about 1 :5:25, can cause the formation of the voids 600X'. In some embodiments, instead of using a basic etchant, a slightly acidic or weakly acidic or a second etchant is used to remove the layer 720 such that the gate dielectric layer 600 in the corner region 600X is not removed much, in turn reducing the formation of the voids 600X' and improving one or more of the performance metrics listed above. In some embodiments, a third etchant, such as H202:H20 in a ratio of about 1 :5, can be included in one or more of the wet etching operations.

[0166] In some embodiments, a first etching operation is performed, followed by a second etching operation, followed by an optional third etching operation.

[0167] After the BARC 410 is removed and the first region 610 is exposed, a first etching operation can be performed, corresponding to FIG. 15 the operations 2200. The first etching operation can be a wet etching operation including a second etchant. In some embodiments, the second etchant includes HC1:H202:H20 in a ratio of about 1 : 10:50. In some embodiments, the second etchant includes HC1 in a concentration ranging from about 0.1 wt% to about 50 wt%. In some embodiments, the second etchant includes an organic acid in a concentration ranging from about 0.1 wt% to about 50 wt%. In some embodiments, the organic acid includes one or more of citric acid, formic acid, oxalic acid, and the like. The first etching operation can remove a substantial portion of the layer 720, such as at least about 90% of the layer 720, at least about 95% of the layer 720, at least about 99% of the layer 720, or other suitable amount of the layer 720.

[0168] A second etching operation can be performed after the first etching operation, corresponding to FIG. 15 the operations 2300, and can include an oxidizing mixture as a third etchant, such as H202:H20 in a ratio of about 1 :5. In some embodiments, the concentration of the oxidizing agent in the mixture can range from about 0.1 to about 107 ppm. The oxidizing agent can include H202, O3, and the like.

[0169] An optional third etching operation can be performed after the second etching operation, and can include a second etchant, corresponding to FIG. 15The third etching operation can be performed for a different length of time than the first etching operation. For example, the third etching operation can be performed for a shorter length of time than the first etching operation.

[0170] FIG. 12Q FIG. 8 is a cross-sectional view depicting a channel 22 with a gate dielectric layer 600. The channel 22 has a middle region 810 in which the upper and lower surfaces of the channel 22 are substantially horizontal and planar. The channel 22 has a left end region 830L and a right end region 830R that are located on either side of the middle region 810 and have curved side surfaces. In some embodiments, the length of the channel 22 is in a range from about 8 nm to about 70 nm. The channel 22 has a first diagonal L1 (or is a sheet diagonal L1) in a range from about 10 nm to about 65 nm. The combination of the channel 22 and the gate dielectric layer 600 has a second diagonal L2. The second diagonal L2 is greater than the first diagonal L1, for example, 0.2 nm < (L2 - L1) < 4 nm. The first diagonal L1 can be offset from a horizontal line L3 of the channel 22 by a first angle θ1 in a range from about -45° to about 45°. The second diagonal L2 can be offset from the first diagonal L1 by a second angle θ2 in a range from about -45° to about 45°. In some embodiments, there is a relationship between the first diagonal L1, the second diagonal L2, the first angle θ1, and the second angle θ2, for example, 0.3 nm < (L2θ2 - L1θ1) < 6.3 nm.

[0171] The gate dielectric layer 600 includes a corner region 600C (or is a corner portion 600C). In the corner region 600C, the concentration of TiN in the gate dielectric layer 600 can exceed the concentration of TiN outside the corner region 600C. That is, during the plasma bombardment of the BARC 410, there can be a depth mixing between the layer 720 and the gate dielectric layer 600 such that there is a relatively higher concentration of TiN in the corner region 600C. The corner region 600C is typically only located on the upper side of the channel 22 and not on the lower side of the channel 22. This is because the upper side of the channel 22 and the gate dielectric layer 600 are in the direct path of the plasma bombardment, and the lower side of the channel 22 and the gate dielectric layer 600 are somewhat protected due to being in the indirect path of the plasma bombardment.

[0172] In some embodiments, although a weakly acidic etchant is used in the first etching operation and optionally the third etching operation, some material in the corner region 600C can be slightly removed due to the deep mixing. As such, the thickness of the gate dielectric layer 600 in the corner region 600C can be slightly less than the thickness outside the corner region 600C. For example, the ratio of the thickness in the corner region 600C to the thickness outside the corner region 600C can be in the range of about 80% to about 99.5%, such as in the range of about 90% to about 99%. FIG. 12P The thickness in the corner region 600C can be maintained by using the weakly acidic etchant described.

[0173] The BARC 410 over the first region 610 is removed by plasma bombardment, while the BARC 410 over the second region 620 can be removed by ashing or other suitable method, so the gate dielectric layer 600 in the second region 620 can not be deep mixed with the layer 720. As such, the corner region 600C in the first region 610 can be different in some aspects from the corner region 600C in the second region 620. For example, the concentration of the transition metal nitride in the corner region 600C in the first region 610 can exceed the concentration of the transition metal nitride in the corner region 600C in the second region 620. In another example, some of the deep mixed material in the corner region 600C can be slightly removed during the removal of the layer 720 in the first region 610, so that the thickness of the gate dielectric layer 600 in the corner region 600C in the first region 610 can be less than the thickness of the gate dielectric layer 600 in the corner region 600C in the second region 620. For example, the ratio of the thickness of the corner region 600C in the first region 610 to the thickness of the corner region 600C in the second region 620 can be in the range of about 80% to about 99.5%, such as in the range of about 90% to about 99%.

[0174] In FIG. 13 After the gate structure 200 is formed, a source / drain opening can be formed in the ILD 130 (shown in FIG. 8B The silicide layer 118 and the source / drain contact 120 are formed on the source / drain regions 82N, 82P.

[0175] In some embodiments, a silicide layer 118 is formed prior to the formation of the source / drain contacts 120. For example, an N-type or P-type metal layer may be formed as a conformal thin layer over the exposed portions of the source / drain regions 82N, 82P. The metal layer may be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or other suitable materials. After the metal layer is formed, the silicide layer 118 may be formed by annealing the device 10. After annealing, the silicide layer 118 can be or includes one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, Si, and YbSi. The silicide in the silicide layer 118 can diffuse into the region below ESL131. The thickness of the silicide layer 118 can range from about 1 nm to about 10 nm. If the silicide layer 118 is less than about 1 nm, the contact resistance may be too high. If the silicide layer 118 is greater than about 10 nm, the silicide layer 118 may short-circuit with channel 22B.

[0176] After forming the silicide layer 118, source / drain contacts 120 are formed by filling the openings above the source / drain regions 82N, 82P with, for example, a liner and a filler layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material, wherein the material may be or include conductive materials such as Co, W, Ru, combinations thereof. In some embodiments, the source / drain contacts 120 may be or include Co-based, W-based, or Ru-based compounds or alloys comprising one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof. The source / drain contacts 120 are located on the silicide layer 118 and contact ESL 131. Reference is made in many figures to a vertically stacked GAAFE depicting device 10 including nanostructures 22. In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and on the source / drain regions 82N, 82P of the FinFET element.

[0177] Additional processing can be performed to complete fabrication of the nanostructure device 20. For example, gate contacts (or gate vias) can be formed to electrically couple to the gate structure 200. Interconnect structures can then be formed over the source / drain contacts 120 and the gate contacts. The interconnect structures can include multiple dielectric layers (including, for example, a second ILD) surrounding metal features including conductive traces and conductive vias that form electrical connections between devices on the substrate 110 (e.g., the nanostructure device 20) and between the IC device 10 and IC devices external to the IC device.

[0178] Embodiments can provide the following advantages. By etching the layer 720 after a plasma bombardment during removal of the BARC using a weakly acidic etchant, etching of corner regions of the gate dielectric layer 600 that are deeply mixed with the transition metal nitride layer 720 is reduced or eliminated, which improves the quality (e.g., thickness uniformity) of the gate dielectric layer 600. And threshold voltage (Vt), channel resistance (Rch), ring performance (RO%), time dependent dielectric breakdown (TDDB), maximum voltage degradation, etc. of devices including the gate dielectric layer 600 can be reduced.

[0179] According to at least one embodiment, a method of forming a nanostructure device includes the following steps. Forming a stack of an alternating plurality of first semiconductor channels and a plurality of second semiconductor layers on a substrate. Removing the plurality of second semiconductor layers to free the plurality of first semiconductor channels. Forming a gate dielectric on the plurality of first semiconductor channels. Forming a transition metal nitride layer on the gate dielectric. Removing the transition metal nitride layer to expose the gate dielectric in a first region of the substrate. Wherein removing includes performing a first etch with an acidic etchant. After performing the first etch, performing a second etch with an oxidizing etchant.

[0180] In some embodiments, performing the first etch includes performing the first etch using an acidic etchant including HCl:H202:H20 in a ratio of about 1:10:50. In some embodiments, performing the first etch includes using an acidic etchant having a concentration of HCl in a range of about 0.1 wt% to about 50 wt%. In some embodiments, performing the second etch includes using an oxidizing agent having H202 in a range of about 0.1 ppm to about 107 ppm. In some embodiments, performing the second etch includes using an oxidizing agent having O3 in a range of about 0.1 ppm to about 107 ppm. In some embodiments, the method further includes forming a bottom anti-reflective layer on the transition metal nitride layer in the first region, and prior to removing the transition metal nitride layer, removing the bottom anti-reflective layer by a plasma bombardment to expose the transition metal nitride layer in the first region.

[0181] According to at least one embodiment, a method of forming a nanostructured device is provided comprising the following steps. A stack of a plurality of first semiconductor channels and a plurality of second semiconductor layers is provided. The plurality of second semiconductor layers is removed to free the plurality of first semiconductor channels. A gate dielectric is formed on the plurality of first semiconductor channels. A plurality of dummy plugs is formed between an adjacent pair of first semiconductor channels in a first region. A transition metal nitride layer is formed on the gate dielectric in the first region and a second region. A bottom antireflective layer is formed on the transition metal nitride layer in the first region and the second region. The bottom antireflective layer is patterned with a plasma bombardment, exposing the first region. The transition metal nitride layer is removed, exposing the gate dielectric in the first region. Wherein removing the transition metal nitride layer comprises performing a first etch using a first acidic etchant. After performing the first etch, a second etch is performed using an oxidizing etchant. After performing the second etch, a third etch is performed using a second acidic etchant.

[0182] In some embodiments, the acid in the second acidic etchant used in the third etch is different than the acid in the first acidic etchant. In some embodiments, the acid in the second acidic etchant used in the third etch is the same as the acid in the first acidic etchant, and the concentration of the acid in the second acidic etchant is different than the concentration of the acid in the first acidic etchant. In some embodiments, the acid in the second acidic etchant used in the third etch is the same as the acid in the first acidic etchant, and the concentration of the acid in the second acidic etchant is lower than the concentration of the acid in the first acidic etchant. In some embodiments, the third etch is performed for a time that is shorter than the time the first etch is performed. In some embodiments, forming the dummy plugs comprises forming the dummy plugs in direct contact with the gate dielectric on a first channel of the first semiconductor channels, and in direct contact with the gate dielectric on a second channel of the first semiconductor channels. In some embodiments, the method further comprises removing the dummy plugs after removing the transition metal nitride layer.

[0183] According to at least one embodiment, a nanostructure device is provided, comprising: a first nanostructure stack in a first region; a second nanostructure stack in a second region; a first gate structure surrounding the first nanostructure stack. The first gate structure comprises: a first gate dielectric having at least two first corner regions located at first upper corners of a first topmost nanostructure of the first nanostructure stack; and a first gate metal on the first gate dielectric. The device further comprises a second gate structure surrounding the second nanostructure stack. The second gate structure comprises: a second gate dielectric having at least two second corner regions located at second upper corners of a second topmost nanostructure of the second nanostructure stack; a transition metal nitride layer on the second gate dielectric; and a second gate metal on the transition metal nitride layer. Wherein a material concentration of the transition metal nitride layer mixed with the first gate dielectric is greater than a material concentration of the transition metal nitride layer mixed with the second gate dielectric.

[0184] In some embodiments, a first thickness of the first gate dielectric in the first corner regions is less than a second thickness of the second gate dielectric in the second corner regions. In some embodiments, a ratio of the first thickness to the second thickness is in a range from about 80% to about 99.5%. In some embodiments, a ratio of the first thickness to the second thickness is in a range from about 90% to about 99%. In some embodiments, a first thickness of the first gate dielectric in the first corner regions is less than a third thickness of the first gate dielectric outside the first corner regions. In some embodiments, a ratio of the first thickness to the third thickness is in a range from about 80% to about 99.5%.

[0185] A nanostructure device comprises a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructure stack is in a first region. The second nanostructure stack is in a second region. The first gate structure surrounds the first nanostructure stack. The first gate structure comprises a first interface layer, a first gate dielectric, and a first gate metal. The first gate dielectric is on the first interface layer and has at least two first corner regions located at first upper corners of a first topmost nanostructure of the first nanostructure stack. The first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure comprises a second interface layer, a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric is on the second interface layer and has at least two second corner regions located at second upper corners of a second topmost nanostructure of the second nanostructure stack. The transition metal nitride layer is on the second gate dielectric. The second gate metal is on the transition metal nitride layer.

[0186] A nanostructure device includes a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructure stack is in a first region. The second nanostructure stack is in a second region. The first gate structure surrounds the first nanostructure stack. The first gate structure includes a first gate dielectric and a first gate metal. The first gate dielectric has at least two first corner regions at first upper corners of a first topmost nanostructure of the first nanostructure stack. The first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure includes a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric has at least two second corner regions at second upper corners of a second topmost nanostructure of the second nanostructure stack. The transition metal nitride layer is on the second gate dielectric. The second gate metal is on the transition metal nitride layer. A first thickness of the first gate dielectric in the first corner regions is less than a second thickness of the first gate dielectric outside the first corner regions.

[0187] A nanostructure device includes a first nanostructure stack, a second nanostructure stack, a first gate structure, and a second gate structure. The first nanostructure stack is in a first region. The second nanostructure stack is in a second region. The first gate structure surrounds the first nanostructure stack. The first gate structure includes a first gate dielectric and a first gate metal. The first gate dielectric has at least two first corner regions at first upper corners of a first topmost nanostructure of the first nanostructure stack. The first gate metal is on the first gate dielectric. The second gate structure surrounds the second nanostructure stack. The second gate structure includes a second gate dielectric, a transition metal nitride layer, and a second gate metal. The second gate dielectric has at least two second corner regions at second upper corners of a second topmost nanostructure of the second nanostructure stack. The transition metal nitride layer is on the second gate dielectric. The second gate metal is on the transition metal nitride layer. A first thickness of the first gate dielectric in the first corner regions is less than a second thickness of the second gate dielectric in the second corner regions.

[0188] In some embodiments, the nanostructure device further includes a source / drain region adjacent to the first gate structure and the second gate structure. In some embodiments, the nanostructure device further includes a source / drain contact over the source / drain region.

[0189] The foregoing summary of features of several embodiments has been presented with sufficient particularity by way of example to convey the spirit and scope of the disclosure to those skilled in the art. This disclosure is deemed not to be limited by the described embodiments, but rather only by the claims. As will be apparent to one of ordinary skill in the art, various changes can be made within the scope of the disclosure, and all modifications and equivalents thereof are intended to be covered by the following claims.

Claims

1. A nanostructure device, characterized by, comprising: a first nanostack in a first region; a second nanostack in a second region; a first gate structure surrounding the first nanostack, the first gate structure comprising: a first interface layer; a first gate dielectric on the first interface layer, having at least two first corner regions located at a first upper corner of a first topmost nanostack of the first nanostack; and a first gate metal on the first gate dielectric; and a second gate structure surrounding the second nanostack, the second gate structure comprising: a second interface layer; a second gate dielectric on the second interface layer, having at least two second corner regions located at a second upper corner of a second topmost nanostack of the second nanostack; a transition metal nitride layer on the second gate dielectric; and a second gate metal on the transition metal nitride layer.

2. The nanostructure device of claim 1, wherein, a first thickness of the first gate dielectric in the first corner regions is less than a second thickness of the second gate dielectric in the second corner regions.

3. The nanostructure device of claim 2, wherein, a ratio of the first thickness to the second thickness is in a range of 80% to 99.5%.

4. The nanostructure device of claim 2, wherein, a ratio of the first thickness to the second thickness is in a range of 90% to 99%.

5. A nanostructure device, characterized by, comprising: a first nanostack in a first region; a second nanostack in a second region; a first gate structure surrounding the first nanostack, the first gate structure comprising: a first gate dielectric having at least two first corner regions located at a first upper corner of a first topmost nanostack of the first nanostack; and a first gate metal on the first gate dielectric; and a second gate structure surrounding the second nanostack, the second gate structure comprising: a second gate dielectric having at least two second corner regions located at a second upper corner of a second topmost nanostack of the second nanostack; a transition metal nitride layer on the second gate dielectric; and a second gate metal on the transition metal nitride layer; wherein a first thickness of the first gate dielectric in the first corner regions is less than a second thickness of the first gate dielectric outside the first corner regions.

6. The nanostructure device of claim 5, wherein, a ratio of the first thickness to the second thickness is in a range of 80% to 99.5%.

7. The nanostructure device of claim 5, wherein, further comprising: a source / drain region adjacent to the first gate structure and the second gate structure.

8. A nanostructure device, characterized by, comprising: a first nanostack in a first region; a second nanostack in a second region; a first gate structure surrounding the first nanostack, the first gate structure comprising: a first gate dielectric having at least two first corner regions located at a first upper corner of a first topmost nanostack of the first nanostack; and a first gate metal on the first gate dielectric; and a second gate structure surrounding the second nanostructure stack, the second gate structure comprising: a second gate dielectric having at least two second corner regions, the at least two second corner regions being located at a second upper corner of a second uppermost nanostructure of the second nanostructure stack; a transition metal nitride layer on the second gate dielectric; and a second gate metal on the transition metal nitride layer; wherein a first thickness of the first gate dielectric in the first corner region is less than a second thickness of the second gate dielectric in the second corner region.

9. The nanostructure device of claim 8, wherein, further comprising: a source / drain region adjacent to the first gate structure and the second gate structure.

10. The nanostructure device of claim 9, wherein, further comprising: a source / drain contact over the source / drain region.

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