Narrow-base-region large-current bridge rectifier chip
By setting piezoelectric grooves in the rectifier chip to form a U-shaped structure and a glass passivation layer, the problem of low current output caused by the thickness of the base region is solved, achieving higher current output and lower power consumption.
Patent Information
- Application Number
- CN202423057058.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2034-12-11
AI Technical Summary
In existing technologies, the thicker base region of the rectifier silicon chip results in higher power consumption and lower output current when the current is forward-biased.
By setting piezoelectric grooves on the silicon wafer to form a U-shaped structure, protrusions are formed at the edge of the N layer, reducing the thickness of the base region. While keeping the thicknesses of the P+ and N+ layers unchanged, the thickness of the N layer is reduced. Combined with a glass passivation layer and an oxide band to protect the PN junction and prevent environmental pollution.
This achieves a reduction in base region thickness, a decrease in forward conduction power consumption, and an increase in current output without increasing the thickness of the P+ and N+ layers.
Smart Images
Figure CN223859535U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of rectifier chips, and more particularly to a narrow-base large-current bridge rectifier chip. BACKGROUND
[0002] The bridge rectifier is an electronic component composed of multiple diodes inside, and mainly functions to rectify and adjust the current direction. Rectification with the bridge rectifier is relatively good, first of all, it is very convenient, and the four tubes inside are generally selected and matched, so the performance is relatively close. Secondly, when large power rectification, the bridge rectifier can be equipped with a heat sink, so that the performance is more stable during work. The bridge rectifier product is made of four rectifier silicon chips connected in a bridge mode, and is packaged with insulating plastic. The zinc metal shell is added outside the insulating layer to enhance heat dissipation.
[0003] The structure of the rectifier silicon chip is P+-N-N+, and the P-N junction in the chip plays a key role. The junction position is the boundary between the P+ layer and the N layer. Its characteristic is unidirectional conduction, that is, when a positive voltage is applied, the P face is positive and the N face is negative, and the current flows through; when a reverse voltage is applied, the P face is negative and the N face is positive, and the current does not flow. In the rectifier silicon chip, the N layer determines the size of the reverse voltage withstand capability VBR and the forward voltage drop VF; the P+ layer is the core of the P-N junction, and the high concentration area on the surface is also easy to form Ohmic contact with the surface metal, thereby reducing VF; the main function of the N+ layer is to diffuse a high concentration area on the surface of the chip to form Ohmic contact with the surface metal, thereby reducing VF.
[0004] In related technologies, the P-N junction is inside the silicon wafer, so it is first leaked out by forming a piezoelectric groove to realize its unidirectional conduction function. Because of the trench, the silicon wafer surface forms a longitudinal and transverse interlaced trench, resulting in a relatively thin edge of the silicon wafer, which is easy to be damaged in the subsequent process operation. The subsequent process refers to the process of dividing a large-size silicon wafer into a small-size silicon wafer. Therefore, in order to facilitate subsequent processing, the base area is relatively thick, and the relatively thick base area increases the power consumption during forward conduction, resulting in a smaller current output. Practical new type content
[0005] In order to solve the problem of the relatively thick base area of the rectifier silicon chip in related technologies increasing the power consumption during forward conduction of the current and resulting in a smaller current output, the present application provides a narrow-base large-current bridge rectifier chip.
[0006] A narrow base area large current bridge rectifier chip, comprising a silicon wafer, the silicon wafer comprises a P+ layer, an N layer, and an N+ layer from top to bottom, a PN junction is formed between the P+ layer and the N layer, a piezoelectric groove is arranged around the side of the silicon wafer, the piezoelectric groove extends from the top surface of the P+ layer to the N layer and forms a U-shaped structure on the top surface of the N layer, so that the edge of the N layer forms a boss, and the width of the boss is greater than the width of the bottom of the piezoelectric groove.
[0007] Preferably, the thickness of the P+ layer (13) is 25um, the thickness of the N+ layer (11) is 25um, and the thickness of the N layer is 130um.
[0008] Preferably, the piezoelectric groove wall is provided with a glass passivation layer covering the wall surface.
[0009] Preferably, the thickness of the glass passivation layer is 10um.
[0010] Preferably, the middle part of the top end of the P+ layer is provided with a soldering surface, and the edge of the soldering surface is provided with an oxidation zone.
[0011] The beneficial technical effects of the present application are: the piezoelectric groove forms a U-shaped structure on the top surface of the N layer to form a boss at the edge of the N layer, which thickens the edge of the N layer and moves the thin area to a position close to the middle, so that when a large-size silicon wafer is cut into small-size silicon wafers, the edge of the small-size silicon wafer is thicker and less likely to jump, which is beneficial to reducing the thickness of the silicon wafer, and under the condition that the thickness of the P+ layer and the N+ layer remains unchanged, the thickness of the N layer is reduced, the N layer is the base area, the thickness of the base area is reduced, the power consumption is smaller when the current is forward conducted, and the current output is larger. BRIEF DESCRIPTION OF DRAWINGS
[0012] Figure 1 It is a sectional view of a narrow base area large current bridge rectifier chip of the present embodiment.
[0013] Figure 2 It is a top view of a narrow base area large current bridge rectifier chip of the present embodiment.
[0014] Reference signs: 1, P+ layer; 11, soldering surface; 12, oxidation zone; 2, N layer; 21, boss; 3, N+ layer; 4, PN junction; 5, piezoelectric groove; 6, glass passivation layer. DETAILED DESCRIPTION
[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0016] Reference Figure 1 and Figure 2 A narrow-base-region high-current bridge rectifier chip includes a silicon wafer. From top to bottom, the silicon wafer comprises a P+ layer, an N+ layer 32, and another N+ layer. The N+ layer 32 is the base region. The P+ layer is formed by high-temperature diffusion of P-type materials boron and aluminum on one side of the base region. The N+ layer is formed by high-temperature diffusion of N-type material phosphorus on the other side. A PN junction 4 is formed between the P+ layer and the N+ layer 32. A piezoelectric groove 5 is arranged around the periphery of the silicon wafer, extending from the top surface of the P+ layer to the N+ layer 32 and forming a U-shaped structure on the top surface of the N+ layer 32, creating a protrusion 21 at the edge of the N+ layer 32. The width is greater than the bottom width of the piezoelectric groove 5. The piezoelectric groove 5 forms a U-shaped structure on the top surface of the N+ layer 32, which forms a protrusion 21 on the edge of the N+ layer 32. This thickens the edge of the N+ layer 32 and transfers the thin area to a position closer to the center. This makes it easier to cut the large silicon wafer into smaller silicon wafers with thicker edges, which is less likely to break. This is beneficial to reduce the thickness of the silicon wafer. While keeping the thickness of the P+ layer and N+ layer unchanged, the thickness of the N+ layer 32 is reduced. The N+ layer 32 is the base region. The base region is thickened, which results in lower power consumption when the current is forward conducting and a larger current output.
[0017] Reference Figure 1 and Figure 2 Furthermore, the thickness of the P+ layer is 25um, the thickness of the N+ layer is 25um, and the thickness of the N+ layer 32 is 130um. In the prior art, the thickness of the N+ layer 32 is 160um, the thickness of the P+ layer is 25um, and the thickness of the N+ layer is 25um. In this embodiment, the thickness of the N+ layer 32 is reduced to 30um to achieve a better reduction in thickness to increase the output current while making the silicon wafer less prone to breakage.
[0018] Reference Figure 1 and Figure 2 Furthermore, the piezoelectric cell 5 has a glass passivation layer 6 covering its wall surface. The thickness of the glass passivation layer 6 is 10µm. During chip use, moisture, contaminants, or dust can cause performance degradation in the PN junction area, or even short circuits or failures. Glass has good sealing properties and can effectively isolate external moisture and dust, thereby protecting the PN junction from environmental pollution.
[0019] Reference Figure 1 and Figure 2 Furthermore, a soldering surface 11 is provided in the middle of the top of the P+ layer, and an oxide band 12 is provided at the edge of the soldering surface 11. The P+ layer is soldered to the external pins through the soldering surface 11 to facilitate the conduction with the overall circuit. The oxide band 12 can effectively avoid reverse breakdown caused by excessive electric field.
[0020] While embodiments of the application have been shown and described, it is to be understood that the embodiments described are merely exemplary and that changes can be made in detail without departing from the principles and spirit of the application. The scope of the application is therefore defined by the appended claims and their equivalents.
Claims
1. A narrow base area high current bridge rectifier chip, characterized by: The application relates to a silicon wafer, which comprises a P+ layer, an N layer and an N+ layer from top to bottom, a PN junction is formed between the P+ layer and the N layer, a piezoelectric groove is arranged around the side of the silicon wafer, the piezoelectric groove extends from the top surface of the P+ layer to the N layer and forms a U-shaped structure on the top surface of the N layer, so that the edges of the N layer form a convex platform, and the width of the convex platform is greater than the width of the bottom of the piezoelectric groove. The thickness of the P+ layer (13) is 25 um, the thickness of the N+ layer (11) is 25 um, and the thickness of the N layer is 130 um. The piezoelectric groove wall is provided with a glass passivation layer covering the wall surface. The thickness of the glass passivation layer is 10 um. The middle part of the top end of the P+ layer is provided with a welding surface, and the edges of the welding surface are provided with oxidation belts.