Semiconductor structure

Abstract

A semiconductor structure includes a first transistor including a first channel layer and a first gate structure; the semiconductor structure also includes a second transistor including a second channel layer and a second gate structure. The semiconductor structure further includes a bonding structure vertically between the first transistor and the second transistor, the bonding structure including a first dielectric bonding layer attached to the first gate structure; and a first conductive bonding structure formed through the first dielectric bonding layer; the bonding structure further includes a second dielectric bonding layer attached to the first dielectric bonding layer and the second gate structure; and a second conductive bonding structure formed through the second dielectric bonding layer and bonded to the first conductive bonding structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to semiconductor technology, in particular to a semiconductor structure. BACKGROUND

[0002] The electronics industry continues to demand smaller and faster electronic devices that support more and more complex and sophisticated functions. As a result, the manufacture of low-cost, high-performance, and low-power integrated circuits (ICs) is a continuing trend in the semiconductor industry. To date, these goals have been largely achieved by scaling down the size of semiconductor integrated circuits (e.g., the minimum feature size) and thereby improving production efficiency and reducing associated costs. However, scaling down the feature size also increases the complexity of the semiconductor manufacturing process. Thus, continued progress in semiconductor integrated circuits and devices requires similar progress in semiconductor manufacturing processes and techniques.

[0003] Recently, complementary FETs (CFETs) have been introduced. In a complementary FET structure, an n-type metal oxide semiconductor device can be stacked on top of a p-type metal oxide semiconductor device, such that the effective channel width of the final device can be further maximized. However, the manufacture of integrated complementary FET devices can be challenging. SUMMARY

[0004] The present utility model aims to provide a semiconductor structure to solve at least one of the above problems.

[0005] In some embodiments, a semiconductor structure is provided, the semiconductor structure comprising a first transistor, wherein the first transistor comprises a first channel layer; and a first gate structure surrounding the first channel layer; a second transistor, wherein the second transistor comprises a second channel layer; and a second gate structure surrounding the second channel layer; a junction structure vertically located between the first transistor and the second transistor, wherein the junction structure comprises a first dielectric junction layer attached to the first gate structure; a first conductive junction structure formed through the first dielectric junction layer; a second dielectric junction layer attached to the first dielectric junction layer and the second gate structure; and a second conductive junction structure formed through the second dielectric junction layer and joined to the first conductive junction structure.

[0006] According to one embodiment of the present utility model, further comprising: a plurality of first source / drain structures attached to two sides of the first channel layer; and a plurality of second source / drain structures attached to two sides of the second channel layer, wherein the first dielectric junction layer extends laterally from a top surface of the first gate structure to vertically overlap the plurality of first source / drain structures.

[0007] According to one of the embodiments of the present application, a first backside via is connected to a first one of the plurality of first source / drain structures, wherein the first backside via and the first conductive bonding structure are located on two sides of the first transistor.

[0008] According to one of the embodiments of the present application, the first conductive bonding structure is electrically connected to a second one of the plurality of first source / drain structures.

[0009] According to one of the embodiments of the present application, the first conductive bonding structure contacts the first gate structure.

[0010] According to one of the embodiments of the present application, a first interconnect structure is attached to the first backside via, a second backside via is connected to the plurality of second source / drain structures, and a second interconnect structure is attached to the second backside via, wherein the first interconnect structure and the second interconnect structure are located on two sides of the first transistor and the second transistor.

[0011] In some embodiments, a semiconductor structure is provided, the semiconductor structure including a p-type transistor, wherein the p-type transistor includes a first channel layer, first and second source / drain structures attached to two sides of the first channel layer in a first direction, and a first gate structure surrounding the first channel layer and extending in a second direction, a first conductive bonding structure bonded to the p-type transistor, a second conductive bonding structure bonded to the first conductive bonding structure in a third direction, and an n-type transistor bonded to the second conductive bonding structure, wherein the n-type transistor includes a second channel layer, third and fourth source / drain structures attached to two sides of the second channel layer, and a second gate structure surrounding the second channel layer.

[0012] According to one of the embodiments of the present application, a first dielectric bonding layer is bonded to the p-type transistor in the third direction, and a second dielectric bonding layer is bonded to the first dielectric bonding layer and the n-type transistor, wherein the first conductive bonding structure is formed through the first dielectric bonding layer, and the second conductive bonding structure is formed through the second dielectric bonding layer.

[0013] According to one of the embodiments of the present application, a closest distance between the first gate structure and the second gate structure is substantially equal to a sum of a thickness of the first dielectric bonding layer and a thickness of the second dielectric bonding layer in the third direction.

[0014] According to one of the embodiments of the present application, the first conductive bonding structure is spaced apart from the second source / drain structure in the first direction or the second direction, but is electrically connected to the second source / drain structure. BRIEF DESCRIPTION OF DRAWINGS

[0015] Embodiments of the present application can be more fully understood from the following detailed description when read together with the accompanying drawings, in which:

[0016] FIG. 1A A schematic perspective view of a transistor with a junction structure formed thereover, in accordance with some embodiments, is shown.

[0017] FIG. 1B A schematic perspective view of a complementary field effect transistor structure, in accordance with some embodiments, is shown. The complementary field effect transistor structure includes a top transistor and a bottom transistor.

[0018] FIG. 1C A cross-sectional schematic view of a package structure, in accordance with some embodiments, is shown. The package structure includes a complementary field effect transistor structure.

[0019] FIG. 2A A schematic perspective view of a transistor with a junction structure formed thereover, in accordance with some embodiments, is shown.

[0020] FIG. 2B A schematic perspective view of a complementary field effect transistor structure, in accordance with some embodiments, is shown. The complementary field effect transistor structure includes a top transistor and a bottom transistor.

[0021] FIG. 2C A cross-sectional schematic view of a package structure, in accordance with some embodiments, is shown. The package structure includes a complementary field effect transistor structure.

[0022] FIG. 3A A schematic perspective view of a transistor with a junction structure formed thereover, in accordance with some embodiments, is shown.

[0023] FIG. 3B A schematic perspective view of a complementary field effect transistor structure, in accordance with some embodiments, is shown. The complementary field effect transistor structure includes a top transistor and a bottom transistor.

[0024] FIG. 3C A cross-sectional schematic view of a package structure, in accordance with some embodiments, is shown. The package structure includes a complementary field effect transistor structure.

[0025] FIG. 4A A schematic perspective view of a transistor with a junction structure formed thereover, in accordance with some embodiments, is shown.

[0026] FIG. 4B A schematic perspective view of a complementary field effect transistor structure, in accordance with some embodiments, is shown. The complementary field effect transistor structure includes a top transistor and a bottom transistor.

[0027] FIG. 4C FIG. 1 shows a cross-sectional schematic view of a packaged structure, in accordance with some embodiments, the packaged structure including a complementary field effect transistor structure.

[0028] FIG. 5A FIG. 2 shows a perspective schematic view of a complementary field effect transistor structure, in accordance with some embodiments, the complementary field effect transistor structure including a top transistor and a bottom transistor.

[0029] FIG. 5B FIG. 3 shows a cross-sectional schematic view of a packaged structure, in accordance with some embodiments.

[0030] FIG. 6A FIG. 4 shows a perspective schematic view of a complementary field effect transistor structure, in accordance with some embodiments, the complementary field effect transistor structure including a top transistor and a bottom transistor.

[0031] FIG. 6B FIG. 5 shows a cross-sectional schematic view of a packaged structure, in accordance with some embodiments.

[0032] FIG. 7A FIG. 6 shows a perspective schematic view of a complementary field effect transistor structure, in accordance with some embodiments, the complementary field effect transistor structure including a top transistor and a bottom transistor.

[0033] FIG. 7B FIG. 7 shows a cross-sectional schematic view of a packaged structure, in accordance with some embodiments.

[0034] FIG. 8A FIG. 8 shows a perspective schematic view of a complementary field effect transistor structure, in accordance with some embodiments, the complementary field effect transistor structure including a top transistor and a bottom transistor.

[0035] FIG. 8B FIG. 9 shows a cross-sectional schematic view of a packaged structure, in accordance with some embodiments.

[0036] FIG. 9 FIG. 10 shows a perspective schematic view of an intermediate stage of manufacturing a complementary field effect transistor structure, in accordance with some embodiments.

[0037] FIG. 10A-1 、 FIG. 10B-1 、 FIG. 10C-1 、 FIG. 10D-1 、 FIG. 10E-1 、 FIG. 10F-1 、 FIG. 10G-1 、 FIG. 10H-1 、 FIG. 10A-2 、 FIG. 10B-2 、 FIG. 10C-2 、 FIG. 10D-2 、 FIG. 10E-2 、 FIG. 10F-2 、 FIG. 10G-2 、 FIG. 10H-2 、 FIG. 10A-3 、 FIG. 10B-3 、 FIG. 10C-3 、FIG. 10D-3 , FIG. 10E-3 , FIG. 10F-3 , FIG. 10G-3 , FIG. 10H-3 , FIG. 10A-4 , FIG. 10B-4 , FIG. 10C-4 , FIG. 10D-4 , FIG. 10E-4 , FIG. 10F-4 , FIG. 10G-4 , FIG. 10H-4 The display shows, according to some embodiments, respectively along FIG. 9 line Y SD1 -Y SD1’ (i.e., in the Y direction), Y MG -Y MG’ (i.e., in the Y direction), Y SD2 -Y SD2’ Cross-sectional schematic diagrams showing intermediate stages in the fabrication of a complementary field-effect transistor structure (i.e., in the Y direction) and X-X' (i.e., in the X direction).

[0038] FIG. 11A , FIG. 11B , FIG. 11C , FIG. 11D , FIG. 11E , FIG. 11F , FIG. 11G , FIG. 11H The diagram shows a cross-sectional view of an intermediate stage in the manufacturing of the packaging structure, according to some embodiments.

[0039] FIG. 12 The diagram shows a cross-sectional view of an intermediate stage in the manufacture of the packaging structure 300b, according to some embodiments.

[0040] The attached figures are labeled as follows:

[0041] 100a, 100b, 100c, 100d: Transistors

[0042] 100Ba, 100Bb, 100Bc, 100Bd, 100Be, 100Bf, 100Bg, 100Bh: Bottom transistors

[0043] 100Ta, 100Tb, 100Tc, 100Td, 100Te, 100Tf, 100Tg, 100Th: Top transistor

[0044] 102B, 102T: Substrate

[0045] 104: Fin Structure

[0046] 104B: Base fin structure

[0047] 106: First semiconductor material layer

[0048] 108: second semiconductor material layer

[0049] 108’: channel layer

[0050] 110: mask structure

[0051] 116: isolation structure

[0052] 130: dummy gate structure

[0053] 132: dummy gate dielectric layer

[0054] 134: dummy gate electrode layer

[0055] 136: hard mask layer

[0056] 140: gate spacer

[0057] 142: fin spacer

[0058] 144: source / drain recess

[0059] 148: inner spacer

[0060] 150-1, 150-2: source / drain structure

[0061] 160: contact etch stop layer

[0062] 162: interlayer dielectric layer

[0063] 168: gate structure

[0064] 170: interface layer

[0065] 172: gate dielectric layer

[0066] 174: gate stack

[0067] 180-1, 180-2, 180-3: opening

[0068] 202B, 202T: dielectric bonding layer

[0069] 204a,204-1a,204-2a,204-3a,204b,204-1b,204-2b,204-3b,204c,204- 1c,204-2c,204-3c,204d,204-1d,204-2d,204-3d,204B-1a,204B-2a,204 B-3a,204B-1b,204B-2b,204B-3b,204B-1c,204B-2c,204B-3c,204B-1d,2 04B-2d,204B-3d,204B-1e,204B-2e,204B-3e,204B-1f,204B-2f,204B-3f 204B-1g, 204B-2g, 204B-3g, 204B-1h, 204B-2h, 204B-3h, 204T-1a, 204T-2a, 204T-3a, 204T-1b, 204T-2b, 204T-3b, 204T-1c, 204T-2c, 204T-3c, 204T-1d, 204T-2d, 204T-3d, 204T-1e, 204T-2e, 204T-3e, 204T-1f, 204T-2f, 204T-3f, 204T-1g, 204T-2g, 204T-3g, 204T-1h, 204T-2h, 204T-3h: Conductive bonding structure

[0070] 206: Through hole

[0071] 208: Joint pad

[0072] 209B, 209T, 218B, 218T: Dielectric layer

[0073] 210, 210B, 210T: Backside through-hole

[0074] 212B, 212T: Interconnection Structure

[0075] 220, 220B, 220T: Conductive structure

[0076] 230: Supporting base

[0077] 232, 234: Adhesive layer

[0078] 300a, 300b, 300c, 300d, 300e, 300f, 300g, 300h: Package structure

[0079] 1000a, 1000b, 1000c, 1000d, 1000e, 1000f, 1000g, 1000h: Complementary Field-Effect Transistor Structures

[0080] BN, BNB, BNT: bonding structure DETAILED DESCRIPTION

[0081] It is to be understood that the following description provides many different embodiments, or examples, to implement various aspects of the subject matter provided. Some of these embodiments can be made in the course of design, manufacturing, and / or use of a product. These embodiments are not intended to be limiting, but instead, are to serve as examples of how the subject matter can be implemented. For example, the dimensions of the elements can be different in other embodiments than those described in the present disclosure, and the dimensions can depend on the processing conditions and / or desired properties of the elements. In addition, the following description includes examples in which a first component is formed over or on a second component. These examples include embodiments in which the first and second components are formed in direct contact, and also include embodiments in which additional components can be formed between the first and second components, such that the first and second components can not be in direct contact. Furthermore, different examples in the description can use repeated references to a number of elements and / or terms. These repeated references are for the purpose of simplifying the description and are not intended to limit the scope of the various embodiments and / or the described configurations.

[0082] Some variations of some embodiments are described herein. In the various figures and displays of embodiments described herein, like reference numerals are used to refer to like elements. It will be understood that additional operations can be provided before, during, and / or after these various figures and displays, and some of the operations described can be replaced or eliminated, for a method for other embodiments.

[0083] Also for ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for the purpose of illustrating the orientation of one element or component with respect to another element or component. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0084] Nanometer structure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridged channel transistors, nanoribbon field effect transistors, and gate all around (GAA) transistors) described below can be patterned by any suitable method. For example, these structures can be patterned by using one or more photolithography processes, including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography and self-alignment processes to create a pattern with smaller pitch, for example, a pattern with a smaller pitch than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned by using a photolithography process. Spacers are formed next to the patterned sacrificial layer by using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacers can then be used to pattern the nanometer structures.

[0085] Embodiments of the present disclosure can relate to packaging structures, such as three-dimensional (3D) packages, three-dimensional integrated circuit devices, and 2.5D packages. Embodiments of the present disclosure form a packaging structure that includes a substrate that carries one or more dies or packages and a protective element (e.g., a protective cap) next to the dies or packages. The protective element can also function as a warpage control element and / or a heat dissipation element. Other components and processes can also be included. For example, test structures can be included to assist in verification testing of the 3D packages, three-dimensional integrated circuit devices, and / or 2.5D packages. The test structures can include test pads formed in a redistribution layer or on the substrate, for example, to allow testing using probes or probe cards and the like. Verification testing can be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0086] Complementary metal-oxide-semiconductor field effect transistors (CMOSFETs), sometimes referred to simply as complementary field effect transistors (CFETs), are used in the semiconductor industry due to their high noise immunity and low static power consumption. Complementary field effect transistors can include an n-type transistor and a p-type transistor. In some embodiments, the n-type transistor and the p-type transistor are vertically oriented to form a complementary field effect transistor structure having a top transistor stacked above a bottom transistor.

[0087] The two vertically oriented transistors can be formed by a single process, a sequential process, or in individual processes. However, if the vertically oriented transistors are formed by a single process, the manufacturing process can be relatively complex. If the vertically oriented transistors are formed by a sequential process, a thermal process performed during the manufacturing process can damage the performance of elements formed in a previous process.

[0088] Accordingly, in some embodiments of the present application, the two vertically oriented transistors are formed individually and then bonded together, which can simplify the manufacturing process. Furthermore, unlike transistors formed by a sequential process, the transistors are not damaged by a thermal process performed after their formation. Accordingly, the performance of the final device can be improved.

[0089] More specifically, the transistors can be formed over individual wafers, and the wafers having transistors of different conductivity types can be bonded together by hybrid bonding, including dielectric-to-dielectric bonding and metal-to-metal bonding. That is, a complementary field effect transistor structure can be formed by bonding a top transistor on a first wafer to a bottom transistor on a second wafer by a hybrid bonding structure.

[0090] FIG. 1A A schematic perspective view of a transistor 100a having a bonding structure formed thereover is shown in accordance with some embodiments. FIG. 1B A schematic perspective view of a complementary field effect transistor structure 1000a including a top transistor 100Ta and a bottom transistor 100Ba is shown in accordance with some embodiments. FIG. 1C A cross-sectional schematic view of a package structure 300a including the complementary field effect transistor structure 1000a is shown in accordance with some embodiments. FIGS. 1A-1C have been simplified for clarity of presentation to better understand the concepts of the present application embodiments. The transistor 100a, the complementary field effect transistor structure 1000a, and the package structure 300a can include additional components, and some components described below can be replaced, modified, or eliminated. Furthermore, to better understand the structure, X-Y-Z coordinate references are provided in the figures.

[0091] In some embodiments, the transistor 100a is a nanostructure transistor (e.g., a nanosheet transistor, a nanowire transistor, a multi-bridged channel transistor, a nanoribbon field effect transistor, and a gate-all-around (GAA) transistor). The transistor 100a can be an n-type transistor or a p-type transistor. In some embodiments, the transistor 100a includes a channel layer 108', a gate structure 168 surrounding the channel layer 108', and source / drain structures 150-1 and 150-2 attached to the channel layer 108'.

[0092] The channel layer 108' can serve as an active region of the transistor 100a and extends in the X-direction between the source / drain structures 150-1 and 150-2. It should be noted that while only one channel layer 108' is shown, the transistor 100a can include multiple channel layers 108' (e.g., 2 to 5) stacked vertically (i.e., in the Z-direction). In some embodiments, the channel layer 108' can include a nanostructure, a nanosheet structure, or a nanowire. FIG. 1A

[0093] According to some embodiments, as shown in FIG. 1A, the source / drain structures 150-1 and 150-2 are formed and attached to both sides of the channel layer 108' in the X-direction. According to some embodiments, the gate structure 168 is formed around the channel layer 108' and between the source / drain structures 150-1 and 150-2. In some embodiments, the gate structure 168 is oriented (i.e., extends) longitudinally along the Y-direction. In some embodiments, gate spacers (e.g., the gate spacers 140 shown in FIG. 1A, but not shown in FIGS. 1B and 1C for clarity) are formed on the sidewalls of the gate structure 168. In some embodiments, an inner spacer (e.g., the inner spacer 148 shown in FIG. 1A, but not shown in FIGS. 1B and 1C for clarity) is formed to separate the gate structure 168 and the source / drain structures 150-1 and 150-2. In some embodiments, an interlayer dielectric layer (e.g., the interlayer dielectric layer 162 shown in FIG. 1A, but not shown in FIGS. 1B and 1C for clarity) is formed over the source / drain structures 150-1 and 150-2. FIG. 1A FIG. 1C FIG. 1A FIG. 1B FIG. 1C FIG. 1A FIG. 1B FIG. 1C FIG. 1A FIG. 1B

[0094] After the transistor 100a is formed, a bonding structure can be formed over the transistor 100a. In some embodiments, the bonding structure includes a dielectric bonding layer (e.g., the dielectric bonding layers 202T and 202B shown in FIG. 2A, but not shown in FIGS. 2B and 2C for clarity) and a conductive bonding structure 204a. In some embodiments, the conductive bonding structure 204a includes conductive bonding structures 204-1a, 204-2a, and 204-3a that are formed through the dielectric bonding layer and electrically connected to the transistor 100a. In some embodiments, the conductive bonding structures 204-1a, 204-2a, and 204-3a each include a via 206 and a bonding pad 208. FIG. 1C FIG. 1A FIG. 1B

[0095] ​​​​​​​​​​​​​​In some embodiments, a conductive bonding structure 204-la is formed over a top surface of the source / drain structure 150-la. In some embodiments, a conductive bonding structure 204-2a is formed over a top surface of the gate structure 168. In some embodiments, as shown in FIG. 1C, a conductive bonding structure 204-3a is laterally spaced apart (e.g., in the Y direction) from the source / drain structure 150-2, but is electrically connected to the source / drain structure 150-2. FIG. 1A

[0096] In addition, a backside via 210 is formed at a backside of the source / drain structure 150-2, another backside via 210 is formed at a backside of the conductive bonding structure 204-3a, and a conductive structure 220 forming an interconnect structure is formed to laterally connect (e.g., in the Y direction) the conductive bonding structure 204-3a and the source / drain structure 150-2 through the backside vias 210.

[0097] In accordance with some embodiments, as shown in FIG. 1D, two transistors (e.g., transistors 100a) having different conductivity types are vertically stacked to form a complementary field effect transistor structure 1000a. More specifically, one transistor 100a can be considered as a top transistor 100Ta and another transistor 100a can be considered as a bottom transistor 100Ba, and the top transistor 100Ta can be flipped and attached to the bottom transistor 100Ba. The top transistor 100Ta and the bottom transistor 100Ba can be bonded by a bonding structure. Then, the top transistor 100Ta and the bottom transistor 100Ba can be considered as the complementary field effect transistor structure 1000a. FIG. 1B FIG. 1C

[0098] In accordance with some embodiments, as shown in FIG. 1D, two transistors (e.g., transistors 100a) having different conductivity types are vertically stacked to form a complementary field effect transistor structure 1000a. More specifically, one transistor 100a can be considered as a top transistor 100Ta and another transistor 100a can be considered as a bottom transistor 100Ba, and the top transistor 100Ta can be flipped and attached to the bottom transistor 100Ba. The top transistor 100Ta and the bottom transistor 100Ba can be bonded by a bonding structure. Then, the top transistor 100Ta and the bottom transistor 100Ba can be considered as the complementary field effect transistor structure 1000a. FIG. 1B ​​​As shown, the conductive bonding structure 204B-la formed over the source / drain structure 150-1 of the bottom transistor 100Ba is directly bonded to the conductive bonding structure 204T-3a formed adjacent to and electrically connected to the source / drain structure 150-2 of the top transistor 100Ta. According to some embodiments, the conductive bonding structure 204B-2a formed over the gate structure 168 of the bottom transistor 100Ba is directly bonded to the conductive bonding structure 204T-2a formed over the gate structure 168 of the top transistor 100Ta. According to some embodiments, the conductive bonding structure 204B-3a formed adjacent to and electrically connected to the source / drain structure 150-2 of the bottom transistor 100Ba is directly bonded to the conductive bonding structure 204T-la formed over the source / drain structure 150-1 of the top transistor 100Ta. In some embodiments, the conductive bonding structure 204B-la, the channel layer 108' of the bottom transistor 100Ba, the conductive bonding structure 204T-3a, one backside via 210T, and one backside via 210B are substantially aligned with one another in the X direction. In some embodiments, the conductive bonding structures 204B-2a and 204B-3a, the channel layer 108' of the top transistor 100Ta, the conductive bonding structures 204T-la and 204T-2a, one backside via 210T, and one backside via 210B are substantially aligned with one another in the X direction. In some embodiments, the channel layer 108' of the bottom transistor 100Ba is substantially parallel to the channel layer 108' of the top transistor 100Ta. In some embodiments, the channel layer 108' of the bottom transistor 100Ba is spaced apart from the channel layer 108' of the top transistor 100Ta in the Y direction of the top view. In some embodiments, the conductive structure 220T and the conductive structure 220B extend in the Y direction and are substantially parallel to one another.

[0099] FIG. 1B According to some embodiments, a cross-sectional schematic view of a package structure 300a is shown. More specifically, the package structure 300a includes FIG. 1C A cross-sectional schematic view of the complementary field effect transistor structure 1000a is shown, and according to some embodiments, the package structure 300a is shown at the channel layer 108' of the bottom transistor 100Ba of the complementary field effect transistor structure 1000a along the X direction.

[0100] As described above, according to some embodiments, the complementary field effect transistor structure 1000a is formed by bonding the top transistor 100Ta and the bottom transistor 100Ba with a bonding structure BN. In some embodiments, the bonding structure BN includes a bonding structure BNB formed over the bottom transistor 100Ba and a bonding structure BNT formed over the top transistor 100Ta. In some embodiments, the bonding structure BNB includes conductive bonding structures 204B-1a, 204B-2a, 204B-3a formed in the dielectric bonding layer 202B, while the bonding structure BNT includes conductive bonding structures 204T-1a, 204T-2a, 204T-3a formed in the dielectric bonding layer 202T. Further, according to some embodiments, a backside via 210B is formed in the dielectric layer 209B and electrically connected to the backside of the bottom transistor 100Ba, and a backside via 210T is formed in the dielectric layer 209T and electrically connected to the backside of the top transistor 100Ta. According to some embodiments, interconnect structures 212T and 212B with conductive structures 220T and 220B are formed over the backside vias 210T and 210B, respectively, and electrically connected to the backside vias 210T and 210B. In some embodiments, the carrier substrate 230 is bonded to the interconnect structure 212T with adhesive layers 232 and 234. It should be noted that, for the sake of clarity, FIG. 2A and / or FIG. 2B Some of the backside vias 210B and 210T and some of the conductive structures 220T and 220B have been omitted and are not shown. The fabrication of the package structure 300a can be described in more detail later.

[0101] FIG. 2C A perspective view of a transistor 100b with a bonding structure formed thereover, according to some embodiments. FIG. 2A A perspective view of a complementary field effect transistor structure 1000b including a top transistor 100Tb and a bottom transistor 100Bb, according to some embodiments, is shown. FIG. 1A A cross-sectional view schematic of a package structure 300b including the complementary field effect transistor structure 1000b, according to some embodiments, is shown. Figs. 2A-2C have been simplified to better understand the concepts of the embodiments of the present disclosure. The transistor 100b, the complementary field effect transistor structure 1000b, and the package structure 300b can include additional components and some of the components described below can be replaced, modified, or eliminated.

[0102] FIG. 2C The transistor 100b shown is substantially the same as FIG. 2BThe illustrated transistor 100a differs from the transistor 100b except for the location of the conductive bonding structures of the transistor. Similar to the above, bonding structures can be formed over the transistor 100b. In some embodiments, the bonding structures include a dielectric bonding layer (e.g., the illustrated dielectric bonding layers 202T and 202B) and conductive bonding structures 204b formed through the dielectric bonding layer. In some embodiments, the conductive bonding structures 204b include conductive bonding structures 204-1b, 204-2b, and 204-3b electrically connected to the transistor 100b. In some embodiments, the conductive bonding structures 204-1b, 204-2b, and 204-3b each include a via 206 and a bonding pad 208. FIG. 2A

[0103] In some embodiments, the conductive bonding structure 204-1b is formed over a top surface of the source / drain structure 150-1. In some embodiments, the conductive bonding structure 204-2b is formed over a top surface of the gate structure 168. In some embodiments, the conductive bonding structure 204-3b is laterally spaced apart (e.g., in the Y direction) from the source / drain structure 150-2, but is electrically connected to the source / drain structure 150-2. The conductive bonding structures 204-1b and 204-2b are approximately aligned with the channel layer 108’.

[0104] According to some embodiments, as FIG. 2B illustrated, two transistors (e.g., the illustrated transistors 100b) having different conductivity types are vertically stacked to form a complementary field effect transistor structure 1000b. More specifically, one transistor 100b can be considered a top transistor 100Tb and the other transistor 100b can be considered a bottom transistor 100Bb. Then, the top transistor 100Tb and the bottom transistor 100Bb can be considered a complementary field effect transistor structure 1000b. FIG. 2C

[0105] According to some embodiments, as FIG. 2B ​​As shown, the conductive bonding structure 204B-1b formed over the source / drain structure 150-1 of the bottom transistor 100Bb is directly bonded to the conductive bonding structure 204T-1b formed over the source / drain structure 150-1 of the top transistor 100Tb. According to some embodiments, the conductive bonding structure 204B-2b formed over the gate structure 168 of the bottom transistor 100Bb is directly bonded to the conductive bonding structure 204T-2b formed over the gate structure 168 of the top transistor 100Tb. According to some embodiments, the conductive bonding structure 204B-3b formed adjacent to and electrically connected to the source / drain structure 150-2 of the bottom transistor 100Bb is directly bonded to the conductive bonding structure 204T-3b formed adjacent to and electrically connected to the source / drain structure 150-2 of the top transistor 100Tb. In some embodiments, the conductive bonding structures 204B-1b and 204B-2b, the channel layer 108' of the bottom transistor 100Bb, the channel layer 108' of the top transistor 100Tb, the conductive bonding structures 204T-1b and 204T-2b, one backside via 210T and one backside via 210B are substantially aligned with each other in the X direction. In some embodiments, the channel layer 108' of the bottom transistor 100Bb substantially overlaps the channel layer 108' of the top transistor 100Tb in the Z direction. In some embodiments, the conductive structure 220T and the conductive structure 220B extend in the Y direction and are substantially aligned with each other.

[0106] FIG. 2B A cross-sectional schematic view of a package structure 300b according to some embodiments is shown. More specifically, the package structure 300b includes FIG. 1B A cross-sectional schematic view of a package structure 300b according to some embodiments is shown. More specifically, the package structure 300b includes FIG. 3A A cross-sectional schematic view of a package structure 300b according to some embodiments is shown. More specifically, the package structure 300b includes FIG. 3B A cross-sectional schematic view of a package structure 300b according to some embodiments is shown. More specifically, the package structure 300b includes

[0107] FIG. 3C A perspective view of a transistor 100c having bonding structures formed thereover according to some embodiments is shown. FIG. 3A to FIG. 3C A perspective view of a complementary field effect transistor structure 1000c according to some embodiments is shown, the complementary field effect transistor structure 1000c including a top transistor 100Tc and a bottom transistor 100Bc. FIG. 3AThis is a cross-sectional schematic diagram of package structure 300c according to some embodiments, which includes complementary field-effect transistor structure 1000c. For clarity, it has been simplified. FIG. 1A To better understand the concept of the embodiments of this utility model, the transistor 100c, the complementary field-effect transistor structure 1000c, and the package structure 300c may include additional components and may replace, modify, or eliminate some of the components described below.

[0108] FIG. 3C The transistor 100c shown is roughly the same as FIG. 3B The transistor 100a shown differs from the transistor in the location of its conductive bonding structure. Similar to the above description, the bonding structure may be formed above the transistor 100c. In some embodiments, the bonding structure includes a dielectric bonding layer (e.g., FIG. 3A The dielectric bonding layers 202T and 202B shown are illustrated, and a conductive bonding structure 204c is formed through the dielectric bonding layers. In some embodiments, the conductive bonding structure 204c includes conductive bonding structures 204-1c, 204-2c, and 204-3c electrically connected to the transistor 100c. In some embodiments, each of the conductive bonding structures 204-1c, 204-2c, and 204-3c includes a via 206 and a bonding pad 208.

[0109] In some embodiments, conductive junction structure 204-1c is formed above the top surface of source / drain structure 150-1. In some embodiments, conductive junction structure 204-2c is formed above the top surface of gate structure 168. In some embodiments, conductive junction structure 204-3c is laterally spaced from source / drain structure 150-2 (e.g., in the X direction), but electrically connected to source / drain structure 150-2. In some embodiments, conductive junction structures 204-1c, 204-2c, and 204-3c are generally aligned with channel layer 108'.

[0110] According to some embodiments, such as FIG. 3B As shown, two transistors with different conductivity types are vertically stacked (e.g., FIG. 3C The transistor 100c shown is used to form a complementary field-effect transistor structure 1000c. More specifically, one transistor 100c can be regarded as a top transistor 100Tc and the other transistor 100c can be regarded as a bottom transistor 100Bc, and the top transistor 100Tc and the bottom transistor 100Bc can then be regarded as the complementary field-effect transistor structure 1000c.

[0111] According to some embodiments, such as FIG. 3BAs shown, the conductive bonding structure 204B-1c formed over the source / drain structure 150-1 of the bottom transistor 100Bc is directly bonded to the conductive bonding structure 204T-3c formed adjacent to and electrically connected to the source / drain structure 150-2 of the top transistor 100Tc. According to some embodiments, the conductive bonding structure 204B-2c formed over the gate structure 168 of the bottom transistor 100Bc is directly bonded to the conductive bonding structure 204T-2c formed over the gate structure 168 of the top transistor 100Tc. According to some embodiments, the conductive bonding structure 204B-3c formed adjacent to and electrically connected to the source / drain structure 150-2 of the bottom transistor 100Bc is directly bonded to the conductive bonding structure 204T-1c formed over the source / drain structure 150-1 of the top transistor 100Tc. In some embodiments, the conductive bonding structures 204B-1c, 204B-2c, and 204B-3c, the channel layer 108' of the bottom transistor 100Bc, the channel layer 108' of the top transistor 100Tc, the conductive bonding structures 204T-1c, 204T-2c, and 204T-3c, the backside via 210T, and the backside via 210B are substantially aligned with one another in the X direction. In some embodiments, the channel layer 108' of the bottom transistor 100Bc substantially overlaps the channel layer 108' of the top transistor 100Tc in the Z direction. In some embodiments, the conductive structure 220T and the conductive structure 220B extend in the Y direction and are substantially aligned with one another.

[0112] FIG. 3B A cross-sectional schematic view of a package structure 300c according to some embodiments is shown. More specifically, the package structure 300c includes a complementary field effect transistor structure 1000c, a backside via 210B, a backside via 210T, a conductive structure 220B, a conductive structure 220T, a conductive bonding structure 204B-1c, a conductive bonding structure 204B-2c, a conductive bonding structure 204B-3c, a conductive bonding structure 204T-1c, a conductive bonding structure 204T-2c, and a conductive bonding structure 204T-3c. FIG. 1B A cross-sectional schematic view of a package structure 300c according to some embodiments is shown. More specifically, the package structure 300c includes a complementary field effect transistor structure 1000c, a backside via 210B, a backside via 210T, a conductive structure 220B, a conductive structure 220T, a conductive bonding structure 204B-1c, a conductive bonding structure 204B-2c, a conductive bonding structure 204B-3c, a conductive bonding structure 204T-1c, a conductive bonding structure 204T-2c, and a conductive bonding structure 204T-3c. FIG. 4A A cross-sectional schematic view of a package structure 300c according to some embodiments is shown. More specifically, the package structure 300c includes a complementary field effect transistor structure 1000c, a backside via 210B, a backside via 210T, a conductive structure 220B, a conductive structure 220T, a conductive bonding structure 204B-1c, a conductive bonding structure 204B-2c, a conductive bonding structure 204B-3c, a conductive bonding structure 204T-1c, a conductive bonding structure 204T-2c, and a conductive bonding structure 204T-3c. FIG. 4B A cross-sectional schematic view of a package structure 300c according to some embodiments is shown. More specifically, the package structure 300c includes a complementary field effect transistor structure 1000c, a backside via 210B, a backside via 210T, a conductive structure 220B, a conductive structure 220T, a conductive bonding structure 204B-1c, a conductive bonding structure 204B-2c, a conductive bonding structure 204B-3c, a conductive bonding structure 204T-1c, a conductive bonding structure 204T-2c, and a conductive bonding structure 204T-3c.

[0113] FIG. 4C A perspective view of a transistor 100d having bonding structures formed thereover according to some embodiments. FIG. 4A A perspective view of a complementary field effect transistor structure 1000d according to some embodiments is shown. The complementary field effect transistor structure 1000d includes a top transistor 100Td and a bottom transistor 100Bd. FIG. 1AThe diagram shows a cross-sectional view of a package structure 300d according to some embodiments, which includes a complementary field-effect transistor structure 1000d. For clarity, figures 4A to 4C have been simplified to better understand the concepts of this embodiment. The transistor 100d, the complementary field-effect transistor structure 1000d, and the package structure 300d may include additional components and may replace, modify, or eliminate some of the components described below.

[0114] FIG. 4C The displayed transistor 100d is roughly the same as FIG. 4B The transistor 100a shown differs from the transistor in the location of its conductive bonding structure. Similar to the above description, the bonding structure may be formed above the transistor 100d. In some embodiments, the bonding structure includes a dielectric bonding layer (e.g., FIG. 3A The dielectric bonding layers 202T and 202B shown are shown, as well as the conductive bonding structure 204d. In some embodiments, the conductive bonding structure 204d includes conductive bonding structures 204-1d, 204-2d, and 204-3d electrically connected to the transistor 100d. In some embodiments, each of the conductive bonding structures 204-1d, 204-2d, and 204-3d includes a via 206 and a bonding pad 208.

[0115] In some embodiments, conductive junction structure 204-1d is formed above the top surface of source / drain structure 150-1. In some embodiments, conductive junction structure 204-2d is formed above the top surface of gate structure 168. In some embodiments, conductive junction structure 204-3d is laterally spaced from source / drain structure 150-2 (e.g., in the X direction), but electrically connected to source / drain structure 150-2. In some embodiments, conductive junction structures 204-1d, 204-2d, and 204-3d are generally aligned with channel layer 108'.

[0116] According to some embodiments, such as FIG. 4B As shown, two transistors with different conductivity types are vertically stacked (e.g., FIG. 4A The transistor 100c shown is used to form a complementary field-effect transistor structure 1000c. More specifically, one transistor 100c can be regarded as a top transistor 100Tc and the other transistor 100c as a bottom transistor 100Bc. Then, the top transistor 100Tc and the bottom transistor 100Bc can be regarded as the complementary field-effect transistor structure 1000c.

[0117] According to some embodiments, such as FIG. 4B As shown, two transistors with different conductivity types are vertically stacked (e.g., FIG. 4CTransistor 100d is shown to form a complementary field-effect transistor structure 1000d. More specifically, one transistor 100d can be regarded as a top transistor 100Td and the other transistor 100d can be regarded as a bottom transistor 100Bd, and the top transistor 100Td and the bottom transistor 100Bd can then be regarded as the complementary field-effect transistor structure 1000d.

[0118] According to some embodiments, such as FIG. 3B As shown, the conductive junction structure 204B-1d formed above the source / drain structure 150-1 of the bottom transistor 100Bd is directly bonded to the conductive junction structure 204T-1d formed above the source / drain structure 150-1 of the top transistor 100Td. According to some embodiments, the conductive junction structure 204B-2d formed above the gate structure 168 of the bottom transistor 100Bd is directly bonded to the conductive junction structure 204T-2d formed above the gate structure 168 of the top transistor 100Td. According to some embodiments, the conductive junction structure 204B-3d formed adjacent to and electrically connected to the source / drain structure 150-2 of the bottom transistor 100Bd is directly bonded to the conductive junction structure 204T-3d formed adjacent to and electrically connected to the source / drain structure 150-2 of the top transistor 100Td. In some embodiments, conductive bonding structures 204B-1d, 204B-2d, and 204B-3d, channel layer 108' of bottom transistor 100Bd, channel layer 108' of top transistor 100Td, conductive bonding structures 204T-1d, 204T-2d, and 204T-3d, back-side via 210T, and back-side via 210B are generally aligned with each other in the X direction. In some embodiments, channel layer 108' of bottom transistor 100Bd generally overlaps channel layer 108' of top transistor 100Td in the Z direction. In some embodiments, conductive structures 220T and 220B extend in the X direction and are generally aligned with each other in the Z direction.

[0119] FIG. 3B The diagram shows a cross-sectional view of the package structure 300c according to some embodiments. More specifically, the package structure 300c includes... FIG. 1B The complementary field-effect transistor (CFPT) structure 1000c is shown, and according to some embodiments, a cross-sectional view of the package structure 300c is shown at the channel layer 108' of the bottom transistor 100Bc of the CFPT structure 1000c along the X direction. Package structure 300c is substantially the same as package structure 300a, except that... FIG. 4C The complementary field-effect transistor structure shown is 1000c, which replaces... FIG. 4B The complementary field-effect transistor structure 1000a is shown, so the detailed structure of the package structure 300c will not be described here.

[0120] FIG. 4B The diagram shows a cross-sectional view of the package structure 300d according to some embodiments. More specifically, the package structure 300d includes... FIG. 1B The complementary field-effect transistor (CFPT) structure 1000d is shown, and according to some embodiments, a cross-sectional view of the package structure 300d is shown at the channel layer 108' of the bottom transistor 100Bd of the CFPT structure 1000d along the X direction. Package structure 300d is substantially the same as package structure 300a, except that... FIG. 5A The complementary field-effect transistor structure shown is 1000d replaced FIG. 1B The complementary field-effect transistor structure 1000a is shown, so the detailed structure of the package structure 300d will not be described here.

[0121] FIG. 1B This is a schematic perspective view of a complementary field-effect transistor (CFPT) structure 1000e, based on some embodiments. The CFPT structure 1000e includes a top transistor 100Te and a bottom transistor 100Be. The CFPT structure 1000e is substantially the same as... FIG. 5B The complementary field-effect transistor structure 1000a shown is characterized by the fact that each of the conductive junction structures 204B-1e, 204B-2e, 204B-3e, 204T-1e, 204T-2e, and 204T-3e is made of a single conductive material. In other words, it does not form a structure like... FIG. 5A The conductive bonding structure shown has a through hole 206 and a bonding pad 208. Each of the conductive bonding structures 204B-1e, 204B-2e, 204B-3e, 204T-1e, 204T-2e and 204T-3e is made of a single conductive bonding material, such as Co, W or the like.

[0122] FIG. 5A The diagram shows a cross-sectional view of the package structure 300e according to some embodiments. More specifically, the package structure 300e includes... FIG. 1B The complementary field-effect transistor (CFPT) structure 1000e is shown, and according to some embodiments, a cross-sectional view of the package structure 300e is shown at the channel layer 108' of the bottom transistor 100Be of the CFPT structure 1000e along the X direction. Package structure 300e is substantially the same as package structure 300a, except that... FIG. 6A The complementary field-effect transistor structure shown is 1000e replaced FIG. 2B The complementary field-effect transistor structure 1000a is shown, so the detailed structure of the package structure 300e will not be described here.

[0123] FIG. 2BThis is a schematic perspective view of a complementary field-effect transistor (CFPT) structure 1000f, based on some embodiments. The CFPT structure 1000f includes a top transistor 100Tf and a bottom transistor 100Bf. The CFPT structure 1000f is substantially similar to... FIG. 6B The complementary field-effect transistor structure 1000b shown is except that each of the conductive junction structures 204B-1f, 204B-2f, 204B-3f, 204T-1f, 204T-2f, and 204T-3f is made of a single conductive material. That is, it does not form a structure like... FIG. 6A The conductive bonding structure shown has a through hole 206 and a bonding pad 208. Each of the conductive bonding structures 204B-1f, 204B-2f, 204B-3f, 204T-1f, 204T-2f and 204T-3f is made of a single conductive bonding material, such as Co, W or the like.

[0124] FIG. 6A The diagram shows a cross-sectional view of the package structure 300f according to some embodiments. More specifically, the package structure 300f includes... FIG. 2B The complementary field-effect transistor (CFPT) structure 1000e is shown, and according to some embodiments, a cross-sectional view of the package structure 300f is shown at the channel layer 108' of the bottom transistor 100Bf of the complementary field-effect transistor structure 1000f along the X direction. Package structure 300f is substantially the same as package structure 300b, except that... FIG. 7A The complementary field-effect transistor structure shown is 1000f replaced FIG. 3B The complementary field-effect transistor structure 1000b is shown, so the detailed structure of the package structure 300f will not be described here.

[0125] FIG. 3B This is a schematic perspective view of a complementary field-effect transistor (CFPT) structure 1000g, based on some embodiments. The CFPT structure 1000g includes a top transistor 100Tg and a bottom transistor 100Bg. The CFPT structure 1000g is substantially similar to... FIG. 7B The complementary field-effect transistor structure 1000c shown is characterized by the fact that each of the conductive junction structures 204B-1g, 204B-2g, 204B-3g, 204T-1g, 204T-2g, and 204T-3g is made of a single conductive material. In other words, it does not form a structure like... FIG. 7A The conductive bonding structure shown has a through hole 206 and a bonding pad 208. Each of the conductive bonding structures 204B-1g, 204B-2g, 204B-3g, 204T-1g, 204T-2g and 204T-3g is made of a single conductive bonding material, such as Co, W or the like.

[0126] FIG. 7AA cross-sectional schematic view of a package structure 300g according to some embodiments is shown. More specifically, the package structure 300g includes FIG. 3B A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c FIG. 8A A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c FIG. 4B A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c

[0127] FIG. 4B A perspective view of a complementary field effect transistor structure 1000h according to some embodiments is shown, the complementary field effect transistor structure 1000h includes a top transistor 100Th and a bottom transistor 100Bh. The complementary field effect transistor structure 1000h is substantially the same as the complementary field effect transistor structure 1000d FIG. 8B A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c FIG. 8A A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c

[0128] FIG. 8A A cross-sectional schematic view of a package structure 300h according to some embodiments is shown. More specifically, the package structure 300h includes FIG. 4B A cross-sectional schematic view of a complementary field effect transistor structure 1000h according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300h is shown at the channel layer 108' of the bottom transistor 100Bh of the complementary field effect transistor structure 1000h along the X direction. The package structure 300h is substantially the same as the package structure 300d, except that the complementary field effect transistor structure 1000h is substituted for the complementary field effect transistor structure 1000d FIG. 9 A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c FIG. 10A-1 to FIG. 10H-1 A cross-sectional schematic view of a complementary field effect transistor structure 1000g according to some embodiments is shown, and a cross-sectional schematic view of the package structure 300g is shown at the channel layer 108' of the bottom transistor 100Bg of the complementary field effect transistor structure 1000g along the X direction. The package structure 300g is substantially the same as the package structure 300c, except that the complementary field effect transistor structure 1000g is substituted for the complementary field effect transistor structure 1000c

[0129] The following description of the materials and methods used to manufacture the complementary field-effect transistor structure 1000b and the package structure 300b is provided as an example. The materials and methods used to manufacture the complementary field-effect transistor structures 1000a, 1000c, 1000d, 1000e, 1000f, 1000g, and 1000h, and the package structures 300a, 300c, 300d, 300e, 300f, 300g, and 300h are similar to those described below for the complementary field-effect transistor structure 1000b and the package structure 300b, and therefore will not be repeated here.

[0130] FIG. 10A-2 to FIG. 10H-2 This shows a schematic perspective view of an intermediate stage in the fabrication of a complementary field-effect transistor structure 1000b, according to some embodiments. FIG. 10A-3 to FIG. 10H-3 , FIG. 10A-4 to FIG. 10H-4 , FIG. 9 Passing the exam FIG. 10A-1 The display shows, according to some embodiments, respectively along FIG. 10A-2 line Y SD1 -Y SD1’ (i.e., in the Y direction), Y MG -Y MG’ (i.e., in the Y direction), Y SD2 -Y SD2’ A cross-sectional schematic diagram of an intermediate stage in the fabrication of a complementary field-effect transistor structure 1000b, shown (i.e., in the Y direction) and X-X' (i.e., in the X direction). More specifically, according to some embodiments, FIG. 10A-3 , FIG. 10A-4 , FIG. 9 and FIG. 10B-1 to FIG. 10H-1 show FIG. 10B-2 to FIG. 10H-2 The diagram shows a cross-sectional view of an intermediate stage of the complementary field-effect transistor structure 1000b. FIG. 10B-3 to FIG. 10H-3 , FIG. 10B-4 to FIG. 10H-4 , FIG. 9 , FIG. 10A-1 This is a cross-sectional schematic diagram of an intermediate stage of the complementary field-effect transistor structure 1000b after manufacturing.

[0131] First, based on some implementation examples, such as FIG. 10A-2 , FIG. 10A-3 , FIG. 10A-4 , FIG. 9 and FIG. 9As shown, a base 102B is formed, and a semiconductor stack (including first semiconductor material layers 106 and second semiconductor material layers 108) is formed over the base 102B. The base 102B can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the base 102B can include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials can include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials can include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials can include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0132] In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are alternately stacked over the base 102B to form the semiconductor stack. In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layers 106 are made of SiGe, and the second semiconductor material layers 108 are made of silicon. It is noted that although FIG. 10A-1 Four first semiconductor material layers 106 and three second semiconductor material layers 108 are shown, but the semiconductor stack can include fewer or more alternately stacked first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor stack can include two to five first semiconductor material layers 106 and two to five second semiconductor material layers 108.

[0133] According to some embodiments, as shown in FIG. 1C, a base 102B is formed, and a semiconductor stack (including first semiconductor material layers 106 and second semiconductor material layers 108) is formed over the base 102B. The base 102B can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the base 102B can include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials can include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials can include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials can include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. FIG. 10A-2 , FIG. 10A-3 , FIG. 10A-4 , FIG. 9 and FIG. 10A-1 As shown in FIG. 1C, after forming the first semiconductor material layers 106 and the second semiconductor material layers 108 as a semiconductor stack over the base 102B, the semiconductor stack is patterned to form the fin structures 104. The fin structures 104 can extend longitudinally in the X-direction. In some embodiments, the patterning process includes forming a mask structure 110 over the semiconductor material stack, and etching the semiconductor material stack and the underlying base 102B through the mask structure 110. In some embodiments, the mask structure 110 is a pad oxide layer and a pad nitride layer formed over the pad oxide layer. In some embodiments, the fin structures 104 include base fin structures 104B and a semiconductor stack formed over the base fin structures 104B.

[0134] According to some embodiments, as shown in FIG. 1C, a base 102B is formed, and a semiconductor stack (including first semiconductor material layers 106 and second semiconductor material layers 108) is formed over the base 102B. The base 102B can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the base 102B can include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials can include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials can include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials can include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. FIG. 10A-2 , FIG. 10A-3 , FIG. 10A-4 , FIG. 10B-1and FIG. 10B-2 As shown, after the formation of the fin structures 104, isolation structures 116 are formed around the fin structures 104. According to some embodiments, the isolation structures 116 are configured to electrically isolate the active regions (e.g., the fin structures 104) of the semiconductor structure, and are also referred to as shallow trench isolation (STI) features.

[0135] More specifically, an insulating layer can be formed around and covering the fin structures 104, and the insulating layer can be recessed to form the isolation structures 116, with the fin structures 104 protruding from the top surfaces of the isolation structures 116. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or combinations of the foregoing. Further, prior to the formation of the insulating layer, a liner layer (not shown) can be formed, and the liner layer can also be recessed to form the isolation structures 116. In some embodiments, the liner layer includes multiple layers of dielectric materials.

[0136] Thereafter, according to some embodiments, as shown in FIG. 10B-3 , FIG. 10B-4 , FIG. 10B-1 and FIG. 10B-2 the dummy gate structures 130 are formed across the fin structures 104, and gate spacers 140 and fin spacers 142 are formed on the sidewalls of the dummy gate structures 130 and the fin structures 104. The dummy gate structures 130 can be used to define the channel regions of the final transistor structures.

[0137] In some embodiments, the dummy gate structures 130 include a dummy gate dielectric layer 132 and a dummy gate electrode layer 134. In some embodiments, the dummy gate dielectric layer 132 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations of the foregoing. In some embodiments, the dummy gate electrode layer 134 is made of a conductive material, including polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), or combinations of the foregoing. In some embodiments, a hard mask layer 136 is formed over the dummy gate electrode layer 134. In some embodiments, the hard mask layer 136 includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide, and the nitride layer is silicon nitride.

[0138] According to some embodiments, as shown in FIG. 10B-3 , FIG. 10B-4 , FIG. 10C-1 and FIG. 10C-2As shown, after forming the dummy gate structure 130, a spacer layer can be formed to cover the top surface and sidewalls of the dummy gate structure 130 and the fin structure 104, and an etching process can be performed to form the gate spacer 140, the fin spacer 142, and the source / drain recesses 144 in the fin structure 104. The gate spacer 140 can be configured to separate the source / drain structure (formed subsequently) from the dummy gate structure 130, and the fin spacer 142 can be configured to limit the growth of the source / drain structure formed therein.

[0139] In some embodiments, the spacer layer is made of one or more dielectric materials. The dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), and / or combinations thereof. According to some embodiments, after forming the spacer layer, the spacer layer is etched to form gate spacers 140 on both sidewalls of the dummy gate structure 130 and fin spacers 142 covering the sidewalls of the fin structure 104. Furthermore, according to some embodiments, portions of the fin structure 104 not covered by the dummy gate structure 130 and gate spacers 140 are etched to form source / drain notches 144 during the etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 130 and gate spacers 140 may be used as etching masks during the etching process. In some embodiments, the isolation structure 116 is also lightly etched during the etching process.

[0140] According to some embodiments, such as FIG. 10C-3 , FIG. 10C-4 , FIG. 10C-1 and FIG. 10C-2 As shown, after forming the source / drain recess 144, the first semiconductor material layer 106 exposed by the source / drain recess 144 is laterally recessed to form a notch, and an internal spacer 148 is formed in the notch. In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 of the fin structure 104 from the source / drain recess 144. In some embodiments, during the etching process, the etching rate (or etching amount) of the first semiconductor material layer 106 is greater than that of the second semiconductor material layer 108, thereby forming a notch between adjacent second semiconductor material layers 108.

[0141] Next, according to some embodiments, interior spacers 148 are formed in the gaps between the second semiconductor material layers 108. The interior spacers 148 can be configured to space source / drain structures and gate structures formed in subsequent fabrication processes. In some embodiments, the interior spacers 148 are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination of the foregoing.

[0142] According to some embodiments, as shown in FIG. 1C, after the interior spacers 148 are formed, source / drain structures 150-1 and 150-2 are formed in the source / drain recesses 144, and a contact etch stop layer 160 and an interlayer dielectric layer 162 are formed over the source / drain structures 150-1 and 150-2. Depending on the context, the source / drain structures described herein can refer to a source or a drain, either alone or collectively. FIG. 10C-3 FIG. 10C-4 FIG. 10D-1 FIG. 10D-2 According to some embodiments, as shown in FIG. 1C, after the interior spacers 148 are formed, source / drain structures 150-1 and 150-2 are formed in the source / drain recesses 144, and a contact etch stop layer 160 and an interlayer dielectric layer 162 are formed over the source / drain structures 150-1 and 150-2. Depending on the context, the source / drain structures described herein can refer to a source or a drain, either alone or collectively.

[0143] In some embodiments, the source / drain structures 150-1 and 150-2 are formed by using an epitaxial growth process, such as molecular beam epitaxy, metal organic chemical vapor deposition, vapor phase epitaxy, or other applicable epitaxial growth process, or a combination of the foregoing. In some embodiments, the source / drain structures 150-1 and 150-2 are made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination of the foregoing. In some embodiments, the source / drain structures 150-1 and 150-2 are doped in situ during the epitaxial growth process. In some embodiments, the source / drain structures 150-1 and 150-2 are doped in one or more implantation processes after the epitaxial growth process.

[0144] According to some embodiments, after the source / drain structures 150-1 and 150-2 are formed, a contact etch stop layer (CESL) 160 is conformally formed to cover the source / drain structures 150-1 and 150-2, and an interlayer dielectric (ILD) layer 162 is formed over the contact etch stop layer 160. In some embodiments, the contact etch stop layer 160 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other applicable dielectric material, or a combination of the foregoing. The dielectric material of the contact etch stop layer 160 can be conformally deposited over the semiconductor structure by performing chemical vapor deposition, atomic layer deposition, other applicable method, or a combination of the foregoing.

[0145] ​​​The ILD layer 162 can include multiple layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric material. The ILD layer 162 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable process.

[0146] According to some embodiments, after depositing the contact etch stop layer 160 and the ILD layer 162, a planarization process (e.g., chemical mechanical polishing or an etch-back process) is performed until the dummy gate electrode layer 134 is exposed. Then, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench, and a gate structure 168 is formed in the gate trench, as shown in FIG. 1C. FIG. 10D-3 、 FIG. 10D-4 、 FIG. 10D-2 and FIG. 10D-4 According to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench, and a gate structure 168 is formed in the gate trench, as shown in FIG. 1C.

[0147] More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form the second semiconductor material layer 108 of the fin structure 104 as channel layers 108’ (e.g., nanostructures). According to some embodiments, the channel layers 108’ are vertically suspended above the substrate 102B and spaced apart from each other in the Z direction, as shown in FIG. 1D. FIG. 10D-1 and FIG. 10D-2 According to some embodiments, the channel layers 108’ are vertically suspended above the substrate 102B and spaced apart from each other in the Z direction, as shown in FIG. 1D.

[0148] According to some embodiments, the channel layers 108’ are vertically suspended above the substrate 102B and spaced apart from each other in the Z direction, as shown in FIG. 1D. FIG. 10D-3 、 FIG. 10D-4 、 FIG. 10D-1 and FIG. 10D-2As shown, after the formation of the channel layer 108', the interface layer 170, the gate dielectric layer 172, and the gate stack 174 are formed to surround the channel layer 108' of the gate structure 168. The interface layer 170 can be used to improve the interface between the channel layer 108' and the subsequently formed dielectric layer. In addition, the interface layer 170 can help to suppress mobility degradation of the charge carriers in the channel layer 108' that serves as the channel region of the transistor. In some embodiments, the interface layer 170 is an oxide layer formed by performing a thermal process. In some embodiments, the interface layer 170 has a thickness in a range from about 0.5 nm to about 1.5 nm.

[0149] According to some embodiments, after the formation of the interface layer 170, the gate dielectric layer 172 is conformally formed in the gate trench. In some embodiments, the gate dielectric layer 172 covers the interface layer 170 and surrounds the channel layer 108'. In some embodiments, the gate dielectric layer 172 is made of one or more layers of dielectric materials, such as Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (Hf02-Al203) alloy, other applicable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 172 is formed by using chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof.

[0150] Next, according to some embodiments, as shown in FIG. 1C, the gate stack 174 is formed over the gate dielectric layer 172 and forms the bottom transistor 100Bb of the complementary field effect transistor structure 1000b. In some embodiments, the gate stack 174 is made of one or more layers of conductive materials, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate stack 174 is formed by using chemical vapor deposition, atomic layer deposition, electroplating, other applicable methods, or combinations thereof. The bottom transistor 100Bb can be a p-type transistor or an n-type transistor. FIG. 10D-3 , FIG. 10D-4 , FIG. 10E-1 and FIG. 10E-2 Next, according to some embodiments, as shown in FIG. 1C, the gate stack 174 is formed over the gate dielectric layer 172 and forms the bottom transistor 100Bb of the complementary field effect transistor structure 1000b. In some embodiments, the gate stack 174 is made of one or more layers of conductive materials, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate stack 174 is formed by using chemical vapor deposition, atomic layer deposition, electroplating, other applicable methods, or combinations thereof. The bottom transistor 100Bb can be a p-type transistor or an n-type transistor.

[0151] According to some embodiments, after the formation of the bottom transistor 100Bb, the bonding structure BNB is formed over the bottom transistor 100Bb. More specifically, according to some embodiments, as shown in FIG. 1D, the bonding structure BNB is formed over the bottom transistor 100Bb. In some embodiments, the bonding structure BNB is formed by using chemical vapor deposition, atomic layer deposition, electroplating, other applicable methods, or combinations thereof. ​ , ​ , Figure 10E-3 and Figure 10E-4As shown, a dielectric bonding layer 202B is formed over the gate structure 168 and the interlayer dielectric layer 162. According to some embodiments, the dielectric bonding layer 202B directly contacts the top surface of the gate structure 168. In addition, according to some embodiments, the dielectric bonding layer 202B laterally extends over and contacts the top surface of the gate spacer 140 and the top surface of the interlayer dielectric layer 162. That is, according to some embodiments, the dielectric bonding layer 202B vertically overlaps the gate structure 168 and the source / drain structures 150-1 and 150-2. In some embodiments, the width of the dielectric bonding layer 202B is greater than the width of the gate structure 168 and the width of each of the source / drain structures 150-1 and 150-2 in both the X-direction and the Y-direction. Figure 10E-2 and Figure 10E-4 As shown, the dielectric bonding layer 202B directly contacts the top surface of the gate structure 168. In addition, according to some embodiments, the dielectric bonding layer 202B laterally extends over and contacts the top surface of the gate spacer 140 and the top surface of the interlayer dielectric layer 162. That is, according to some embodiments, the dielectric bonding layer 202B vertically overlaps the gate structure 168 and the source / drain structures 150-1 and 150-2. In some embodiments, the width of the dielectric bonding layer 202B is greater than the width of the gate structure 168 and the width of each of the source / drain structures 150-1 and 150-2 in both the X-direction and the Y-direction.

[0152] In some embodiments, the dielectric bonding layer 202B is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination of the foregoing. The dielectric bonding layer 202B can be formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0153] According to some embodiments, after the dielectric bonding layer 202B is formed, a via 206 is formed in the dielectric bonding layer 202B. More specifically, according to some embodiments, an opening (including openings 180-1, 180-2, and 180-3) is formed through the dielectric bonding layer 202B, and the via 206 is formed in the openings 180-1, 180-2, and 180-3. Figure 10F-1 , Figure 10F-2 , Figure 10F-3 and Figure 10F-4 According to some embodiments, after the dielectric bonding layer 202B is formed, a via 206 is formed in the dielectric bonding layer 202B. More specifically, according to some embodiments, an opening (including openings 180-1, 180-2, and 180-3) is formed through the dielectric bonding layer 202B, and the via 206 is formed in the openings 180-1, 180-2, and 180-3.

[0154] In some embodiments, the opening 180-1 is formed through the dielectric bonding layer 202B, the interlayer dielectric layer 162, and the contact etch stop layer 160 over the source / drain structure 150-1, such that the opening 180-1 exposes the top surface of the source / drain structure 150-1. The opening 180-1 can be formed by forming a mask layer over the dielectric bonding layer 202B, patterning the mask layer to form an opening in the mask layer, etching the dielectric bonding layer 202B through the opening, and removing the mask layer.

[0155] According to some embodiments, after the opening 180-1 is formed, the via 206 is formed in the opening 180-1. According to some embodiments, as shown in FIG. 2B, the via 206 is formed in the opening 180-1 by performing a deposition process to fill the opening 180-1 with a conductive material. Figure 10F-1 and Figure 10F-4As shown, a top surface of the via 206 is lower than a top surface of the dielectric bonding layer 202B. Formation of the via 206 can include forming a silicide layer (not shown) on the exposed top surface of the source / drain structure 150-1, and forming a conductive material over the silicide layer. The silicide layer can be formed by forming a metal layer over the top surface of the source / drain structure 150-1, and annealing the metal layer to react the metal layer with the source / drain structure 150-1. After forming the silicide layer, the unreacted metal layer can be removed.

[0156] According to some embodiments, after forming the silicide layer, the conductive material is formed in the opening 180-1. In some embodiments, the conductive material of the via 206 is Ru, Co, W, or the like. In some embodiments, the conductive material is formed by performing a selective deposition process. That is, the conductive material can be deposited over the silicide layer in the opening 180-1, but not over the dielectric bonding layer 202B. In some embodiments, the selective deposition of the conductive material for forming the via 206 stops before a top surface of the conductive material reaches a top surface of the dielectric bonding layer 202B.

[0157] In some other embodiments, the conductive material of the via 206 is formed by performing a chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other applicable deposition process. The conductive material will then fill in the opening 180-1 and be formed over the top surface of the dielectric bonding layer 202B. After forming the conductive material, a chemical mechanical polishing process can be performed to remove the conductive material over the dielectric bonding layer 202B, such that the top surface of the dielectric bonding layer 202B is exposed. In some embodiments, after performing the chemical mechanical polishing, a top surface of the conductive material of the via 206 is lower than the top surface of the dielectric bonding layer 202B. In some other embodiments, an additional etch-back process is performed to partially remove the conductive material, such that a top surface of the conductive material of the via 206 is lower than the top surface of the dielectric bonding layer 202B.

[0158] In some embodiments, the opening 180-2 is formed through the dielectric bonding layer 202B over the gate electrode 168, such that the opening 180-2 exposes a top surface of the gate electrode 168. According to some embodiments, as shown in FIG. 1C, the opening 180-2 is formed through the dielectric bonding layer 202B over the gate electrode 168, such that the opening 180-2 exposes a top surface of the gate electrode 168. In some embodiments, the opening 180-2 is formed through the dielectric bonding layer 202B over the gate electrode 168, such that the opening 180-2 exposes a top surface of the gate electrode 168. Figure 10F-2 and Figure 10F-4 According to some embodiments, as shown in FIG. 1C, after forming the opening 180-2, a via 206 is formed in the opening 180-2, and a top surface of the via 206 is lower than a top surface of the dielectric bonding layer 202B. Formation of the via 206 in the opening 180-2 can be similar to or the same as the via 206 in the opening 180-1 described above, except that a silicide layer is not formed. That is, according to some embodiments, the conductive material of the via 206 is directly deposited on the top surface of the gate electrode 168.

[0159] In some embodiments, the opening 180-3 is formed through the dielectric bonding layer 202B, the interlayer dielectric layer 162, the contact etch stop layer 160, and the isolation structure 116, such that the opening 180-3 partially protrudes into the substrate 102B. According to some embodiments, as shown in FIG. 18B, after the opening 180-3 is formed, a via 206 is formed in the opening 180-3, and a top surface of the via 206 is lower than a top surface of the dielectric bonding layer 202B. The formation of the via 206 in the opening 180-3 can be similar to or the same as the via 206 in the opening 180-1 described above, and is not elaborated here. In some embodiments, the openings 180-1, 180-2, 180-3 and the via 206 formed therein are formed in individual processes. In some other embodiments, the openings 180-1, 180-2, 180-3 and the via 206 formed therein are formed in the same process, respectively. Figure 10F-3

[0160] Next, according to some embodiments, as shown in FIGS. 18C and 18D, Figure 10G-1 Figure 10G-2 Figure 10G-3 and Figure 10G-4 then a bonding pad 208 is formed over the via 206 to fill the upper portion of the opening 180-1, 180-2, 180-3. As described above, according to some embodiments, the via 206 does not completely fill the opening 180-1, 180-2, 180-3, such that the bonding pad 208 can be formed in the upper portion of the opening 180-1, 180-2, 180-3.

[0161] In some embodiments, the bonding pad 208 is made of a conductive material different from the material used to form the via 206. In some embodiments, the bonding pad 208 is made of Co or W. In some embodiments, the conductive material of the bonding pad 208 is selectively deposited on the via 206. That is, according to some embodiments, the conductive material is only deposited on the exposed top surface of the via 206, but not on the dielectric bonding layer 202B. Therefore, an additional polishing process is not needed. In some embodiments, a top surface of the bonding pad 208 is substantially flush with a top surface of the dielectric bonding layer 202B. In some embodiments, each bonding pad 208 has a thickness greater than about 5 nm, such that the bonding pad 208 can have sufficient bonding capability in a subsequent bonding process.

[0162] According to some embodiments, as shown in FIGS. 18C and 18D, Figure 10G-1 Figure 10G-2 Figure 10G-3 and Figure 10G-4 the bonding structure BNB formed over the bottom transistor 100Bb includes the dielectric bonding layer 202B and the conductive bonding structures 204B-1b, 204B-2b, and 204B-3b formed through the dielectric bonding layer 202B. ​​​​​

[0163] In some embodiments, the conductive bonding structure 204B-1b is formed through the dielectric bonding layer 202B, the interlayer dielectric layer 162, and the contact etch stop layer 160 over the source / drain structure 150-1, such that the conductive bonding structure 204B-1b sits on a top surface of the source / drain structure 150-1. In some embodiments, the conductive bonding structure 204B-1b directly contacts the top surface of the source / drain structure 150-1.

[0164] In some embodiments, the conductive bonding structure 204B-2b is formed through the dielectric bonding layer 202B over the gate electrode 168, such that the conductive bonding structure 204B-2b sits on a top surface of the gate electrode 168. In some embodiments, the conductive bonding structure 204B-2b directly contacts the top surface of the gate electrode 168.

[0165] In some embodiments, the conductive bonding structure 204B-3b is formed through the dielectric bonding layer 202B, the interlayer dielectric layer 162, the contact etch stop layer 160, and the isolation structure 116. Further, in accordance with some embodiments, as shown in FIG. 2B, the conductive bonding structure 204B-3b extends further into the substrate 102B. That is, a bottom surface of the conductive bonding structure 204B-3b is lower than a bottom surface of the isolation structure 116. Figure 10G-3

[0166] Further, as noted above, in accordance with some embodiments, as shown in FIG. 2B, the conductive bonding structure 204B-3b is laterally spaced apart from the source / drain structure 150-2 in the Y-direction. In some embodiments, the conductive bonding structure 204B-3b is laterally spaced apart from the source / drain structure 150-2 (e.g., in the Y-direction) by greater than about 3 nm. Figure 10G-3

[0167] ​​In some embodiments, the conductive bonding structures 204B-lb, 204B-2b, and 204B-3b have different heights in the Z direction. In some embodiments, the height of the conductive bonding structure 204B-3b is greater than the height of the conductive bonding structure 204B-lb and the height of the conductive bonding structure 204B-2b in the Z direction. In some embodiments, the height of the conductive bonding structure 204B-lb is greater than the height of the conductive bonding structure 204B-2b in the Z direction. In some embodiments, the top surfaces of the conductive bonding structures 204B-lb, 204B-2b, and 204B-3b are substantially flush with each other. In some embodiments, the top surfaces of the conductive bonding structures 204B-lb, 204B-2b, and 204B-3b are substantially flush with the top surface of the dielectric bonding layer 202B. In some embodiments, the bottom surface of the conductive bonding structure 204B-2b is higher than the bottom surfaces of the conductive bonding structures 204B-lb, 204B-3b. In some embodiments, the bottom surface of the conductive bonding structure 204B-lb is higher than the bottom surface of the conductive bonding structure 204B-3b.

[0168] The processes shown in FIGS. 2A-2E can be performed on another wafer Figures 10A-1 through 10G-1 、 Figures 10A-2 through 10G-2 、 Figures 10A-3 through 10G-3 and Figures 10A-4 through 10G-4 to form a top transistor 100Tb over the substrate 102T. In addition, according to some embodiments, a bonding structure BNT is formed over the top transistor 100Tb.

[0169] The bottom transistor 100Bb and the top transistor 100Tb formed over the substrates 102B and 102T can have similar structures but different conductivity types. For example, the bottom transistor 100Bb can be a p-type transistor, while the top transistor 100Tb can be an n-type transistor. According to some embodiments, similar to the bonding structure BNB, the bonding structure BNT also includes a dielectric bonding layer 202T and conductive bonding structures 204Tb (including conductive bonding structures 204T-lb, 204T-2b, 204T-3b). The processes and materials used to form the bonding structure BNT (including the dielectric bonding layer 202T and the conductive bonding structures 204Tb), the top transistor 100Tb, and the substrate 102T can be similar to or the same as the processes and materials described above for forming the bonding structure BNB (including the dielectric bonding layer 202B and the conductive bonding structures 204b), the bottom transistor 100Bb, and the substrate 102B, and thus are not described in detail here.

[0170] The substrate 102B can be considered a first wafer, the substrate 102T can be considered a second wafer, and the second wafer can be bonded to the first wafer to form the complementary field effect transistor structure 1000b. More specifically, according to some embodiments, after the top transistor 100Tb is formed, the second substrate 102Tb is flipped upside down and the bonding structures BNT formed above the top transistor 100Tb are bonded to the bonding structures BNB, as shown in FIGS. 10H-1, 10H-2, 10H-3, and 10H-4. Further, according to some embodiments, the top transistor 100Tb and the bottom transistor 100Bb are bonded together by a hybrid bonding, including a dielectric-to-dielectric bonding and a metal-to-metal bonding. That is, according to some embodiments, the dielectric bonding layer 202B in the bonding structure BNB is directly bonded to (i.e., directly contacts) the dielectric bonding layer 202B in the bonding structure BNT. Further, according to some embodiments, the conductive bonding structures 204B-1b, 204B-2b, and 204B-3b in the bonding structure BNB are directly bonded to (i.e., directly contacts) the conductive bonding structures 204T-1b, 204T-2b, 204T-3b in the bonding structure BNT. In some embodiments, the hybrid bonding is achieved by an annealing process. In some embodiments, the annealing process is performed at a temperature of about 200 °C to about 400 °C for about 30 minutes to about 6 hours.

[0171] In some embodiments, as shown in FIGS. 10H-1, 10H-2, 10H-3, and 10H-4, the bonding pad 208 of the conductive bonding structure 204B-1b in the bonding structure BNB is directly bonded to (i.e., directly contacts) the bonding pad 208 of the conductive bonding structure 204T-1b in the bonding structure BNT. Figure 10H-1 In some embodiments, as shown in FIGS. 10H-1, 10H-2, 10H-3, and 10H-4, the bonding pad 208 of the conductive bonding structure 204B-2b in the bonding structure BNB is directly bonded to (i.e., directly contacts) the bonding pad 208 of the conductive bonding structure 204T-2b in the bonding structure BNT. Figure 10H-4 In some embodiments, as shown in FIGS. 10H-1, 10H-2, 10H-3, and 10H-4, the bonding pad 208 of the conductive bonding structure 204B-3b in the bonding structure BNB is directly bonded to (i.e., directly contacts) the bonding pad 208 of the conductive bonding structure 204T-3b in the bonding structure BNT. The bonding structure BNB and the bonding structure BNT can be considered a bonding structure BN. Figure 10H-2 Figure 10H-4 Figure 10H-3

[0172] Figures 11A through 11H FIGS. 10H-1, 10H-2, 10H-3, and 10H-4 show cross-sectional schematic views of intermediate stages of fabricating a packaged structure 300b, according to some embodiments. As described above, a first wafer (e.g., substrate 102B) and a second wafer (e.g., substrate 102T) can be bonded together, and the packaged structure 300b can then be formed. Figure 11A ​​​The structure shown may include the complementary field-effect transistor structure 1000b shown in Figures 10H-1, 10H-2, 10H-3, and 10H-4, but for clarity, some parts of the top transistor 100Tb and the bottom transistor 100Bb of the complementary field-effect transistor structure 1000b have been simplified. That is, Figures 11A through 11H The detailed structure and method shown for manufacturing the complementary field-effect transistor structure 1000b are similar to or the same as those described above. Figures 2A through 2C , Figure 9 , Figures 10A-1 through 10H-1 , Figures 10A-2 through 10H-2 , Figures 10A-3 through 10H-3 , Figures 10A-4 through 10H-4 The structure and method shown are not elaborated here.

[0173] According to some embodiments, such as Figure 11A As shown, a hybrid bonding structure is used to bond the top transistor 100Tb to the bottom transistor 100Bb. Furthermore, according to some embodiments, before bonding to the bottom transistor 100Bb, the top transistor 100Tb is flipped vertically, with substrates 102B and 102T located on either side of the top transistor 100Tb and the bottom transistor 100Bb. According to some embodiments, such as... Figure 11A As shown, the front side of the top transistor 100Tb is opposite to the front side of the bottom transistor 100Bb.

[0174] According to some embodiments, such as Figure 11B As shown, after the top transistor 100Tb is bonded to the bottom transistor 100Bb, a planarization process is performed over the substrate 102T. In some embodiments, the substrate 102T is planarized until the isolation structure 116 (not shown) is exposed. Figure 11B (In some embodiments, after the planarization process, the substrate 102T is completely removed).

[0175] Next, based on some embodiments, such as Figure 11C As shown, a dielectric layer 209T is formed above the back side of the top transistor 100Tb, and a back-side via 210T is formed through the dielectric layer 209T. In some embodiments, the dielectric layer 209T is made of a low dielectric constant dielectric material having a dielectric constant value of less than 7. In some embodiments, the dielectric layer 209T is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. The dielectric layer 209T can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0176] After forming the dielectric layer 209T, a back-side trench can be formed through the dielectric layer 209T. Furthermore, the back-side trench can expose the bottom of the source / drain structure 150-2, conductive junction structure 204T-2b, and gate structure 168 of the top transistor 100Tb. In some embodiments, the bottom of the source / drain structure 150-2, conductive junction structure 204T-2b, and gate structure 168 is also slightly removed. Subsequently, according to some embodiments, a back-side via 210T is formed in the back-side trench, such that the back-side via 210T is electrically connected to the back side of the top transistor 100Tb. In some embodiments, a back-side via 210T contacts the back side of the gate structure 168 of the top transistor 100Tb. In some embodiments, a back-side via 210T contacts the back side of the source / drain structure 150-2 of the top transistor 100Tb. In some embodiments, a back-side via 210T contacts the back side of a conductive bonding structure 204T-3B adjacent to the source / drain structure 150-2. In some embodiments, the back-side via 210T and conductive bonding structures 204T-1b and 204T-2b are on both sides of the top transistor 100Tb.

[0177] The back-side via 210T may include a back-side silicide layer (not shown) and a conductive filler layer formed above the back-side silicide layer. In some embodiments, the back-side silicide layer is an N-type epitaxial silicide, such as TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, or the like. In some embodiments, the back-side silicide layer is a P-type epitaxial silicide, such as NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or the like.

[0178] According to some embodiments, such as Figure 11C As shown, after forming the back-side silicide layer, a conductive filler layer is formed to fill the back-side trench, and a polishing process is performed to form the back-side via 210T. In some embodiments, the conductive filler layer is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof. The conductive filler layer can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0179] A liner layer (not shown) and / or a barrier layer (not shown) can be formed on the sidewall of the backside via 210T. For example, the liner layer can include silicon nitride, but any other applicable dielectric can be used as an alternative. For example, the barrier layer can include tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, or the like can also be used. The liner layer and the barrier layer can be formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0180] According to some embodiments, as shown in FIG. 2A, after the backside via 210T is formed, an interconnect structure 212T is formed over the backside via 210T and over the backside of the top transistor 100Tb. In some embodiments, the interconnect structure 212T is a backside interconnect structure. In some embodiments, the interconnect structure 212T includes a plurality of dielectric layers 218T and conductive structures 220T (e.g., vias and metal lines) formed in the plurality of dielectric layers 218T. Figure 11D

[0181] In some embodiments, the backside via 210T is electrically connected to a conductive structure 220T in the interconnect structure 212T. According to some embodiments, as shown in FIG. 2A, the conductive structure 220T in the interconnect structure 212T is electrically connected to the top transistor 100Tb through the backside via 210T. In addition, according to some embodiments, the backside via 210T connected to the backside of the source / drain structure 150-2 is electrically connected to the backside via 210T connected to the backside of the conductive bonding structure 204B-3b (not shown in FIG. 2A, please refer to FIG. 2B) through the conductive structure 220T of the interconnect structure 212T. Figure 11D Figure 11D Figure 2B

[0182] The dielectric layer 218T can include multiple layers made of multiple layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other applicable low-k dielectric materials. The dielectric layer 218T can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0183] ​​​​In some embodiments, the conductive structure 220T is made of a conductive material, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, combinations thereof, or other applicable materials. In some embodiments, the conductive structure 220T can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0184] After the interconnect structure 212T is formed, a carrier substrate 230 is attached to the interconnect structure 212T to provide a semiconductor structure with mechanical and structural support in subsequent manufacturing processes. The carrier substrate 230 may comprise glass, silicon oxide, aluminum oxide, metal, the aforementioned alloys, and / or the like. In some embodiments, the interconnect structure 212T is attached to the carrier substrate 230 by fusion bonding. In some embodiments, an adhesive layer 232 is formed over the carrier substrate 230, an adhesive layer 234 is formed over the interconnect structure 212T, and the carrier substrate 230 is bonded to the interconnect structure 212T by bonding the adhesive layers 232 and 234. The adhesive layers 232 and 234 may be adhesive or tape.

[0185] According to some embodiments, such as Figure 11F As shown, after the carrier substrate 230 is attached to the interconnect structure 212T, the substrate 102B undergoes a planarization process. In some embodiments, the substrate 102B undergoes a planarization process until the isolation structure 116 (not shown) is exposed. Figure 11F (in some embodiments, after the planarization process, the substrate 102B is completely removed).

[0186] Next, based on some embodiments, such as Figure 11G As shown, dielectric layer 209B is formed above the back side of the bottom of bottom transistor 100Bb, and back-side via 210B is formed through dielectric layer 209B. The processes and materials used to form dielectric layer 209B and back-side via 210B can be similar to or the same as those used to form dielectric layer 209T and back-side via 210T as described above, and therefore will not be repeated here.

[0187] According to some embodiments, such as Figure 11H As shown, after forming the back-side via 210B, an interconnect structure 212B is formed above the back-side via 210B and above the back side of the bottom transistor 100Bb. The process and materials used to form the interconnect structure 212B may be similar to or the same as those used to form the interconnect structure 212T described above, and therefore will not be repeated here.

[0188] In some embodiments, the interconnect structure 212B includes a plurality of dielectric layers 218B and conductive structures 220B (e.g., vias and metal lines) formed in the plurality of dielectric layers 218B. In some embodiments, the backside via 210B is electrically connected to a conductive structure 220B in the interconnect structure 212B. According to some embodiments, as shown in FIG. 3B, the conductive structure 220B in the interconnect structure 212B is electrically connected to the bottom transistor 100Bb through the backside via 210B. In addition, according to some embodiments, the backside via 210B connected to the backside of the source / drain structure 150-2 is electrically connected to the backside via 210B connected to the backside of the conductive bonding structure 204B-3b through the conductive structure 220B of the interconnect structure 212B (see FIG. 3B). Figure 11D Figure 2B ).

[0189] According to some embodiments, as shown in FIG. 3B, the package structure 300b includes a complementary field effect transistor structure 1000b formed therein. In addition, according to some embodiments, the complementary field effect transistor structure 1000b includes a bottom transistor 100Bb formed above a first wafer and a top transistor 100Tb formed above a second wafer. In some embodiments, the bottom transistor 100Bb is a p-type transistor and the top transistor 100Tb is an n-type transistor. In some embodiments, the bottom transistor 100Bb is an n-type transistor and the top transistor 100Tb is a p-type transistor. The top transistor 100Tb and the bottom transistor 100Bb can each include at least one channel layer 108' and a gate structure 168 surrounding the channel layer 108'. According to some embodiments, a bonding structure BN including a bonding structure BNB and a bonding structure BNT is vertically located between the top transistor 100Tb and the bottom transistor 100Bb. Figure 11H

[0190] In some embodiments, the bonding structure BN includes a dielectric bonding layer 202B attached to the gate structure 168 of the bottom transistor 100Bb, a conductive bonding structure 204B through the dielectric bonding layer 202B, a dielectric bonding layer 202T attached to the dielectric bonding layer 202B and the gate structure 168 of the top transistor 100Tb, and a conductive bonding structure 204T formed through the dielectric bonding layer 202T and bonded to the conductive bonding structure 204B.

[0191] ​​Furthermore, according to some embodiments, backside via 210T is electrically connected to top transistor 100Tb, and backside via 210B is electrically connected to bottom transistor 100Bb. Moreover, according to some embodiments, interconnect structure 212T is formed over backside via 210T, and interconnect structure 212B is formed over backside via 210B. According to some embodiments, interconnect structure 212T and interconnect structure 212B are located on both sides of top transistor 100Tb and bottom transistor 100Bb. In some embodiments, the closest distance between gate structure 168 of top transistor 100Tb and gate structure 168 of bottom transistor 100Bb is substantially equal to the sum of the thickness of dielectric bonding layer 202B and the thickness of dielectric bonding layer 202T in the Z direction. In some embodiments, interconnect structure 212B and top transistor 100Tb are on both sides of bottom transistor 100Bb in the Z direction, while interconnect structure 212T and bottom transistor 100Bb are on both sides of bottom transistor 100Tb in the Z direction.

[0192] Figure 12 A cross-sectional schematic view of an intermediate stage of fabricating package structure 300b is shown, according to some other embodiments. Figure 12 The structure shown is substantially the same as Figure 11A The structure shown, except that additional sacrificial layers are formed. More specifically, according to some embodiments, sacrificial layer 103B is formed over substrate 102B before bottom transistor 100Bb is formed, and sacrificial layer 103T is formed over substrate 102T before top transistor 100Tb is formed.

[0193] According to some embodiments, sacrificial layers 103B and 103T can be configured to function as etch stop layers during a planarization process used to remove substrates 102B and 102T. That is, during Figure 11B and Figure 11F sacrificial layers 103T and 103B function as etch stop layers, such that the planarization process is stopped when sacrificial layers 103T and 103B are exposed. Thereafter, sacrificial layers 103T and 103B can be removed. In addition to sacrificial layers 103T and 103B, the processes shown in Figures 11A through 11H may be performed to form package structure 300b. In some embodiments, sacrificial layers 103B and 103T are both SiGe layers.

[0194] As described above, n-type field effect transistors (e.g., top transistors 100Ta-100Th) and p-type field effect transistors (e.g., bottom transistors 100Ba-100Bh) can be formed individually on two wafers. The two wafers can be bonded together by hybrid bonding, such that the n-type field effect transistors and the p-type field effect transistors can be bonded to form complementary field effect transistor structures (e.g., complementary field effect transistor structures 1000a-1000h). Since the n-type field effect transistors and the p-type field effect transistors are formed individually, the first formed transistors will not be damaged by the fabrication processes (e.g., thermal processes) used to form the later transistors. Thus, the performance of the final complementary field effect transistor structures can be improved.

[0195] Hybrid bonding includes dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, metal-to-metal bonding is achieved by bonding conductive bonding structures (e.g., conductive bonding structures 204T-1a-204T-1h, 204T-2a-204T-2h, 204T-3a-204T-3h, 204B-1a-204B-1h, 204B-2a-204B-2h, 204B-3a-204B-3h).

[0196] Since the conductive bonding structures can have relatively small dimensions, the conductive bonding structures can be made of conductive materials, such as ruthenium, cobalt, or tungsten. These conductive materials can have less resistance at smaller dimensions, which can improve the performance of the final device compared to copper. In addition, since the conductive bonding structures are formed first on different wafers and then bonded together, the aspect ratio of these conductive structures can be relatively small compared to via structures in complementary field effect transistor structures formed by a single process. Furthermore, the conductive materials of the conductive bonding structures can be formed by selective deposition, thus the topography can be better controlled and the yield can be improved.

[0197] It should be understood that elements in the illustrated transistors 100a-100h can be combined and / or interchanged. In addition, it should be noted that, Figures 1A through 12 like elements in the above-described structures can be labeled with like reference numerals and can include like or similar materials and can be formed by like or similar processes, and thus, for brevity, these redundant details are omitted. In addition, although the above-described structures are described with respect to a method, it should be understood that, Figures 1A through 12 with respect to a method, it should be understood that, Figures 1A through 12 The disclosed structures are not limited to the method and can be structures independent of the method. Similarly, Figures 1A through 12 The illustrated method is not limited to the disclosed structures and can be independent of the structures. Furthermore, according to some embodiments, the above-described channel layers (e.g., nanostructures) can include nanowires, nanosheets, or other applicable nanostructures.

[0198] Further, while the disclosed methods are illustrated and described above as a series of acts or events, it will be appreciated that the illustrated ordering of these acts or events may be modified in some other implementations. In other implementations, additional acts or events not described above can be performed in addition to or instead of those illustrated. Further, many of the described acts or events can be performed in parallel, or in different orders, or in different groupings. Further, in some implementations, one or more of the acts or events listed above can be performed as a single act or event.

[0199] Further, the terms "approximately," "substantially," "about," and "near," as used above, consider small variations as being within the scope of the terms. For example, these terms can refer to instances where the event or circumstance occurs exactly as well as instances where the event or circumstance occurs in a close manner.

[0200] Embodiments can be provided for forming a semiconductor structure. The semiconductor structure can include forming a bottom transistor and a top transistor over two individual wafers. The top transistor can then be bonded to the bottom transistor by a bonding structure. Further, the bonding structure can include a first conductive bonding structure formed over the bottom transistor and a second conductive bonding structure formed over the top transistor. The first conductive bonding structure can be bonded to the second conductive structure. As the bottom transistor and the top transistor are formed individually, the manufacturing process can be simplified and the performance of the final device can be improved.

[0201] In some embodiments, a semiconductor structure is provided, including a first transistor including a first channel layer; and a first gate structure surrounding the first channel layer; the semiconductor structure further including a second transistor including a second channel layer; and a second gate structure surrounding the second channel layer; the semiconductor structure further including a bonding structure vertically between the first transistor and the second transistor, the bonding structure including a first dielectric bonding layer attached to the first gate structure; and a first conductive bonding structure formed through the first dielectric bonding layer; the bonding structure further including a second dielectric bonding layer attached to the first dielectric bonding layer and the second gate structure; and a second conductive bonding structure formed through the second dielectric bonding layer and bonded to the first conductive bonding structure.

[0202] In some other embodiments, the semiconductor structure described above further includes a plurality of first source / drain structures attached to two sides of the first channel layer; and a plurality of second source / drain structures attached to two sides of the second channel layer, wherein the first dielectric bonding layer extends laterally from a top surface of the first gate structure to vertically overlap the plurality of first source / drain structures.

[0203] In some other embodiments, the semiconductor structure further comprises a first backside via connected to a first one of the first source / drain structures, wherein the first backside via and the first conductive bonding structure are located on two sides of the first transistor.

[0204] In some other embodiments, the first conductive bonding structure is electrically connected to a second one of the first source / drain structures.

[0205] In some other embodiments, the first conductive bonding structure contacts the first gate structure.

[0206] In some other embodiments, the semiconductor structure further comprises a first interconnect structure attached to the first backside via; a second backside via connected to a first one of the second source / drain structures; and a second interconnect structure attached to the second backside via, wherein the first interconnect structure and the second interconnect structure are located on two sides of the first transistor and the second transistor.

[0207] In some embodiments, a semiconductor structure is provided, the semiconductor structure comprising a p-type transistor comprising a first channel layer; a first source / drain structure and a second source / drain structure attached to two sides of the first channel layer in a first direction; the p-type transistor further comprising a first gate structure surrounding the first channel layer and extending in a second direction. The semiconductor structure further comprises a first conductive bonding structure bonded to the p-type transistor; a second conductive bonding structure bonded to the first conductive bonding structure in a third direction; the semiconductor structure further comprising an n-type transistor bonded to the second conductive bonding structure, the n-type transistor comprising a second channel layer; a third source / drain structure and a fourth source / drain structure attached to two sides of the second channel layer; the n-type transistor further comprising a second gate structure surrounding the second channel layer.

[0208] In some other embodiments, the semiconductor structure further comprises a first dielectric bonding layer bonded to the p-type transistor in the third direction; and a second dielectric bonding layer bonded to the first dielectric bonding layer and the n-type transistor, wherein the first conductive bonding structure is formed through the first dielectric bonding layer, and the second conductive bonding structure is formed through the second dielectric bonding layer.

[0209] In some other embodiments, a closest distance between the first gate structure and the second gate structure is substantially equal to a sum of a thickness of the first dielectric bonding layer and a thickness of the second dielectric bonding layer in the third direction.

[0210] In some other embodiments, the first conductive bonding structure is spaced apart from the second source / drain structure in the first direction or the second direction, but is electrically connected to the second source / drain structure.

[0211] In some other embodiments, the first conductive bonding structure contacts the first gate structure in the third direction, and the second conductive bonding structure contacts the second gate structure in the third direction.

[0212] In some other embodiments, the semiconductor structure further comprises a third conductive bonding structure electrically connected to the first source / drain structure; and a fourth conductive bonding structure bonded to the third conductive bonding structure in the third direction and electrically connected to a third source / drain structure, wherein a thickness of the third conductive bonding structure in the third direction is greater than a thickness of the first conductive bonding structure in the third direction.

[0213] In some other embodiments, the first conductive bonding structure contacts the first source / drain structure in the third direction.

[0214] In some other embodiments, the first conductive bonding structure comprises a first via; and a first bonding pad formed over the first via, wherein the first via and the first bonding pad are made of different conductive materials.

[0215] In some other embodiments, the semiconductor structure further comprises a first backside via electrically connected to the p-type transistor; and a first interconnect structure attached to the first backside via, wherein the first interconnect structure and the n-type transistor are located on two sides of the p-type transistor in the third direction.

[0216] In some other embodiments, the semiconductor structure further comprises a second backside via electrically connected to the n-type transistor; and a second interconnect structure attached to the second backside via, wherein the second interconnect structure and the first interconnect structure are located on two sides of the n-type transistor in the third direction.

[0217] In some embodiments, a method of fabricating a semiconductor structure is provided, the method comprising forming a first transistor over a first substrate, the first transistor comprising a first channel layer and a first gate structure adjacent to the first channel layer. The method also comprises forming a first dielectric bonding layer covering a top surface of the first gate structure, and forming a first conductive bonding structure through the first dielectric bonding layer and electrically connected to the first transistor. The method also comprises forming a second transistor over a second substrate, the second transistor comprising a second channel layer and a second gate structure adjacent to the second channel layer. The method also comprises forming a second dielectric bonding layer covering a top surface of the second gate structure, forming a second conductive bonding structure through the second dielectric bonding layer and electrically connected to the second transistor. The method also comprises bonding the first dielectric bonding layer to the second dielectric bonding layer, and bonding the first conductive bonding structure to the second conductive bonding structure.

[0218] In some other embodiments, the method further includes, after bonding the first dielectric bonding layer to the second dielectric bonding layer, removing the second substrate; forming a second backside via that is electrically connected to the second transistor; and forming a second interconnect structure that is electrically connected to the second backside via, wherein the second interconnect structure and the first transistor are on two sides of the second transistor.

[0219] In some other embodiments, the method further includes bonding a carrier substrate to the second interconnect structure; after bonding the carrier substrate, removing the first substrate; forming a first backside via that is electrically connected to the first transistor; and forming a first interconnect structure that is electrically connected to the first backside via.

[0220] In some other embodiments, the step of forming the first electrically conductive bonding structure through the first dielectric bonding layer further includes forming an opening in the first dielectric bonding layer to expose a top surface of the first gate structure; and selectively depositing the first bonding pad in the opening.

[0221] The foregoing outlines features of many embodiments, such that those skilled in the art can better understand the aspects of the present embodiments. Those skilled in the art should appreciate that they can readily use the present embodiments as a basis for designing or modifying other processes and structures, while yet achieving the same ultimate objectives. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present embodiments. It should be noted that various changes can be made to the embodiments described and equivalents can be substituted without departing from the true spirit and scope of the present embodiments. In this regard, any reference numerals in the accompanying drawings are included for illustrative purposes only and do not limit the scope of the claims.

Claims

1. A semiconductor structure, characterized by, comprises: a first transistor, wherein the first transistor comprises: a first channel layer; and a first gate structure surrounding the first channel layer; a second transistor, wherein the second transistor comprises: a second channel layer; and a second gate structure surrounding the second channel layer; a junction structure vertically located between the first transistor and the second transistor, wherein the junction structure comprises: a first dielectric junction layer attached to the first gate structure; a first conductive junction structure formed through the first dielectric junction layer; a second dielectric junction layer attached to the first dielectric junction layer and the second gate structure; and a second conductive junction structure formed through the second dielectric junction layer and joined to the first conductive junction structure.

2. The semiconductor structure of claim 1, wherein, further comprises: a plurality of first source / drain structures attached to two sides of the first channel layer; and a plurality of second source / drain structures attached to two sides of the second channel layer, wherein the first dielectric junction layer extends laterally from a top surface of the first gate structure to vertically overlap the plurality of first source / drain structures.

3. The semiconductor structure of claim 2, wherein, further comprises: a first backside via connected to a first one of the plurality of first source / drain structures, wherein the first backside via and the first conductive junction structure are located on two sides of the first transistor.

4. The semiconductor structure of claim 3, wherein, the first conductive junction structure is electrically connected to a second one of the plurality of first source / drain structures.

5. The semiconductor structure of claim 3, wherein, the first conductive junction structure contacts the first gate structure.

6. The semiconductor structure of any one of claims 3 to 5, wherein, further comprises: a first interconnect structure attached to the first backside via; a second backside via connected to the plurality of second source / drain structures; and a second interconnect structure attached to the second backside via, wherein the first interconnect structure and the second interconnect structure are located on two sides of the first transistor and the second transistor.

7. A semiconductor structure, characterized by comprises: a p-type transistor, wherein the p-type transistor comprises: a first channel layer; a first source / drain structure and a second source / drain structure attached to two sides of the first channel layer in a first direction; and a first gate structure surrounding the first channel layer and extending in a second direction; a first conductive junction structure joined to the p-type transistor; a second conductive junction structure joined to the first conductive junction structure in a third direction; and an n-type transistor joined to the second conductive junction structure, wherein the n-type transistor comprises: a second channel layer; a third source / drain structure and a fourth source / drain structure attached to two sides of the second channel layer; and a second gate structure surrounding the second channel layer. further comprises:

8. The semiconductor structure of claim 7, wherein, a first dielectric junction layer joined to the p-type transistor in the third direction; and a second dielectric junction layer joined to the first dielectric junction layer and the n-type transistor, wherein the first conductive junction structure is formed through the first dielectric junction layer and the second conductive junction structure is formed through the second dielectric junction layer. a closest distance between the first gate structure and the second gate structure is substantially equal to a sum of a thickness of the first dielectric junction layer and a thickness of the second dielectric junction layer in the third direction.

9. The semiconductor structure of claim 8, wherein, ​ 10. The semiconductor structure of claim 7, wherein, The first conductive bonding structure is spaced apart from the second source / drain structure in the first direction or the second direction, but is electrically connected to the second source / drain structure.

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