Display panel and display terminal

Abstract

The utility model relates to a display panel and a display terminal. The display panel comprises a substrate and a thin film transistor, wherein the thin film transistor comprises a first electrode, an interlayer insulating layer, a second electrode, an active part and a grid electrode; the interlayer insulating layer comprises a first side wall and a second side wall; the active part covers the first side wall and extends to be in contact with the first electrode and the second electrode; the grid electrode at least covers the first side wall and the second side wall. A first electrode, an interlayer insulating layer and a second electrode are stacked in the thickness direction of a substrate, so that the extension direction of a first side wall becomes the length direction of a channel, a vertical channel is realized, and the mobility of the thin film transistor is improved; the grid electrode covers the first side wall, a front channel can be formed in the active part, the grid electrode covers the second side wall, a rear channel can be formed in the active part, the effect of a vertical double-grid channel is achieved, and the mobility of the thin film transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display terminal. BACKGROUND

[0002] With the continuous development of display technology, the demand for high resolution, high refresh rate, low power consumption, logic circuit display integration and the like is increasing, and these all put forward higher requirements on thin film transistors (TFT). For example, higher pixel charging rate requires TFT to have higher mobility. TFT can adopt metal oxide semiconductor as an active layer, and thin film transistor adopting metal oxide semiconductor as an active layer is called oxide TFT. Oxide TFT has the advantages of good large-size uniformity and low leakage current, but the mobility of oxide TFT at present is about 10 cm 2 / v·s, which cannot meet the requirements of TFT characteristics of increasing product specifications.

[0003] Therefore, it is urgent to solve the above technical problems. CONTENT OF THE UTILITY MODEL

[0004] The embodiments of the present application provide a display panel and a display terminal to improve the technical problem that the mobility of oxide TFT cannot meet the requirements of TFT characteristics of increasing product specifications.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, which comprises a substrate and a thin film transistor arranged on the substrate, and the thin film transistor comprises:

[0006] A first electrode is arranged on one side surface of the substrate;

[0007] An interlayer insulating layer is arranged on one side surface of the first electrode away from the substrate, and the interlayer insulating layer comprises opposite first and second side walls;

[0008] A second electrode is arranged on one side surface of the interlayer insulating layer away from the substrate;

[0009] An active part covers the first side wall and extends to contact the first electrode and the second electrode;

[0010] A gate electrode covers at least the first and second side walls, and the first and second electrodes are both arranged in insulation with the gate electrode.

[0011] Optionally, the interlayer insulating layer is provided with a through hole corresponding to the middle region of the first electrode, a side wall of the interlayer insulating layer close to the middle region of the first electrode is a first side wall, and a side wall of the interlayer insulating layer away from the middle region of the first electrode is a second side wall.

[0012] Optionally, the second side wall is flush with the side wall of the first electrode.

[0013] Optionally, the display panel further comprises a gate insulating layer arranged on a surface of the gate electrode close to the substrate, and a projection of the gate electrode on the substrate overlaps a projection of the gate insulating layer on the substrate.

[0014] Optionally, the display panel further comprises a gate insulating layer arranged on a surface of the gate electrode close to the substrate, and the gate insulating layer is provided with a hollow hole corresponding to the second side wall, and the gate electrode contacts the second side wall through the hollow hole.

[0015] Optionally, the active part covers a side wall of the second electrode close to the through hole and at least part of a surface of the second electrode away from the substrate.

[0016] Optionally, the active part covers a bottom wall of the through hole.

[0017] Optionally, the thickness of the interlayer insulating layer is 100-500 nm.

[0018] Optionally, the display panel further comprises a passivation layer arranged on a side of the thin film transistor away from the substrate, and the passivation layer covers the thin film transistor.

[0019] According to a second aspect of the present application, a display terminal is provided, which comprises the display panel described above.

[0020] In the display panel of the embodiments of the present application, the first electrode, the interlayer insulating layer and the second electrode are stacked in the thickness direction of the substrate, so that the active part extends along the first side wall, the extension direction of the first side wall becomes the channel length direction, thereby realizing a vertical channel and improving the mobility of the thin film transistor; the gate electrode covers the first side wall, so that a front channel is formed in the active part; the gate electrode covers the second side wall, so that a rear channel is formed in the active part; by forming the front channel and the rear channel, the effect of a vertical double-gate channel is realized, and the mobility of the thin film transistor can be further improved.

[0021] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description only show some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0023] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0024] Figure 1 is a top view structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0025] Figure 2 is Figure 1 is a sectional structural diagram at C-C in

[0026] Figure 3 is Figure 1 is another sectional structural diagram at C-C in

[0027] Figures 4A to 4F is Figure 1 is a manufacturing process flow diagram of the display panel in

[0028] Figure 5 is a structural schematic diagram of a display terminal provided in an exemplary embodiment of the present disclosure.

[0029] Explanation of reference numerals:

[0030] Display panel 1, display area AA, non-display area NA, sub-pixel 100;

[0031] Substrate 10;

[0032] Thin film transistor 20, first electrode 21, interlayer insulating layer 22, first sidewall 22a, second sidewall 22b, second electrode 23, active part 24, gate 25, gate insulating layer 26;

[0033] Thickness d1 of interlayer insulating layer 22;

[0034] Passivation layer 30;

[0035] Display terminal 2, terminal body 3. DETAILED DESCRIPTION

[0036] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort are within the protection scope of the present application.

[0037] To achieve the above object, according to a first aspect of the present application, as shown in the accompanying drawings, Figures 1 to 2 A display panel 1 is provided, which comprises a substrate 10 and a thin film transistor 20 disposed on the substrate 10, the thin film transistor 20 comprising a first electrode 21, an interlayer insulating layer 22, a second electrode 23, an active part 24 and a gate 25, the first electrode 21 being disposed on one side surface of the substrate 10; the interlayer insulating layer 22 being disposed on the side surface of the first electrode 21 away from the substrate 10, the interlayer insulating layer 22 comprising a first sidewall 22a and a second sidewall 22b; the second electrode 23 being disposed on the side surface of the interlayer insulating layer 22 away from the substrate 10; the active part 24 covering the first sidewall 22a and extending to contact the first electrode 21 and the second electrode 23; the gate 25 covering at least the first sidewall 22a and the second sidewall 22b, and the first electrode 21 and the second electrode 23 are both insulated from the gate 25.

[0038] The display panel 1 can be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0039] As shown in the accompanying drawings, Figure 1 The display panel 1 comprises a display area AA and a non-display area NA disposed peripherally of the display area AA. The display area AA can be provided with a plurality of sub-pixels 100, which can comprise red sub-pixels, green sub-pixels and blue sub-pixels, so as to realize color display. The non-display area NA can be provided with a driving circuit, such as a gate driving circuit, etc., which can provide driving signals for the sub-pixels 100.

[0040] In some embodiments, the material of the substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz or silicon wafer, etc. The flexible material can be one of polyimide (PI), polycarbonate (PC), poly (norbornene) (PNB) and polyethylene terephthalate (PET), etc.

[0041] As shown in the accompanying drawings, Figure 2As shown, the thin-film transistor 20 is disposed on one side surface of the substrate 10. The thin-film transistor 20 can be disposed in the display area AA and / or the non-display area NA. When the thin-film transistor 20 is located in the display area AA, it can function as a transistor in a pixel driving circuit to drive the sub-pixel 100 for display. When the thin-film transistor 20 is located in the non-display area NA, it can function as a transistor in a gate driving circuit, but is not limited thereto.

[0042] One of the first electrode 21 and the second electrode 23 serves as the source of the thin-film transistor 20, and the other serves as the drain of the thin-film transistor 20. Both the first electrode 21 and the second electrode 23 are conductive materials, such as one or an alloy of two metals like Mo or Cu, or transparent conductive oxides like ITO (indium tin oxide), IZO (indium zinc oxide), and ZnO (zinc oxide).

[0043] The material of the interlayer insulating layer 22 can be SiO x or SiN x / SiO x Layers, but not limited to these.

[0044] like Figure 2 As shown, an interlayer insulating layer 22 is disposed on the first electrode 21. The interlayer insulating layer 22 has through holes that expose the middle region of the first electrode 21. It should be noted that the surface of the first electrode 21 facing away from the substrate 10 can be divided into a middle region and an edge region, with the middle region and the edge region adjacent to each other. That is to say, the interlayer insulating layer 22 is not disposed in the middle region of the first electrode 21, but is disposed in the edge region of the first electrode 21, i.e., the interlayer insulating layer 22 forms a ring structure.

[0045] like Figure 2 As shown, the interlayer insulation layer 22 has two opposing sidewalls, one of which is a first sidewall 22a and the other is a second sidewall 22b.

[0046] The active layer 24 is made of metal oxide semiconductor, such as IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), and IGZTO (indium gallium zinc tin oxide). Oxide TFTs fabricated using metal oxides as the active layer 24 exhibit high mobility. For example, when Ln-IZO (lanthanide rare-earth-doped metal oxide) is used as the active layer in an oxide TFT, a 30cm mobility can be achieved. 2 / v·s migration rate.

[0047] The active layer 24 covers the first sidewall 22a and extends to contact the first electrode 21 and the second electrode 23, that is, in the thickness direction d1 of the interlayer insulating layer 22, the active layer 24 covers the first sidewall 22a, the end of the active layer 24 close to the first electrode 21 overlaps the first electrode 21, and the end of the active layer 24 close to the second electrode 23 overlaps the second electrode 23. The part of the active layer 24 corresponding to the first sidewall 22a constitutes a vertical channel. Since the vertical channel has a smaller channel length L, the mobility of the thin film transistor 20 can be improved.

[0048] It should be noted that, Figure 2 In some embodiments, in the patterning process, the first sidewall 22a of the interlayer insulating layer 22 and the side surface of the interlayer insulating layer 22 close to the substrate 10 form an acute angle or a right angle. When the first sidewall 22a of the interlayer insulating layer 22 and the side surface of the interlayer insulating layer 22 close to the substrate 10 form a right angle, the thickness d1 of the interlayer insulating layer 22 is the channel length L. When the first sidewall 22a of the interlayer insulating layer 22 and the side surface of the interlayer insulating layer 22 close to the substrate 10 form an acute angle, the thickness d1 of the interlayer insulating layer 22 is slightly smaller than the channel length L. That is, the channel length L is greater than or equal to the thickness d1 of the interlayer insulating layer 22. The mobility is negatively correlated with the channel length L, so reducing the channel length L can improve the mobility.

[0049] In some embodiments, the thickness of the active layer 24 can be 20-40 nm. For example, the thickness of the active layer 24 can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.

[0050] The gate 25 covers the first sidewall 22a and the second sidewall 22b, and the material of the gate 25 can be Cu, Mo, Al, etc. The first electrode 21 and the second electrode 23 are both insulated from the gate 25, that is, the first electrode 21 and the second electrode 23 are separated from the gate 25 by an insulating material.

[0051] Since the gate 25 covers both surfaces of the active layer 24, a front channel and a back channel can be formed. The back channel refers to the interface of the side of the active layer 24 in contact with the first sidewall 22a, and the front channel and the back channel are opposite in the thickness direction of the active layer 24. The front channel refers to the interface of the side of the active layer 24 away from the first sidewall 22a. The part of the gate 25 covering the first sidewall 22a is used to control the front channel, and the part of the gate 25 covering the second sidewall 22b is used to control the back channel. By forming a front channel and a back channel on the active layer 24, the effect of a double-gate channel can be achieved, further improving the mobility of the thin film transistor 20.

[0052] Optionally, as Figure 2As shown, the interlayer insulating layer 22 has through holes corresponding to the middle region of the first electrode 21. The sidewall of the interlayer insulating layer 22 near the middle region of the first electrode 21 is the first sidewall 22a, and the sidewall of the interlayer insulating layer 22 away from the middle region of the first electrode 21 is the second sidewall 22b.

[0053] like Figure 2 As shown, the interlayer insulating layer 22 has through holes corresponding to the middle region of the first electrode 21, meaning that the interlayer insulating layer 22 has a ring-shaped structure. The sidewall closest to the middle region of the first electrode 21 is called the first sidewall 22a, and the sidewall furthest from the middle region of the first electrode 21 is called the second sidewall 22b. The first sidewall 22a is also the inner sidewall of the ring-shaped structure, and the second sidewall 22b is also the outer sidewall of the ring-shaped structure.

[0054] In some embodiments, throughout the entire annular structure, the active portion 24 overlaps with the first electrode 21 and the second electrode 23, meaning the active portion 24 covers the entire circumferential first sidewall 22a of the through hole. With this configuration, the circumference of the through hole is equal to the channel width W, thereby maximizing the channel width W without increasing the size of the through hole.

[0055] Optionally, the sidewall of the second electrode 23 near the through hole is flush with the first sidewall 22a, and / or the sidewall of the second electrode 23 away from the through hole is flush with the second sidewall 22b.

[0056] In some embodiments, the sidewall of the second electrode 23 near the through hole is flush with the first sidewall 22a. With the above arrangement, the first sidewall 22a and the sidewall of the second electrode 23 near the through hole can transition smoothly, reducing the unevenness of the film layers such as the active part 24 and the gate 25, thereby reducing the stress inside the film layers and making it more conducive to the fabrication of foldable display panels.

[0057] In some embodiments, the sidewall of the second electrode 23 away from the through hole is flush with the second sidewall 22b, which can make the second sidewall 22b and the sidewall of the second electrode 23 away from the through hole transition smoothly, reducing the unevenness of the film layer such as the gate 25, thereby reducing the stress inside the film layer, which is more conducive to the production of foldable display panels.

[0058] In some embodiments, the sidewall of the second electrode 23 near the through hole is flush with the first sidewall 22a, and the sidewall of the second electrode 23 away from the through hole is flush with the second sidewall 22b, thereby further reducing the stress inside the film layer and making it more conducive to the fabrication of a foldable display panel.

[0059] Optionally, such as Figure 2As shown, the second sidewall 22b is flush with the sidewall of the first electrode 21. This means that the outline of the orthographic projection of the interlayer insulating layer 22 onto the substrate 10 coincides with the outline of the orthographic projection of the first electrode 21 onto the substrate 10. This configuration allows for a smaller footprint of the thin-film transistor 20.

[0060] Optionally, such as Figure 3 As shown, the display panel 1 also includes a gate insulating layer 26 disposed on the surface of the gate 25 near the substrate 10, wherein the orthographic projection of the gate 25 on the substrate 10 overlaps with the orthographic projection of the gate insulating layer 26 on the substrate 10. By making the orthographic projection of the gate 25 on the substrate 10 overlap with the orthographic projection of the gate insulating layer 26 on the substrate 10, the gate insulating layer 26 and the gate 25 can be formed using the same patterning process, simplifying the manufacturing process of the display panel 1.

[0061] In the front channel, the gate insulating layer 26 separates the gate 25 and the active portion 24; in the rear channel, the gate insulating layer 26 separates the gate 25 and the first electrode 21, and the gate insulating layer 26 separates the gate 25 and the second electrode 23.

[0062] In some embodiments, the material of the gate insulating layer 26 is the same as that of the interlayer insulating layer 22, thereby eliminating the interface between the gate insulating layer 26 and the interlayer insulating layer 22 and improving the mobility of the thin film transistor 20.

[0063] In some embodiments, the material of the gate insulating layer 26 is different from the material of the interlayer insulating layer 22.

[0064] Optionally, such as Figure 3 As shown, Figure 3 Implementation examples and Figure 2 The difference in the embodiment lies in the gate insulating layer 26. For example... Figure 3 As shown, the gate insulating layer 26 has a cutout hole corresponding to the second sidewall 22b, and the gate 25 contacts the second sidewall 22b through the cutout hole.

[0065] The cutout can be formed through a patterning process, exposing the second sidewall 22b. The gate 25 covers the sidewall and bottom wall of the cutout and contacts the second sidewall 22b. This means that at the back channel, only an interlayer insulating layer 22 is provided between the gate 25 and the active portion 24, thereby reducing the lateral spacing between the gate 25 and the active portion 24 and improving the mobility of the thin-film transistor 20. Here, lateral spacing refers to... Figure 2 The horizontal spacing in the middle.

[0066] Optionally, such as Figure 2 and Figure 3 As shown, the active portion 24 covers at least a portion of the sidewall of the second electrode 23 near the through hole and the side of the second electrode 23 away from the substrate 10.

[0067] The side wall of the second electrode 23 near the side of the via hole refers to the side wall of the inner ring of the ring structure in the second electrode 23. By covering the side wall of the second electrode 23 near the side of the via hole and the upper surface of the second electrode 23 with the active part 24, the contact area of the active part 24 and the second electrode 23 can be increased, thereby reducing the precision requirement of the patterning process of the active part 24 and making the thin film transistor 20 easier to manufacture.

[0068] Optionally, as shown in Figure 2 and Figure 3 , the active part 24 covers the bottom wall of the via hole. That is, the active part 24 can continuously cover the bottom wall and the first side wall 22a of the via hole. By the above arrangement, the contact area of the active part 24 and the middle region of the first electrode 21 can be increased, thereby ensuring the reliability of the connection.

[0069] Optionally, the thickness d1 of the interlayer insulating layer 22 is 100 nanometers to 500 nanometers. For example, the thickness d1 of the interlayer insulating layer 22 can be 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, 450 nanometers, 500 nanometers, etc. The thickness d1 of the interlayer insulating layer 22 refers to the dimension in the direction perpendicular to the bearing surface of the substrate 10. The bearing surface of the substrate 10 refers to the surface of the substrate 10 near the side of the thin film transistor 20.

[0070] When the thickness d1 of the interlayer insulating layer 22 is 100 nanometers to 500 nanometers, the thin film transistor 20 with a channel length less than or equal to 0.5 microns can be formed. The smaller the thickness d1 of the interlayer insulating layer 22, the smaller the channel length L, which is beneficial to increase the width-length ratio W / L of the channel and improve the mobility of the thin film transistor 20.

[0071] The thin film transistor 20 provided by the embodiments of the present application has an on-current that is at least 10 times more than that of a planar TFT, and an equivalent mobility >100 c㎡ / v·s.

[0072] Optionally, as shown in Figure 2 and Figure 3 , the display panel 1 further comprises a passivation layer 30, the passivation layer 30 is arranged on the side of the thin film transistor 20 away from the substrate 10, and the passivation layer 30 covers the thin film transistor 20.

[0073] The material of the passivation layer 30 can be a stack of SiO x or SiN x / SiO x . The passivation layer 30 is used to protect the thin film transistor 20 and prevent water vapor and the like from invading the thin film transistor 20.

[0074] The following will be described in combination with Figures 4A to 4FA manufacturing process of a display panel 1 is provided for the embodiments of the present application.

[0075] As shown in Figure 4A , a substrate 10 is provided, and a first electrode 21 is formed on the substrate 10.

[0076] In some embodiments, the material of the substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz, or a silicon wafer, etc. The flexible material can be one of polyimide (PI), polycarbonate (PC), poly (norbornene) (PNB), and polyethylene terephthalate (PET), etc.

[0077] The first electrode 21 can be formed by a film forming process to form an electrode layer, and then a patterning process is performed on the electrode layer to form the first electrode 21.

[0078] The film forming process can include physical vapor deposition (PVD) film forming, etc. PVD refers to a process of transferring atoms or molecules from a source to the surface of a substrate by a physical process. The basic methods of PVD include vacuum evaporation, sputtering, ion plating (hollow cathode ion plating, hot cathode ion plating, arc ion plating, active reactive ion plating, radio frequency ion plating, direct current discharge ion plating).

[0079] The material of the first electrode 21 can be one of Mo, Cu, etc. or an alloy of two of them, and the material of the first electrode 21 can also be ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), etc. transparent conductive oxide.

[0080] The patterning process includes steps such as coating photoresist, exposure and development, etching, etc.

[0081] As shown in Figure 4B , an interlayer insulating layer 22 is formed on the first electrode 21, and the interlayer insulating layer 22 is provided with a through hole corresponding to the middle region of the first electrode 21, and the through hole exposes the middle region of the first electrode 21. The sidewall of the interlayer insulating layer 22 on the side close to the through hole is a first sidewall 22a, and the sidewall of the interlayer insulating layer 22 on the side away from the through hole is a second sidewall 22b.

[0082] The interlayer insulating layer 22 can be formed by a film forming process and a patterning process. The interlayer insulating layer 22 can also be subjected to high-temperature annealing for 2 to 3 hours, and the temperature of the high-temperature annealing is 300 to 400℃.

[0083] In some embodiments, the material of the interlayer insulating layer 22 can be SiO x or SiN x / SiO xThe interlayer insulating layer 22 has a thickness d1 that can range from 100 nanometers to 500 nanometers, and the channel length of the thin film transistor 20 is affected by the thickness d1 of the interlayer insulating layer 22.

[0084] like Figure 4C As shown, a second electrode 23 is formed on the interlayer insulating layer 22, and the second electrode 23 is located on the upper surface of the interlayer insulating layer 22.

[0085] The formation process of the second electrode 23 is similar to that of the first electrode 21, and the material of the second electrode 23 can be the same as that of the first electrode 21. The material of the second electrode 23 can also be a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), or ZnO (zinc oxide).

[0086] like Figure 4D As shown, an active portion 24 is formed on the second electrode 23, and the active portion 24 covers the first sidewall 22a and at least part of the middle region of the first electrode 21 and at least part of the second electrode 23.

[0087] The active part 24 can be formed through film deposition and patterning processes. The material of the active part 24 is a metal oxide semiconductor, such as IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0088] Since the active part 24 covers the through hole, the channel width W of the active part 24 is equal to the perimeter of the through hole, thereby increasing the width-to-length ratio W / L of the channel and achieving a higher mobility.

[0089] like Figure 4E As shown, a gate insulating layer 26 and a gate 25 are formed on the active portion 24. The gate 25 covers the entire structure in the preceding process, that is, the gate 25 covers the active portion 24, the first electrode 21, the second electrode 23, and the second sidewall 22b. Since the gate 25 covers both the front and back surfaces of the active portion 24, a front channel and a rear channel can be formed. The rear channel refers to the interface on the side of the active portion 24 that contacts the first sidewall 22a, and the front channel and rear channel are opposite each other in the thickness direction of the active portion 24. The front channel refers to the interface on the side of the active portion 24 that is away from the first sidewall 22a. By forming a front channel and a rear channel on the active portion 24, the mobility of the thin-film transistor 20 can be improved.

[0090] In some embodiments, a film layer of gate insulating layer is first formed by a film deposition process, and then a film layer of gate is formed by a film deposition process. Then, the gate insulating layer 26 and gate 25 are formed by the same patterning process, thereby simplifying the manufacturing process of the display panel 1.

[0091] In some embodiments, the material of the gate insulating layer 26 may be SiO2. x or SiN x / SiO x The stacking of layers.

[0092] In some embodiments, the gate 25 may be made of metals such as Cu, Mo, and Al.

[0093] like Figure 4F As shown, a passivation layer 30 is formed on the thin-film transistor 20, and the passivation layer 30 covers the thin-film transistor 20.

[0094] The material of passivation layer 30 can be SiO x or SiN x / SiO x The stacked layers. The passivation layer 30 is used to protect the thin-film transistor 20 from moisture and other contaminants.

[0095] It should be noted that the first electrode 21 and the second electrode 23 of the thin-film transistor 20 can be connected to other components of the display panel 1 via traces. The connection traces between the first electrode 21 and the second electrode 23 and other components are not shown in the accompanying drawings of this application. For example, the first electrode 21 and the second electrode 23 can be extended along the bearing surface of the substrate 10 to form an extension, and then the traces can be electrically connected to the extensions of the first electrode 21 and the second electrode 23 via vias.

[0096] like Figure 5 As shown, according to a second aspect of this application, a display terminal 2 is provided, which includes the aforementioned display panel 1 and terminal body 3, wherein the display panel 1 and terminal body 3 are integrated into one unit.

[0097] In this embodiment, as Figure 5 As shown, the display terminal 2 includes the aforementioned display panel 1.

[0098] In this embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0099] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0101] The embodiments, implementation manners and related technical features of the present application can be combined with each other without conflict.

[0102] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a substrate and a thin film transistor disposed on the substrate, the thin film transistor comprising: a first electrode disposed on a side surface of the substrate; an interlayer insulating layer disposed on a side surface of the first electrode away from the substrate, the interlayer insulating layer comprising opposite first and second side walls; a second electrode disposed on a side surface of the interlayer insulating layer away from the substrate; an active part covering the first side wall and extending to contact the first and second electrodes; a gate electrode covering at least the first and second side walls, the first and second electrodes each being disposed in insulating relation to the gate electrode.

2. The display panel of claim 1, wherein, The interlayer insulating layer is provided with a through hole corresponding to a middle region of the first electrode, the side wall of the interlayer insulating layer close to the middle region of the first electrode being the first side wall, and the side wall of the interlayer insulating layer away from the middle region of the first electrode being the second side wall.

3. The display panel of claim 2, wherein, The second side wall is flush with the side wall of the first electrode.

4. The display panel of claim 2, wherein, The display panel further comprises a gate insulating layer disposed on a side surface of the gate electrode close to the substrate, a normal projection of the gate electrode on the substrate overlapping a normal projection of the gate insulating layer on the substrate.

5. The display panel of claim 2, wherein, The display panel further comprises a gate insulating layer disposed on a side surface of the gate electrode close to the substrate, the gate insulating layer being provided with a hollow hole corresponding to the second side wall, the gate electrode contacting the second side wall through the hollow hole.

6. The display panel of claim 2, wherein, The active part covers a side wall of the second electrode close to the through hole and at least part of a surface of the second electrode away from the substrate.

7. The display panel of claim 6, wherein, The active part covers a bottom wall of the through hole.

8. The display panel of claim 1, wherein, The thickness of the interlayer insulating layer is 100-500 nm.

9. The display panel of any one of claims 1 to 8, wherein, The display panel further comprises a passivation layer disposed on a side of the thin film transistor away from the substrate, the passivation layer covering the thin film transistor.

10. A display terminal, characterized by The display panel comprises the display panel of any one of claims 1-9.

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