TO-247 packaging structure capable of improving heat dissipation efficiency
By using a metal substrate, bent surface mount leads, and copper sheet heat dissipation in the TO-247 package structure, the problem of low heat dissipation efficiency is solved, achieving efficient heat dissipation and simplified production.
Patent Information
- Application Number
- CN202520346802.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-02-28
AI Technical Summary
The existing TO-247 package structure has low heat dissipation efficiency, which cannot meet the heat dissipation requirements of high-power devices, leading to device overheating, affecting performance and life cycle. In addition, traditional heat dissipation methods are cumbersome, increasing production costs and reducing production efficiency.
The chip is carried on a metal substrate, the pins are changed to bent surface mount pins, copper sheet is added for heat dissipation, the packaged chips are merged and share a metal frame, the current path is shortened, the number of pins is increased to reduce on-resistance, and surface mount technology is used for production.
It improves heat dissipation efficiency, reduces on-resistance and heat generation, simplifies production processes, reduces costs, and increases production efficiency.
Smart Images
Figure CN223859670U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of TO-247 package structure, and in particular to a TO-247 package structure that improves heat dissipation efficiency. Background Technology
[0002] TO-247 is an internationally standardized power semiconductor package, officially known as the TO-247 package (Transistor Outline Package 247). The TO-247 package is widely used in power devices due to its excellent thermal performance and mechanical strength, making it a popular choice in electronic products.
[0003] The existing TO-247 package uses a single-chip structure, which improves heat dissipation by locking a small heat sink on the copper frame on the back of the device. However, the heat dissipation area of a single small heat sink is limited and cannot fully meet the heat dissipation requirements of high-power devices. This causes the device to be prone to heat concentration during operation, which affects its performance and lifespan. In addition, the production process is complicated.
[0004] In some applications requiring high current and low resistance (such as BMS battery management systems), the temperature rise issue in the BMS battery management system needs to be addressed by symmetrically soldering two TO-247 packaged chips. However, symmetrical soldering of two TO-247 packaged chips requires soldering on a separate PCB board, and the heat dissipation method using heat sinks is cumbersome, increasing production costs and significantly reducing production efficiency. Due to the limitations of existing packaging forms, the traditional TO-247 package structure has too low heat dissipation efficiency, which can easily lead to device overheating and further cause other heat concentration problems.
[0005] The purpose of this invention is to design a TO-247 package structure that improves heat dissipation efficiency to address the problems existing in the prior art. Utility Model Content
[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a TO-247 independent packaging structure and a combined packaging structure that improves heat dissipation efficiency, thereby solving the above-mentioned technical problems.
[0007] This utility model provides a TO-247 package structure to improve heat dissipation efficiency, comprising:
[0008] A metal substrate that carries the packaged chip;
[0009] A drain bonding frame D is disposed in the center of a metal substrate, and the drain bonding frame D is connected to the drain of the packaged chip;
[0010] A source solder frame S is arranged at the edge of the metal substrate, and the source solder frame S is connected to the source of the packaged chip through a solder wire;
[0011] A gate solder frame G is arranged at the edge of the metal substrate, and the gate solder frame G is connected to the gate of the packaged chip through a solder wire;
[0012] A plurality of drain pins are arranged at the edge of the drain solder frame D, a plurality of source pins are arranged at the edge of the source solder frame S, and a plurality of gate pins are arranged at the edge of the gate solder frame G, and the drain pins, the source pins and the gate pins are curved patch pins.
[0013] Further, when the metal substrate is used to carry the independently packaged chip, the drain pins, the source pins and the gate pins are arranged at the same edge of the metal substrate.
[0014] Further, when the metal substrate is used to carry the independently packaged chip, a plastic packaging shell is arranged above the metal substrate, and the copper sheet C is wrapped outside the plastic packaging shell of each group of symmetrically soldered independently packaged chips, so as to dissipate heat of the independently packaged chip.
[0015] Further, the bending angle of the curved patch pin is 120°, the length of the starting end of the curved patch pin is 3mm, and the length of the soldering end of the curved patch pin is 3.5mm.
[0016] Further, the drain solder frame D, the source solder frame S and the gate solder frame G are all copper solder frames.
[0017] Further, when the metal substrate is used to carry the combined packaged chip, the source solder frame S comprises a first source solder frame S1 and a second source solder frame S2, which are symmetrically arranged at the edges of the metal substrate, and the first source solder frame S1 and the second source solder frame S2 are connected to the source of the combined packaged chip through a solder wire.
[0018] Further, when the metal substrate is used to carry the combined packaged chip, the gate solder frame G comprises a first gate solder frame G1 and a second gate solder frame G2, which are symmetrically arranged at the edges of the metal substrate, the first gate solder frame G1 is arranged on the same side as the first source solder frame S1, the second gate solder frame G2 is arranged on the same side as the second source solder frame S2, and the first gate solder frame G1 and the second gate solder frame G2 are connected to the gate of the combined packaged chip through a solder wire.
[0019] Further, a plurality of source pins are symmetrically arranged at the edges of the first source solder frame S1 and the second source solder frame S2, so as to reduce the on-resistance.
[0020] The utility model has the advantages that:
[0021] One is to wrap copper sheet C on the TO-247 plastic package of each group of symmetrically welded independent packaged chips, to reduce the on-resistance of the drain of the symmetrically welded independent packaged chips to the drain of another independent packaged chip, and when the copper sheet C is not added, the current from the drain of the independent packaged chip to the drain of another independent packaged chip is from the drain pin of the independent packaged chip to the pin of another independent packaged chip through a PCB board, and after the copper sheet C is added, the current is directly from the drain pin of the independent packaged chip to the pin of another independent packaged chip through the copper sheet C, so that the resistance between the drains of the two independent packaged chips is greatly reduced, and under the same current condition, the heat generated is also reduced after the resistance is reduced.
[0022] Two is to bend the original pin and change it to a curved patch pin, so that the whole package can be mass produced by surface mount technology (SMT).
[0023] Three is to divide the source electrode welding frame S and the gate electrode welding frame G into two (first source electrode welding frame S1 and second source electrode welding frame S2, first gate electrode welding frame G1 and second gate electrode welding frame G2) respectively, so that two chips can be combined and packaged on one metal substrate, the current path between the two chips in the traditional design needs to pass through external PCB wiring, while the combined packaging design directly shortens the path between the chips, so that the two chips share one metal frame, reduces the current flow path, and further reduces the on-resistance and improves the heat dissipation capacity.
[0024] Four is to reduce the on-resistance of the combined packaged chip and improve the heat dissipation capacity, the source electrode welding frame S is widened, and the pin corresponding to each source electrode welding frame (S1, S2) can be increased to several pins, the resistance will be reduced accordingly with the increase of the number of pins in the process of current passing through the pins, the number of source pins is increased, the current density and path resistance of each pin are reduced, and the overall on-resistance of the package is reduced, and the electrical efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS
[0025] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed to be used in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.
[0026] Figure 1 is a TO-247 package structure diagram of embodiment one.
[0027] Figure 2 is a wire bonding diagram of the TO-247 package structure of embodiment one.
[0028] Figure 3This is a circuit schematic diagram of the back-to-back symmetrical packaged chips of Example 1.
[0029] Figure 4 This is a structural diagram of the plastic encapsulation shell with copper sheet C wrapped around its outer side in Example 1.
[0030] Figure 5 This is a diagram of the bent patch pin structure of Embodiment 1.
[0031] Figure 6 This is a diagram of the TO-247 package structure in Example 2.
[0032] Figure 7 This is a wire bonding diagram of the TO-247 package structure in Example 2.
[0033] Figure 8 This is a dimensional diagram of the metal substrate in Example 2. Detailed Implementation
[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the present invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] Example 1
[0036] like Figure 1 , Figure 2 As shown, this embodiment provides a TO-247 package structure to improve heat dissipation efficiency, including:
[0037] A metal substrate that carries the packaged chip;
[0038] A drain bonding frame D is disposed in the center of a metal substrate, and the drain bonding frame D is connected to the drain of the packaged chip;
[0039] The source bonding frame S is disposed at the edge of the metal substrate, and the source bonding frame S is connected to the source of the packaged chip through bonding wires;
[0040] A gate bonding frame G is disposed at the edge of a metal substrate, and the gate bonding frame G is connected to the gate of the packaged chip via bonding wires;
[0041] The drain bonding frame D has a drain pin at its edge, the source bonding frame S has a source pin at its edge, and the gate bonding frame G has a gate pin at its edge. The drain pin, source pin, and gate pin are bent surface mount pins.
[0042] Further, when the metal substrate is used to carry the independently packaged chips, the drain pin, source pin and gate pin are arranged at the same edge of the metal substrate.
[0043] Further, when the metal substrate is used to carry the independently packaged chips, a plastic packaging shell is arranged above the metal substrate, and a copper sheet C is wrapped outside the plastic packaging shell of each group of symmetrically welded independently packaged chips, for heat dissipation of the independently packaged chips.
[0044] Further, the drain welding frame D, the source welding frame S and the gate welding frame G are all copper welding frames.
[0045] In the embodiment, as shown in Figure 3 , Figure 4 a copper sheet C is wrapped on each group of symmetrically welded TO-247 plastic packages, so as to reduce the conduction resistance of the drain of the independently packaged chip to the drain of another independently packaged chip in the symmetric welding. Without the copper sheet C, the current from the drain of the independently packaged chip to the drain of another independently packaged chip is from the drain pin of the independently packaged chip to the pin of the drain of another independently packaged chip through the PCB board. After the copper sheet C is added, the current directly passes through the copper sheet C from the drain pin of the independently packaged chip to the pin of the drain of another independently packaged chip, which greatly reduces the resistance between the drains of the two independently packaged chips. After the resistance is reduced, the heat generated under the same current condition is also reduced.
[0046] Further, as shown in Figure 5 , the bending angle of the bending patch pin is 120°, the length of the starting end of the bending patch pin is 3 mm, and the length of the welding end of the bending patch pin is 3.5 mm.
[0047] In the embodiment, the original pin of the TO-247 package is used for plug-in mounting and needs to be inserted into the PCB board for welding. The original pin is bent and changed into a bending patch pin, so that the whole package can be mass-produced by surface mount technology (SMT). The welding end of the bending patch pin is the position where the pin contacts the PCB pad, and the electrical and mechanical connection is realized through solder. The part of the pin connected to the package body is the starting end of the pin and the package structure. As shown in Figure 5 , the thickness H1 of the plastic packaging shell is 4.83-5.21 mm, and the thickness H2 of the copper welding frame is 2 mm.
[0048] Embodiment Two
[0049] The difference between the embodiment and the embodiment one is that only one chip is independently packaged on the metal substrate in the embodiment one, and then the copper sheet C is wrapped outside the plastic packaging shell of the symmetrically welded independent packaging chips to improve the heat dissipation capacity. In the embodiment two, two chips are directly symmetrically combined and packaged on one metal substrate to improve the heat dissipation capacity, and there is no need to additionally wrap the copper sheet C outside the plastic packaging shell.
[0050] As shown in Figure 6 , Figure 7 , when the metal substrate is used to carry the combined and packaged chip, the source welding frame S includes a first source welding frame S1 and a second source welding frame S2, which are symmetrically arranged at the edges of the metal substrate, and the first source welding frame S1 and the second source welding frame S2 are connected to the source of the combined and packaged chip through welding wires.
[0051] When the metal substrate is used to carry the combined and packaged chip, the gate welding frame G includes a first gate welding frame G1 and a second gate welding frame G2, which are symmetrically arranged at the edges of the metal substrate, the first gate welding frame G1 is arranged on the same side as the first source welding frame S1, and the second gate welding frame G2 is arranged on the same side as the second source welding frame S2, and the first gate welding frame G1 and the second gate welding frame G2 are connected to the gate of the combined and packaged chip through welding wires.
[0052] A plurality of source pins are symmetrically arranged at the edges of the first source welding frame S1 and the second source welding frame S2, respectively, for reducing the on-resistance.
[0053] In the embodiment, since two symmetrically welded chips need to be packaged, the source welding frame S and the gate welding frame G need to be divided into two (the first source welding frame S1 and the second source welding frame S2, and the first gate welding frame G1 and the second gate welding frame G2) respectively, so that the two chips can be combined and packaged on one metal substrate. In the traditional design, the current path between the two chips needs to pass through the external PCB wiring, while the combined and packaged design directly shortens the path between the chips, so that the two chips share one metal frame, reduces the current flow path, and then reduces the on-resistance and improves the heat dissipation capacity.
[0054] In order to reduce the on-resistance of the combined and packaged chip and improve the heat dissipation capacity, the source welding frame S is widened, and the pins corresponding to each source welding frame (S1, S2) can be increased to several pins, three pins in the figure, and the number can also be designed according to the actual use. In the process of current passing through the pins, the resistance will decrease with the increase of the number of pins. Increasing the number of source pins reduces the current density and path resistance of each pin, and then reduces the overall on-resistance of the package and improves the electrical efficiency.
[0055] Due to the widening of the original source pad, the gate pad needs to be appropriately reduced, and the width of the gate pin and the drain pin is reduced, and the package area occupied by the gate pin is reduced. The double-chip wire leads out need to be managed by the symmetrical pin mode to separate the electrodes, and the upper and lower symmetrical pins optimize the layout of the electrodes of each chip, and higher efficient current transmission is realized.
[0056] As shown in Figure 8 The length L of the metal substrate in the embodiment is 20.8-21.1mm, and the width W of the metal substrate is 15.75-16.13mm.
[0057] The above only describes some embodiments of the utility model, and does not limit the protection scope of the utility model, and equivalent devices or equivalent process transformations are made by using the contents of the utility model specification and drawings, or are directly or indirectly used in other related technical fields, and are also included in the patent protection scope of the utility model.
Claims
1. A TO-247 package structure for improving heat dissipation efficiency, characterized in that, The utility model relates to a metal substrate for carrying independent packaged chips, comprising: a metal substrate carrying packaged chips; a drain solder frame D arranged in the center of the metal substrate, the drain solder frame D connecting the drain of the packaged chips; a source solder frame S arranged at the edge of the metal substrate, the source solder frame S connecting the source of the packaged chips through solder wires; a gate solder frame G arranged at the edge of the metal substrate, the gate solder frame G connecting the gate of the packaged chips through solder wires; a drain pin arranged at the edge of the drain solder frame D, a source pin arranged at the edge of the source solder frame S, and a gate pin arranged at the edge of the gate solder frame G, the drain pin, the source pin, and the gate pin being curved patch pins.
2. The TO-247 package structure with improved heat dissipation efficiency according to claim 1, characterized in that, When the metal substrate is used to carry independent packaged chips, the drain pin, the source pin, and the gate pin are arranged at the same edge of the metal substrate.
3. The TO-247 package structure with improved heat dissipation efficiency according to claim 2, characterized in that, When the metal substrate is used to carry independent packaged chips, a plastic packaging shell is arranged above the metal substrate, and a copper sheet C is wrapped outside the plastic packaging shell of each set of symmetrically soldered independent packaged chips for heat dissipation of the independent packaged chips.
4. The TO-247 package structure with improved heat dissipation efficiency according to claim 1, characterized in that, The bending angle of the curved patch pin is 120°, the length of the starting end of the curved patch pin is 3 mm, and the length of the soldering end of the curved patch pin is 3.5 mm.
5. The TO-247 package structure with improved heat dissipation efficiency according to claim 1, characterized in that, The drain solder frame D, the source solder frame S, and the gate solder frame G are all copper solder frames.
6. The TO-247 package structure with improved heat dissipation efficiency according to claim 1, characterized in that, When the metal substrate is used to carry merged packaged chips, the source solder frame S includes a first source solder frame S1 and a second source solder frame S2, which are symmetrically arranged at the edges of the metal substrate, respectively, and the first source solder frame S1 and the second source solder frame S2 connect the source of the merged packaged chips through solder wires.
7. The TO-247 package structure with improved heat dissipation efficiency according to claim 6, characterized in that, When the metal substrate is used to carry merged packaged chips, the gate solder frame G includes a first gate solder frame G1 and a second gate solder frame G2, which are symmetrically arranged at the edges of the metal substrate, respectively, the first gate solder frame G1 is arranged on the same side as the first source solder frame S1, the second gate solder frame G2 is arranged on the same side as the second source solder frame S2, and the first gate solder frame G1 and the second gate solder frame G2 connect the gate of the merged packaged chips through solder wires.
8. The TO-247 package structure with improved heat dissipation efficiency according to claim 7, characterized in that, A plurality of source pins are symmetrically arranged at the edges of the first source solder frame S1 and the second source solder frame S2, respectively, for reducing the on-resistance.