Heterogeneous trench gate silicon carbide VDMOS
By designing a heterogeneous trench gate structure in silicon carbide VDMOS, increasing the gate dielectric thickness, and introducing a floating gate, the contradiction between low switching loss and low on-resistance of the device is resolved, achieving high switching speed and high reliability.
Patent Information
- Application Number
- CN202423285927.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing silicon carbide VDMOS devices have difficulty simultaneously achieving the characteristics of low switching loss, high switching speed, and low on-resistance in various fields.
A heterogeneous trench gate silicon carbide VDMOS was designed. By increasing the dielectric thickness of the gate metal layer and introducing a floating gate structure, the gate leakage capacitance was reduced, while the positions of the masking region and the floating gate were optimized to improve the reliability of the device.
It achieves low switching losses, high switching speed and low on-resistance, while improving the gate reliability of the device.
Smart Images
Figure CN223872669U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a heterogeneous trench gate silicon carbide VDMOS. Background Technology
[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. While the performance requirements for silicon carbide VDMOS vary across different applications, the overall requirements generally include lower on-resistance, faster switching speed, and higher reliability. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a heterogeneous trench gate silicon carbide VDMOS, which achieves the characteristics of low switching loss, high switching speed and low on-resistance.
[0004] In a first aspect, this utility model provides a heterogeneous trench-gate silicon carbide VDMOS, comprising:
[0005] silicon carbide substrate,
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a groove is provided in the drift layer;
[0007] A shielding area is provided within the groove, and the lower and outer sides of the shielding area are both connected to the drift layer;
[0008] A P-type well region, the lower side of which is connected to the upper side of the drift layer; an N-type source region is provided on the P-type well region;
[0009] An insulating dielectric layer is provided at its lower part within the groove, and the insulating dielectric layer is connected to the upper side and inner side of the shielding area. The outer side of the insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region, respectively. A floating grid is provided within the insulating dielectric layer, and a groove is provided on the insulating dielectric layer. The floating grid is located above the shielding area.
[0010] A gate metal layer is disposed within the trench;
[0011] A source metal layer, wherein the source metal layer is connected to the P-type well region and the N-type source region respectively;
[0012] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0013] The advantages of this utility model are:
[0014] I. The gate metal layer of this utility model increases the gate dielectric thickness from the middle region of the gate to the drain without affecting the characteristics of the gate to the P-type well region of the device, thereby reducing the gate-drain capacitance, reducing the Miller capacitance of the device, and improving the switching speed of the device.
[0015] Second, the gate metal layer reduces the gate-drain capacitance of the device, but it will affect the carrier concentration at the bottom of the insulating medium of the device, and thus affect the on-resistance of the device. Therefore, a floating gate is designed. The floating gate can form electrons under the insulating medium corresponding to the floating gate of the device through the charge effect of the capacitor, thereby reducing the on-resistance of the device.
[0016] Third, the bottom of the masking area and the bottom of the insulating medium are located on the same plane, and the top is located on the same plane as the bottom of the floating gate. This can effectively improve the gate reliability of the device while reducing the difficulty of the process. Attached Figure Description
[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0018] Figure 1 This is a schematic diagram of a heterogeneous trench gate silicon carbide VDMOS according to the present invention.
[0019] Figure 2 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 1 .
[0020] Figure 3 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 2 .
[0021] Figure 4 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 3 .
[0022] Figure 5 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 4 .
[0023] Figure 6 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 5 .
[0024] Figure 7 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 6 .
[0025] Figure 8 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 7 .
[0026] Figure 9 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 8 .
[0027] Figure 10 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 9 .
[0028] Figure 11 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 10 .
[0029] Figure 12 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 10 one.
[0030] Figure 13 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 10 two.
[0031] Figure 14 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 10 three.
[0032] Figure 15 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 10 Four.
[0033] Figure 16 This is a cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS according to the present invention. Figure 10 five. Detailed Implementation
[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0039] like Figure 1 As shown, this application embodiment provides a heterogeneous trench gate silicon carbide VDMOS, including:
[0040] Silicon carbide substrate 1,
[0041] Drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1, and a groove 21 is provided in the drift layer 2;
[0042] The masking area 3 is located in the groove 21, and the lower side and the outer side of the masking area 3 are connected to the drift layer 2.
[0043] P-type well region 4, the lower side of which is connected to the upper side of the drift layer 2; an N-type source region 41 is provided on the P-type well region 4;
[0044] An insulating dielectric layer 5 is provided at its lower part within the groove 21 and is connected to the upper and inner sides of the shielding area 3. The outer side of the insulating dielectric layer 5 is connected to the inner side of the P-type well area 4 and the inner side of the N-type source area 41, respectively. A floating grid 51 is provided inside the insulating dielectric layer 5, and a groove 52 is provided on the insulating dielectric layer 5. The floating grid 51 is located above the shielding area 3.
[0045] A gate metal layer 6 is disposed within the trench 52;
[0046] Source metal layer 7, which is connected to the P-type well region 4 and the N-type source region 41 respectively;
[0047] And a drain metal layer 8, which is connected to the lower side of the silicon carbide substrate 1.
[0048] In this embodiment, preferably, the trench 52 is inverted U-shape, and the lower side of the gate metal layer 6 and the upper side of the floating gate 51 are located on the same plane.
[0049] In this embodiment, preferably, the lower side of the suspended grid 51 and the upper side of the shielding area 3 are located on the same plane.
[0050] In this embodiment, preferably, the thickness of the shielding area 3 is greater than the thickness of the floating grid 51.
[0051] In this embodiment, preferably, the upper side of the suspended grid 51 is lower than the lower side of the P-type trap region 4.
[0052] In this embodiment, preferably, the doping concentration of the masking region 3 is greater than the doping concentration of the drift layer 2.
[0053] like Figures 1 to 16 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:
[0054] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 8; grow epitaxially on the upper side of silicon carbide substrate 1 to form drift layer 2;
[0055] Step 2: Form a barrier layer 9 above the drift layer 2, etch the barrier layer 9 to form a via, and perform ion implantation into the drift layer 2 to form a P-type trap region 4;
[0056] Step 3: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions into the P-type trap region 4 to form the N-type source region 41;
[0057] Step 4: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions into the drift layer 2 to form the masking region 3;
[0058] Step 5: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the masking area 3 to the drift layer, deposit the insulating medium, and form the first insulating medium area 53.
[0059] Step 6: Remove the original blocking layer 9, re-form the blocking layer 9, etch the blocking layer to form a through hole, and etch the drift layer 2 to the upper side of the masking area 3 to form a groove 21;
[0060] Step 7: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, deposit metal, and form a floating gate 51;
[0061] Step 8: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, deposit the insulating medium to form the second insulating medium region 54, the insulating medium layer 5 includes the first insulating medium region 53 and the second insulating medium region 54.
[0062] Step 9: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and etch the insulating dielectric layer 5 to form a first channel 521. Deposit metal to form a first gate metal region 61. Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and etch the insulating dielectric layer 5 to form a second channel 522. Deposit metal to form a second gate metal region 62. The trench 52 includes the first channel 521 and the second channel 522. The gate metal layer 6 includes the first gate metal region 61 and the second gate metal region 62.
[0063] Step 10: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the drift layer 2 to the upper side of the P-type well region 4, deposit metal to form the source metal layer 7, remove the barrier layer 9, and complete the fabrication.
[0064] In another embodiment, the silicon carbide substrate 1 and the drift layer 2 are N-type; the masking region 3 is P-type; and the doping concentration of the silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the drift layer 2 is 1-5e17cm. -3The doping concentration of the P-type well region 4 is 1-5e18cm. -3 The doping concentration of the masking region 3 is 3-6e17cm. -3 The insulating dielectric layer 5 can be made of silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm. -3 The doping concentration of silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device. The doping concentration of drift layer 2 is a trade-off between reverse breakdown voltage and on-resistance. The doping concentration of masking region 3 is to protect the electric field concentration at the gate corner of the device and improve the gate reliability. P-type well region 4 is to form the gate switching characteristics of the device and to form an ohmic contact with the source metal layer, thus constructing the body diode of the device. The concentration of N-type source region 41 is to reduce the source contact resistance of the device and reduce the on-resistance of the device.
[0065] The silicon carbide substrate 1 of the device has a thickness of 1 μm, and the drift layer 2 has a thickness of 30-100 μm, which is adjusted within the above range according to different requirements for the device's breakdown voltage characteristics. The width of the N-type source region 41 is 40-60% of the width of the P-type well region 4; the width of the P-type well region 4 occupies 80-90% of the device cell width, and the device cell width is 100-500 μm. The source metal layer 7 has a thickness of 300 nm, the N-type source region 41 has a thickness of 200 nm, the P-type well region 4 has a thickness of 500 nm, the gate metal layer 6 has a thickness of 850 nm, and the top thickness of the gate metal layer 6 is 20 nm. The thickness of the insulating medium from the top of the inner side of the gate metal layer 6 to the top of the floating gate 51 is 650nm, the thickness of the floating gate 51 is 200nm, the thickness of the masking region 3 is 300nm, and the distance between the outer side of the gate metal layer 6 and the inner side of the P-type well region 4 is 50nm. The gate metal layer 6 of this invention increases the thickness of the insulating medium from the middle region of the gate to the drain without affecting the characteristics of the gate to the P-type well region 4, thereby reducing the gate-drain capacitance, reducing the Miller capacitance, reducing the switching loss, and improving the switching speed of the device.
[0066] The gate metal layer 6 reduces the gate-drain capacitance of the device, but it affects the carrier concentration at the bottom of the insulating medium, which in turn affects the on-resistance of the device. Therefore, a floating gate is designed. The floating gate 51 can form electrons under the insulating medium corresponding to the floating gate 51 through the charge effect of the capacitor, thereby reducing the on-resistance of the device. While increasing the carrier concentration at its bottom, the floating gate 51 can also increase the carrier concentration from the N-type source region 41 to the masking region 3 through the insulating medium on both sides, thereby reducing the on-resistance of the device.
[0067] To improve the reliability of the trench gate of the device, a masking region 3 is designed. The lower side of the masking region 3 is on the same plane as the lower side of the insulating dielectric layer 5, and the upper side of the masking region 3 is on the same plane as the lower side of the floating gate 51. This can effectively improve the gate reliability of the device while reducing the difficulty of the process.
[0068] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A heterogeneous trench-gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a groove is provided in the drift layer; A shielding area is provided within the groove, and the lower and outer sides of the shielding area are both connected to the drift layer; A P-type well region, the lower side of which is connected to the upper side of the drift layer; an N-type source region is provided on the P-type well region; An insulating dielectric layer is provided at its lower part within the groove, and the insulating dielectric layer is connected to the upper side and inner side of the shielding area. The outer side of the insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region, respectively. A floating grid is provided within the insulating dielectric layer, and a groove is provided on the insulating dielectric layer. The floating grid is located above the shielding area. A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P-type well region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The heterogeneous trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The trench is in the shape of an inverted U-shape, and the lower side of the gate metal layer and the upper side of the floating gate are located on the same plane.
3. The heterogeneous trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The lower side of the suspended grid and the upper side of the shielding area are located on the same plane.
4. A heterogeneous trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the shielding area is greater than the thickness of the floating grid.
5. A heterogeneous trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The upper side of the suspended grid is lower than the lower side of the P-type well region.
6. A heterogeneous trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the masking region is greater than that of the drift layer.