Frequency shift keying signal receiving device, road side unit and ETC system

Abstract

The utility model relates to a frequency shift keying signal receiving device, a road side unit and an ETC system. The frequency shift keying signal receiving device comprises an automatic gain control circuit, a phase-locked loop circuit, a frequency mixing circuit, a surface acoustic wave filter circuit, a logarithmic detection circuit and a shaping circuit. The automatic gain control circuit adjusts the 2FSK signal and outputs a first signal; the phase-locked loop circuit generates a local oscillator signal; the frequency mixing circuit performs frequency mixing processing on the first signal and the local oscillator signal and then outputs a second signal; the surface acoustic wave filter circuit filters the second signal to obtain a third signal; the logarithmic detection circuit detects the third signal to obtain a baseband envelope signal; the shaping circuit carries out shaping processing on the baseband envelope signal to obtain a baseband data signal. According to the utility model, discrete components are adopted to replace integrated chips, so that noise can be reduced, signal receiving sensitivity can be improved, and the compatibility problem caused by different chips adopted by different manufacturers can be solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of intelligent transportation, more specifically, to a frequency shift keying signal receiving device, roadside unit and ETC system. BACKGROUND

[0002] The traditional ETC technical system (ETC1.0) supports path identification and entrance and exit consumption, ASK modulation, and low transmission rate of 256kbps-512kbps. The product has a large number of applications in the market. The newly upgraded technology (ETC2.0) adopts 2FSK modulation mode, modulation frequency offset 1MHz, communication rate 4Mbps, supports RSU and OBU to carry out information broadcast, information service, high-order modulation, and high data transmission rate. The product is a new application in the market.

[0003] At present, the RSU supporting ETC2.0 is realized by the integrated scheme of the radio frequency chip at the receiving end, the noise is large, the receiving sensitivity is low, and the chips of different manufacturers on the market cannot be compatible with each other. UTILITY MODEL CONTENT

[0004] The technical problem to be solved by the utility model lies in that, in view of the problems existing in the prior art, a frequency shift keying signal receiving device, roadside unit and ETC system are provided.

[0005] The utility model adopts the technical scheme in the technical solution: a frequency shift keying signal receiving device is constructed, which comprises: an automatic gain control circuit, a phase-locked loop circuit, a mixing circuit, a surface acoustic wave filter circuit, a logarithmic detection circuit and a shaping circuit;

[0006] The mixing circuit is connected with the automatic gain control circuit and the phase-locked loop circuit respectively, the input end of the surface acoustic wave filter circuit is connected with the mixing circuit, and the output end of the surface acoustic wave filter circuit is connected with the logarithmic detection circuit and the shaping circuit in sequence;

[0007] The automatic gain control circuit is used for receiving 2FSK signals and outputting first signals after adjusting the 2FSK signals;

[0008] The phase-locked loop circuit is used for generating a local oscillation signal and sending the local oscillation signal to the mixing circuit;

[0009] The mixing circuit mixes and processes the first signals and the local oscillation signal to output second signals;

[0010] The surface acoustic wave filter circuit filters and processes the second signals to obtain third signals;

[0011] The logarithmic detection circuit detects and processes the third signals to obtain a baseband envelope signal;

[0012] The shaping circuit shapes the baseband envelope signal to obtain a baseband data signal.

[0013] The frequency shift keying signal receiving device further comprises a first amplification circuit.

[0014] The first amplification circuit is arranged between the acoustic surface filtering circuit and the logarithmic detection circuit, and is used for amplifying the third signal.

[0015] The frequency shift keying signal receiving device further comprises a first attenuation circuit and a second attenuation circuit.

[0016] The first attenuation circuit is arranged between the automatic gain control circuit and the mixing circuit, and is used for attenuating the signal output by the automatic gain control circuit.

[0017] The second attenuation circuit is arranged between the phase-locked loop circuit and the mixing circuit, and is used for attenuating the local oscillation signal.

[0018] The frequency shift keying signal receiving device further comprises a low-pass filtering circuit.

[0019] The input end of the low-pass filtering circuit is connected with the output end of the logarithmic detection circuit, and is used for filtering high-frequency components in the baseband envelope signal to obtain a fifth signal.

[0020] The shaping circuit further comprises a second amplification circuit.

[0021] The input end of the second amplification circuit is connected with the output end of the low-pass filtering circuit, and is used for amplifying the fifth signal output by the low-pass filtering circuit to obtain a sixth signal.

[0022] The shaping circuit further comprises a hysteresis comparison circuit.

[0023] The input end of the hysteresis comparison circuit is connected with the output end of the second amplification circuit, and is used for outputting the baseband data signal after processing the sixth signal.

[0024] The shaping circuit further comprises a signal adjustment circuit.

[0025] The signal adjustment circuit is connected with the output end of the hysteresis comparison circuit, and is used for adjusting the baseband data signal.

[0026] The frequency shift keying signal receiving device, the roadside unit and the ETC system of the utility model, including: automatic gain control circuit, phase-locked loop circuit, mixing circuit, sound surface filter circuit, logarithmic detection circuit and shaping circuit;Automatic gain control circuit adjusts 2FSK signal and outputs first signal;Phase-locked loop circuit generates local oscillator signal;Mixing circuit mixes first signal and local oscillator signal and exports second signal;Sound surface filter circuit filters second signal and obtains third signal;Logarithmic detection circuit detects third signal and obtains baseband envelope signal;Shaping circuit shapes baseband envelope signal and obtains baseband data signal.The utility model adopts discrete component to replace integrated chip, can reduce noise, improve the sensitivity of signal reception, and can solve the compatibility problem caused by the different chips of different manufacturers.

[0027] The first pin of the sound surface filter is connected with the output end of the mixing circuit, the fifth pin of the sound surface filter is connected with the first pin of the first processing chip through the sixth capacitor, the third pin of the first processing chip is connected with the first pin of the tenth processing chip in turn through the seventh capacitor, the second resistor and the eighth capacitor, the first end of the fifth resistor is connected with the second end of the seventh capacitor and the first end of the second resistor, the second end of the fifth resistor is grounded, the first end of the sixth resistor is connected with the second end of the second resistor, and the second end of the sixth resistor is grounded, the third pin of the tenth processing chip is connected with the first end of the fourteenth resistor and the first end of the thirteenth capacitor through the thirty-ninth resistor, and the second end of the fourteenth resistor is grounded, the second end of the thirteenth capacitor is connected with the eighth pin of the fourth processing chip, and the fourth pin of the fourth processing chip outputs the baseband envelope signal.

[0028] The utility model also provides a roadside unit, which comprises the frequency shift keying signal receiving device.

[0029] The utility model also provides an ETC system, which comprises the roadside unit.

[0030] The utility model discloses a frequency shift keying signal receiving device, roadside unit and ETC system, including: automatic gain control circuit, phase-locked loop circuit, mixing circuit, sound surface filter circuit, logarithmic detection circuit and shaping circuit;Automatic gain control circuit adjusts 2FSK signal and outputs first signal;Phase-locked loop circuit generates local oscillator signal;Mixing circuit mixes first signal and local oscillator signal and exports second signal;Sound surface filter circuit filters second signal and obtains third signal;Logarithmic detection circuit detects third signal and obtains baseband envelope signal;Shaping circuit shapes baseband envelope signal and obtains baseband data signal.The utility model adopts discrete component to replace integrated chip, can reduce noise, improve the sensitivity of signal reception, and can solve the compatibility problem caused by the different chips of different manufacturers. BRIEF DESCRIPTION OF DRAWINGS

[0031] The utility model will be further described in connection with the drawings and examples, and the drawings show:

[0032] Figure 1It is the principle block diagram of the frequency shift keying signal receiving device provided by the utility model.

[0033] Figures 2 to 5 It is the circuit diagram of the frequency shift keying signal receiving device provided by the utility model.

[0034] Figure 6 It is the signal schematic diagram provided by the utility model. Specific embodiments

[0035] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0036] In order to solve the problems existing in the prior art, the utility model adopts discrete components to build a 2FSK receiving device, that is, a frequency shift keying signal receiving device. Compared with the traditional superheterodyne 2FSK receiving demodulation circuit, the receiving device can realize higher receiving sensitivity and signal quality detection, and there is no compatibility problem.

[0037] Specifically, referring to Figure 1 , Figure 1 It is the principle block diagram of one preferred embodiment of the frequency shift keying signal receiving device provided by the utility model.

[0038] Specifically, as shown in Figure 1 The frequency shift keying signal receiving device comprises an automatic gain control circuit 11, a phase-locked loop circuit 12, a mixing circuit 15, a surface acoustic wave filter circuit 16, a logarithmic detection circuit 18 and a shaping circuit 19. The mixing circuit 15 is connected with the automatic gain control circuit 11 and the phase-locked loop circuit 12 respectively, the input end of the surface acoustic wave filter circuit 16 is connected with the mixing circuit 15, and the output end of the surface acoustic wave filter circuit 16 is connected with the logarithmic detection circuit 18 and the shaping circuit 19 in sequence.

[0039] Automatic gain control circuit 11 receives a 2FSK signal, adjusts it, and outputs a first signal; phase-locked loop circuit 12 generates a local oscillator signal and sends it to mixer circuit 15; mixer circuit 15 mixes the first signal and the local oscillator signal and outputs a second signal; surface acoustic wave (SAW) filter circuit 16 filters the second signal to obtain a third signal; logarithmic detector circuit 18 detects the third signal to obtain a baseband envelope signal; shaping circuit 19 shapes the baseband envelope signal to obtain a baseband data signal. Optionally, in this embodiment, automatic gain control circuit 11 and phase-locked loop circuit 12 are implemented using existing conventional circuits, and this invention does not impose specific limitations.

[0040] The 2FSK signal uses two different frequencies to represent binary data: a higher frequency represents 1, and a lower frequency represents 0. Specifically, the 2FSK signal includes: a carrier frequency of FcMHz, a modulation frequency of ±MHz, a data 1 frequency of Fc+1MHz, and a data 0 frequency of Fc-1MHz. After adjustment by the automatic gain control circuit 11 (AGC circuit), the carrier frequency of the first signal is FcMHz, the data 1 frequency is Fc+1MHz, and the data 0 frequency is Fc-1MHz. The phase-locked loop circuit 12 (PLL circuit) generates a local oscillator signal Lo of Fc±42.5MHz. Figure 6 As shown in this embodiment, the first signal and the local oscillator signal are mixed by the mixing circuit 15 to obtain the second signal (signal 2). This second signal includes the frequency of data 1 (41.5MHz) and the frequency of data 0 (43.5MHz). After the second signal is input to the surface acoustic wave (SAW) filter circuit 16, a third signal is output. The 3dB bandwidth of the SAW filter circuit 16 is 37.7–42.3MHz. At this point, signal 0 is filtered out, and the intermediate frequency (IF) signal of the third signal only contains the frequency of data 1. After the third signal is input to the logarithmic detector circuit 18, a fourth signal (signal 4) is output. This fourth signal is a 4Mbps baseband envelope signal. After being processed by the shaping circuit 19, the baseband envelope signal is restored to the baseband data signal. In this embodiment, the IF signal (i.e., the second signal) output after the mixing circuit 15 is directly input to the SAW filter circuit 16 to filter out low-frequency signals and output the third signal. Then, it passes through the logarithmic detector circuit 18 to output the baseband envelope signal, and finally, the shaping circuit 19 restores the signal to the baseband data signal. Since the demodulated signal is the original baseband signal, there will be no compatibility issues.

[0041] Furthermore, such as Figure 1 As shown, the frequency shift keying signal receiving device further includes: a first amplifier circuit 17; the first amplifier circuit 17 is disposed between the surface acoustic wave filter circuit 16 and the logarithmic detector circuit 18, and is used to amplify the third signal.

[0042] Further, as shown in Figure 1 The frequency shift keying signal receiving device further comprises a first attenuation circuit 13 and a second attenuation circuit 14; the first attenuation circuit 13 is arranged between the automatic gain control circuit 11 and the mixing circuit 15, and is used for attenuating the signal output by the automatic gain control circuit 11; the second attenuation circuit 14 is arranged between the phase-locked loop circuit 12 and the mixing circuit 15, and is used for attenuating the local oscillation signal.

[0043] Optionally, in some embodiments, as shown in Figure 1 The shaping circuit 19 comprises a low-pass filter circuit 191; an input end of the low-pass filter circuit 191 is connected with an output end of the logarithmic detection circuit 18, and is used for filtering high-frequency components in the baseband envelope signal to obtain a fifth signal.

[0044] In some embodiments, as shown in Figure 1 The shaping circuit 19 further comprises a second amplification circuit 192; an input end of the second amplification circuit 192 is connected with an output end of the low-pass filter circuit 191, and is used for amplifying the fifth signal output by the low-pass filter circuit 191 to obtain a sixth signal.

[0045] In some embodiments, as shown in Figure 1 The shaping circuit 19 further comprises a hysteresis comparison circuit 193; an input end of the hysteresis comparison circuit 193 is connected with an output end of the second amplification circuit 192, and is used for outputting a baseband data signal after processing the sixth signal. Through the hysteresis comparison circuit 193, the signal can be prevented from having burrs.

[0046] In some embodiments, as shown in Figure 1 The shaping circuit 19 further comprises a signal adjustment circuit 194; the signal adjustment circuit 194 is connected with an output end of the hysteresis comparison circuit 193, and is used for adjusting the baseband data signal. Through the signal adjustment circuit 194, the signal can be more perfect and have better stability.

[0047] It can be understood that, in other embodiments, if the performance requirement is not high, the second amplification circuit 192 and the hysteresis comparison circuit 193 can be selected alternatively.

[0048] Reference Figure 2 to 5 , Figures 2 to 5 The circuit of one specific example of the utility model is shown.

[0049] As shown in Figure 2 In this embodiment, the first attenuation circuit 13 and the second attenuation circuit 14 are both π attenuation circuits. As shown in Figure 2As shown, the first attenuation circuit 13 comprises a third capacitor C3, a first resistor R1, a third resistor R3, a fourth resistor R4 and a fourth capacitor C4; the second attenuation circuit 14 comprises a tenth capacitor C10, an eleventh capacitor C11, a seventh resistor R7, an eighth resistor R8 and a ninth capacitor. The mixing circuit 15 comprises a mixer U3. The first end of the third capacitor C3 is connected to the AGC circuit through the first connector SMA1, the second end of the third capacitor C3 is connected to the first end of the first resistor R1 and the first end of the third resistor R3, the second end of the third resistor R3 is grounded, the second end of the first resistor R1 is connected to the first end of the fourth resistor R4 and the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is connected to the eighth pin of the mixer U3, and the second end of the fourth resistor R4 is grounded; the first end of the tenth capacitor C10 is connected to the PLL circuit through the second connector SMA2, the second end of the tenth capacitor C10 is connected to the first end of the seventh resistor R7 and the first end of the eighth resistor R8, the second end of the eighth resistor R8 is grounded, the second end of the seventh resistor R7 is connected to the first end of the ninth resistor R9 and the first end of the eleventh capacitor C11, the second end of the eleventh capacitor C11 is connected to the first pin of the mixer U3, and the second end of the ninth resistor R9 is grounded.

[0050] As shown in Figure 2 and Figure 3 , the surface acoustic wave filter circuit 16 comprises a surface acoustic wave filter U2; the first amplification circuit 17 comprises a sixth capacitor C6, a first processing chip U1, a seventh capacitor C7, a second resistor R2, a fifth resistor R5, a sixth resistor R6, an eighth capacitor C8, a tenth processing chip U10 and a thirty-ninth capacitor C39; the logarithmic detection circuit 18 comprises a fourteenth resistor R14, a thirteenth capacitor C13 and a fourth processing chip U4.

[0051] The first pin of the surface acoustic wave filter U2 is connected to the output end of the mixing circuit 15 (as shown in Figure 2 , the first pin of the surface acoustic wave filter U2 is connected to the fifth pin of the mixer U3 through the fifth capacitor C5), the fifth pin of the surface acoustic wave filter U2 is connected to the first pin of the first processing chip U1 through the sixth capacitor C6, the third pin of the first processing chip U1 is connected to the first pin of the tenth processing chip U10 in turn through the seventh capacitor C7, the second resistor R2 and the eighth capacitor C8, the first end of the fifth resistor R5 is connected to the second end of the seventh capacitor C7 and the first end of the second resistor R2, the second end of the fifth resistor R5 is grounded, the first end of the sixth resistor R6 is connected to the second end of the second resistor R2, and the second end of the sixth resistor R6 is grounded; the third pin of the tenth processing chip U10 is connected to the first end of the fourteenth resistor R14 and the first end of the thirteenth capacitor C13 through the thirty-ninth capacitor C39, the second end of the fourteenth resistor R14 is grounded; the second end of the thirteenth capacitor C13 is connected to the eighth pin of the fourth processing chip U4, and the fourth pin of the fourth processing chip U4 outputs the baseband envelope signalFigure 2 (IF1 in the text).

[0052] like Figure 3 As shown, the low-pass filter circuit 191 includes: twelfth inductor L12, thirteenth inductor L13, fourteenth inductor L14, forty-third capacitor C43, forty-fourth capacitor C44, forty-fifth capacitor C45, fifteenth resistor R15, fifteenth capacitor C15, sixteenth resistor R16, seventeenth resistor R17, comparator U5A, eighteenth resistor R18, ninth inductor L9, tenth inductor L10, eleventh inductor L11, fortieth capacitor C40, forty-first capacitor C41, forty-second capacitor C42, twenty-first resistor R21, and comparator U5B. Figure 4 As shown, the hysteresis comparator circuit 193 includes: comparator U7A, the thirty-second resistor R32, and the twenty-seventh resistor R27.

[0053] Among them, the first end of the twelfth inductor L12 is connected to the fourth pin of the fourth processing chip U4, and the second end of the twelfth inductor L12 is connected in sequence to the thirteenth inductor L13, the fourteenth inductor L14, the fifteenth resistor R15, the fifteenth capacitor C15, the sixteenth resistor R16, the seventeenth resistor R17, comparator U5A, the eighteenth resistor R18, the ninth inductor L9, the tenth inductor L10, the eleventh inductor L11, the twenty-first resistor R21, and comparator U5B; the forty-third capacitor C43 is connected to the twelfth inductor L1... 2. The forty-fourth capacitor C44 is connected in parallel with the thirteenth inductor L13, the forty-fifth capacitor C45 is connected in parallel with the fourteenth inductor L14, the fortieth capacitor C40 is connected in parallel with the ninth inductor L9, the forty-first capacitor C41 is connected in parallel with the tenth inductor L10, and the forty-second capacitor C42 is connected in parallel with the eleventh inductor L11. The output of comparator U5B is connected to the negative input of comparator U7A through the thirty-second resistor R32, and the positive input of comparator U7A is connected to the reference signal VRef_1 through the twenty-seventh resistor R27.

[0054] like Figure 5 As shown, the signal adjustment circuit 194 includes: comparator U7B, comparator U8A, comparator U8B, inverter U11B and inverter U11A, and related peripheral devices. For example... Figure 5As shown, the negative input terminal of the comparator U7B is connected with the output terminal of the comparator U7A through the thirtieth resistor R30, the output terminal of the comparator U7B is connected with the positive input terminal of the comparator U8A through the thirty-sixth resistor R36, the output terminal of the comparator U8A is connected with the positive input terminal of the comparator U8B through the twenty-eighth resistor R28, the output terminal of the comparator U8B is connected with the input terminal of the inverter U11B through the twentieth resistor R20 and the fifty-seventh resistor R57 in sequence, the output terminal of the inverter U11B is connected with the input terminal of the inverter U11A through the fifty-fifth resistor R55, and the output terminal of the inverter U11A is connected with the MCU through the connector J1.

[0055] Compared with the traditional integrated chip, the receiving sensitivity of the receiving circuit of the present application can be higher.

[0056] Further, the present application also provides a road side unit, which can comprise the frequency shift keying signal receiving device disclosed by the present application.

[0057] Further, the present application also provides an ETC system, which comprises the road side unit disclosed by the present application.

[0058] The frequency shift keying signal receiving device can be better used in the road side unit (RSU) equipment to realize the receiving demodulation of ETC2.0, solve the compatibility problem caused by different chips used by different manufacturers, improve the receiving sensitivity, and realize the detection of signal quality.

[0059] The above embodiments are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and implement it accordingly, and cannot limit the protection scope of the present application. Any equivalent changes and modifications within the scope of the claims of the present application shall belong to the scope of the claims of the present application.

Claims

1. A frequency shift keying signal receiving apparatus characterized by comprising: The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

2. The frequency shift keying signal receiving apparatus according to claim 1, characterized by The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

3. The frequency shift keying signal receiving apparatus according to claim 1, characterized by The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

4. The frequency shift keying signal receiving apparatus according to claim 1, characterized by The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

5. A frequency shift keying signal receiving apparatus according to claim 4, characterised in that, The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

6. A frequency shift keying signal receiving apparatus according to claim 5, characterised in that, The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

7. A frequency shift keying signal receiving apparatus according to claim 6, characterised in that, The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit.

8. The frequency shift keying signal receiving apparatus according to claim 2, characterized by The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. The application relates to a 2FSK signal processing circuit. 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The application relates to a 2 The first pin of the acoustic surface filter is connected with the output end of the mixing circuit, the fifth pin of the acoustic surface filter is connected with the first pin of the first processing chip through the sixth capacitor, the third pin of the first processing chip is connected with the first pin of the tenth processing chip in turn through the seventh capacitor, the second resistor and the eighth capacitor, the first end of the fifth resistor is connected with the second end of the seventh capacitor and the first end of the second resistor, the second end of the fifth resistor is grounded, the first end of the sixth resistor is connected with the second end of the second resistor, and the second end of the sixth resistor is grounded; the third pin of the tenth processing chip is connected with the first end of the fourteenth resistor and the first end of the thirteenth capacitor through the thirty-ninth capacitor, the second end of the fourteenth resistor is grounded; the second end of the thirteenth capacitor is connected with the eighth pin of the fourth processing chip, and the fourth pin of the fourth processing chip outputs the baseband envelope signal.

9. A roadside unit, comprising: Comprising: A frequency shift keying signal receiving apparatus according to any one of claims 1-8.

10. An ETC system characterised by, A road side unit according to claim 9.

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