Trench gate silicon carbide VDMOS of trench source electrode
By introducing a P-type well region and a low-resistance region structure into silicon carbide VDMOS, the gate breakdown problem of the trench gate is solved, the breakdown voltage of the device and the freewheeling capability of the body diode are improved, and the on-resistance is reduced.
Patent Information
- Application Number
- CN202520455556.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-03-17
AI Technical Summary
Existing silicon carbide VDMOS devices are prone to gate breakdown due to electric field concentration at the trench gate, and the introduction of P-type doping affects the on-resistance of the device and increases the complexity of the device structure.
The structure employs a P-type well region and a low-resistance region. By forming a pn junction in the drift layer and the P-type well region, electric field concentration at the gate corner is avoided. The potential of the P-type well region is reduced by the P-type source region, which increases the contact area of the body diode and reduces the on-resistance.
This improves the gate reliability and body diode freewheeling capability of the device, while reducing the on-resistance and structural complexity of the device.
Smart Images
Figure CN223885548U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of trench gate trench source silicon carbide VDMOS. BACKGROUND
[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, its performance requirements in different fields are different, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss.
[0003] In addition, gate breakdown caused by electric field concentration at the corner of gate insulating medium in trench gate device is prone to occur. There are two general solutions. One is to use P-type shielding region structure to suppress gate breakdown, but this will affect the on-resistance of the device due to the introduction of P-type doping. The other is to use deep trench P-type well region, but due to the high potential of P-type well region, the potential needs to be drawn from the edge of P-type well region, which will increase the complexity of device structure and packaging. SUMMARY
[0004] The technical problem to be solved by the utility model is to provide a trench gate trench source silicon carbide VDMOS, which solves the problem of gate reliability of trench gate and does not need to draw additional electrodes, improves the freewheeling capability of body diode, and reduces the on-resistance of the device.
[0005] In a first aspect, the utility model provides a trench gate trench source silicon carbide VDMOS, which comprises:
[0006] a silicon carbide substrate,
[0007] a drift layer connected to the upper side of the silicon carbide substrate on the lower side; a first protruding part is provided on the upper side of the drift layer, a second protruding part is provided on the first protruding part, and a groove is provided on the second protruding part;
[0008] a low resistance region connected to the upper side of the drift layer on the lower side, and connected to the outer side of the first protruding part on the inner side;
[0009] a P-type well region connected to the upper side of the low resistance region, the upper side of the drift layer, the upper side of the first protruding part, the outer side of the second protruding part and the upper side of the second protruding part; an N-type source region is provided on the P-type well region;
[0010] a P-type source region connected to the P-type well region;
[0011] An insulating medium layer is arranged in the groove, and the outer side of the insulating medium layer is connected with the P-type well region and the N-type source region respectively; a groove is arranged in the insulating medium layer;
[0012] A gate metal layer is arranged in the groove;
[0013] A source metal layer is connected with the P-type source region, the P-type well region and the N-type source region respectively;
[0014] And a drain metal layer is connected with the lower side of the silicon carbide substrate.
[0015] The utility model has the advantages of:
[0016] First, the P-type well region of the utility model can form a pn junction with the drift layer to realize voltage resistance when the device is subjected to a high voltage at the device drain; the space charge region in the pn junction located in the P-type well region is distributed in the direction away from the gate corner of the P-type well region, which can avoid the problem of drain high field breakdown at the gate corner of the device;
[0017] Second, the potential of the P-type well region is lower than the potential of the device gate through the source metal layer when the device is subjected to a drain voltage, which can diffuse the pn junction electric field to the P-type well region on both sides and improve the voltage resistance; the P-type source region is arranged to lower the potential of the P-type well region;
[0018] Third, the P-type source region of the utility model forms a pn junction body diode of the device, which increases the contact area of the body diode and the N-type region and improves the body diode current continuation capability;
[0019] Fourth, the utility model constructs a low resistance region below the P-type well region, which can reduce the resistance at the edge of the device after the device is turned on without affecting the function of the device source, so as to expand the device current to the edge and achieve the purpose of reducing the total on-resistance. BRIEF DESCRIPTION OF DRAWINGS
[0020] The utility model will be further described in combination with the embodiments with reference to the drawings.
[0021] Figure 1 The utility model is a schematic diagram of a trench gate silicon carbide VDMOS with a trench source.
[0022] Figure 2 The utility model is a process cross section of a trench gate silicon carbide VDMOS with a trench source. Figure 1 .
[0023] Figure 3 The utility model is a process cross section of a trench gate silicon carbide VDMOS with a trench source. Figure 2 .
[0024] Figure 4 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 3 .
[0025] Figure 5 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 4 .
[0026] Figure 6 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 5 .
[0027] Figure 7 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 6 .
[0028] Figure 8 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 7 .
[0029] Figure 9 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 8 .
[0030] Figure 10 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 9 .
[0031] Figure 11 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 10 .
[0032] Figure 12 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 10 One.
[0033] Figure 13 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 10 Two.
[0034] Figure 14 For the process section of a trench source trench gate silicon carbide VDMOS of the utility model Figure 10 Three. DETAILED DESCRIPTION
[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0039] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0040] As shown in Figure 1 The embodiment of the present application provides a trench gate silicon carbide VDMOS with a trench source, which comprises:
[0041] a silicon carbide substrate 101,
[0042] a drift layer 102, which is connected to the lower side of the silicon carbide substrate 101; the drift layer 102 is provided with a first protruding part 1021, the first protruding part 1021 is provided with a second protruding part 1022, and the second protruding part 1022 is provided with a groove 10221;
[0043] a low-resistance region 103, which is connected to the upper side of the drift layer 102, and is connected to the outer side of the first protruding part 1021;
[0044] a P-type well region 104, which is connected to the upper side of the low-resistance region 103, the upper side of the drift layer 102, the upper side of the first protruding part 1021, the outer side of the second protruding part 1022 and the upper side of the second protruding part 1022; the P-type well region 104 is provided with an N-type source region 1041;
[0045] a P-type source region 105, which is connected to the P-type well region 104;
[0046] an insulating medium layer 106, which is arranged in the groove 10221, and is connected to the outer side of the P-type well region 104 and the N-type source region 1041; the insulating medium layer 106 is provided with a trench 1061;
[0047] a gate metal layer 107, which is arranged in the trench 1061;
[0048] a source metal layer 108, which is connected to the P-type source region 105, the P-type well region 104 and the N-type source region 1041;
[0049] and a drain metal layer 109 connected to the lower side of the silicon carbide substrate 101.
[0050] In this embodiment, preferably, a first opening (not shown in the figure) is provided on the P-type well region 104, and the P-type source region 105 is arranged in the first opening; a second opening (not shown in the figure) is provided on the P-type source region 105, and the lower part of the source metal layer 108 is arranged in the second opening.
[0051] In this embodiment, preferably, the lower side of the gate metal layer 107 is flush with the upper side of the second protruding part 1022.
[0052] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the low-resistance region 103.
[0053] In this embodiment, preferably, the doping concentration of the P-type well region 104 is less than the doping concentration of the P-type source region 105.
[0054] As shown in Figures 1 to 14 the preparation method of the silicon carbide VDMOS includes the following steps:
[0055] Step 1, depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 109; epitaxially growing on the upper side of the silicon carbide substrate 101 to form a drift layer 102;
[0056] Step 2, forming a barrier layer 110 above the drift layer 102, etching the barrier layer 110 to form a through hole, and performing ion implantation on the drift layer 102 to form a low-resistance region 103 and a first protruding part 1021;
[0057] Step 3, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation on the drift layer 102 to form a first well region 111 and a second protruding part 1022;
[0058] Step 4, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation on the first well region 111 to form a P-type source region 105;
[0059] Step 5, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation on the drift layer 102 to form a second well region 112, and the P-type well region 104 includes the first well region 111 and the second well region 112;
[0060] Step 6, removing the original barrier layer 110, re-forming the barrier layer 110, etching the barrier layer 110 to form a through hole, and performing ion implantation on the second well region 112 to form an N-type source region 1041;
[0061] Step 7, remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, etch the first well region 111 and the drift layer 102, then oxidize to form an insulating medium layer 106, the insulating medium layer 106 is provided with a groove 1061;
[0062] Step 8, remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, and deposit metal to form a gate metal layer 107;
[0063] Step 9, remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, and etch the P-type source region 105, then deposit metal to form a first source metal region 1081;
[0064] Step 10, remove the original barrier layer 110, re-form the barrier layer 110, etch the barrier layer 110 to form a via, and etch the P-type well region 104 and the N-type source region 1041, then deposit metal to form a second source metal region 1082, the source metal layer 108 includes the first source metal region 1081 and the second source metal region 1082, remove the barrier layer 110, and the preparation is completed.
[0065] In another embodiment of the utility model, the silicon carbide substrate 101, the drift layer 102 and the low resistance region 103 are all N type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm -3 The doping concentration of the drift layer 102 is 6-10e16cm -3 The doping concentration of the low resistance region 103 is 1-5e17cm -3 The doping concentration of the P-type well region 104 is 6-10e16cm -3 The doping concentration of the P-type source region 105 is 1-5e19cm -3 The material of the insulating medium layer 106 can be silicon dioxide, and the doping concentration of the N-type source region 1041 is 2-8e18cm -3The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of low resistance ohmic contact with the drain metal layer 109, and to reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse voltage withstand and on-resistance of the device; the doping concentration of the P-type well region 104 is to achieve the voltage withstand of the pn junction structure of the device when the drain of the device is subjected to high voltage; the doping concentration of the P-type source region 105 is to reduce the potential difference between the source metal layer 108 and the P-type well region 104 of the device, and to ensure the low potential of the P-type well region 104 of the device; the doping concentration of the N-type low resistance region 103 is to reduce the resistivity at the edge of the device, to distribute the current of the JFET region of the device to the edge, and to reduce the on-resistance of the device; the doping concentration of the N-type source region 1041 is to reduce the source contact resistance of the device and to reduce the on-resistance of the device;
[0066] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to form low resistance ohmic contact with the drain metal layer 109 and to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 50-100 μm, which is adjusted within the above range according to different requirements for the voltage withstand characteristics of the device; the thickness of the second source metal region 1082 is 300 nm, the thickness of the first source metal region is 1.4 μm, the thickness of the P-type source region 105 located below the first source metal region 1081 is 200 nm, the thickness of the P-type source region 105 located below the second source metal region 1082 is 1.3 μm, and the width is 200 nm; the thickness of the P-type well region 104 located directly below the first source metal region 1081 is 1 μm, the thickness of the P-type well region 104 located below the second source metal region 1082 is 2.3 μm; the thickness of the P-type well region 104 located directly below the N-type source region 1041 is 100 nm, the thickness of the N-type source region 1041 is 200 nm, the width of the N-type source region 1041 of the device is 500 nm, the total width of the P-type well region 104 is 2 μm, the width of the insulating medium layer 106 is 50% of the width of the device structure, the thickness of the gate metal is 600 nm, the thickness of the insulating medium layer 106 at the bottom is 200 nm, the thickness of the N-type low resistance region 103 is 1 μm, and the width is 800 nm-1 μm, which is to avoid the influence of the N-type low resistance region 103 on the P-type well region 104 above it;
[0067] In the embodiment, the source metal layer 108 and the P-type well region 104 of the device are extended to the inside of the device through the groove, when the device drain withstands a high voltage, the N-type drift layer 102 and the P-type well region 104 of the device form a pn junction to realize voltage resistance, and the problem of gate corner breakdown due to high electric field of the drain is avoided; when the device withstands a drain voltage, the potential of the P-type well region 104 of the device needs to be lower than that of the gate of the device, so as to realize the diffusion of the electric field of the pn junction from the vertical direction to the left and right P-type well regions 104, and the first source metal region 1081 is constructed to balance the potential of the P-type well region 104 of the device; in order to reduce the potential of the P-type well region 104, a P-type source region 105 is prepared;
[0068] The P-type source region 105 not only reduces the potential, but also forms a pn junction body diode of the device, increases the contact area of the body diode and the N-type region, and improves the body diode freewheeling capability;
[0069] In the embodiment, the N-type low resistance region 103 is constructed, the resistance at the edge of the device is reduced on the basis of not affecting the function of the source of the device when the device is turned on, so that the current of the device is expanded to the edge, and the purpose of reducing the total on-resistance is realized.
[0070] Although the specific embodiments of the utility model are described above, those skilled in the art should understand that the specific examples described by us are only illustrative, and are not used to limit the scope of the utility model, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the utility model should be covered in the scope of protection of the claims of the utility model.
Claims
1. A trench-gate silicon carbide VDMOS with a trench source, characterized in that: include: silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer is provided with a first protrusion, the first protrusion is provided with a second protrusion, and the second protrusion is provided with a groove; A low-resistivity region, wherein the lower side of the low-resistivity region is connected to the upper side of the drift layer, and the inner side of the low-resistivity region is connected to the outer side of the first protrusion. A P-type well region is provided, which is connected to the upper side of the low-resistivity region, the upper side of the drift layer, the upper side of the first protrusion, the outer side of the second protrusion, and the upper side of the second protrusion; an N-type source region is provided on the P-type well region; A P-type source region, wherein the P-type source region is connected to the P-type well region; An insulating dielectric layer is provided at its lower part within the groove, and the outer surface of the insulating dielectric layer is respectively connected to the P-type well region and the N-type source region; The insulating dielectric layer has grooves inside; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is respectively connected to the P-type source region, the P-type well region and the N-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The trench-gate silicon carbide VDMOS with trench source as described in claim 1, characterized in that: The P-type well region has a first opening, and the P-type source region is disposed within the first opening; the P-type source region has a second opening, and the lower part of the source metal layer is disposed within the second opening.
3. The trench-gate silicon carbide VDMOS with trench source as described in claim 1, characterized in that: The lower side of the gate metal layer is flush with the upper side of the second protrusion.
4. The trench-gate silicon carbide VDMOS with trench source as described in claim 1, characterized in that: The doping concentration of the drift layer is less than that of the low-resistivity region.
5. A trench-gate silicon carbide VDMOS with a trench source as described in claim 1, characterized in that: The doping concentration of the P-type well region is less than that of the P-type source region.