Asymmetric trench gate silicon carbide VDMOS
By optimizing the structure of silicon carbide VDMOS devices through asymmetric trench gate structure design, the problems of high conduction loss of body diode, slow reverse recovery speed and insufficient gate reliability are solved, achieving faster reverse recovery and higher reliability.
Patent Information
- Application Number
- CN202520455559.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-03-17
AI Technical Summary
Existing silicon carbide VDMOS devices suffer from high body diode conduction losses, slow reverse recovery speed, poor gate reliability, and insufficient source maximum current surge reliability in high-power applications.
An asymmetric trench gate structure design is adopted. By setting a masking layer in the trench and making ohmic contact with the source metal layer, a pn junction diode is formed. Schottky diodes are set on both sides of the freewheeling region. The device structure is optimized to reduce the conduction loss of the body diode and improve the reverse recovery speed and gate reliability.
It effectively reduces the body diode conduction loss of the device, improves the reverse recovery speed and gate reliability, and enhances the source maximum current freewheeling capability of the device under extreme conditions.
Smart Images
Figure CN223885549U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of asymmetric trench gate silicon carbide VDMOS. BACKGROUND
[0002] Silicon carbide (SiC) VDMOS (Vertical Double-diffused Metal-oxide-semiconductor Field Effect Transistor) is a typical representative of silicon carbide power devices, and has been widely used in electric vehicles, aerospace, power conversion and other high-tech fields due to its outstanding performance. However, different application scenarios have different performance requirements for silicon carbide power VDMOS, but in general, the core requirements mainly focus on the following aspects:
[0003] 1. Lower on-resistance: In high-power applications such as electric drive systems for electric vehicles and power conversion equipment, the on-resistance of the device directly affects the energy conversion efficiency and system heating. Lower on-resistance can significantly reduce energy loss during conduction, improve overall energy efficiency, and thus extend the cruising range of electric vehicles or reduce the cooling requirements of power conversion equipment.
[0004] 2. Faster switching speed: Fast switching capability is crucial for high-frequency power electronic equipment. In the aerospace field, high-frequency switching power supplies and pulse power systems require fast response and high-precision control to achieve efficient energy distribution and conversion. The fast switching characteristics of silicon carbide VDMOS can effectively reduce switching loss and improve the dynamic performance and power density of the system.
[0005] 3. Higher reliability:
[0006] Gate reliability: In complex working environments such as high temperature, high humidity, and high voltage impact, the reliability of the gate is a key factor affecting the service life of the device. The high thermal stability and chemical stability of silicon carbide material enable its gate structure to remain stable under extreme conditions, thereby extending the service life of the device.
[0007] Drain voltage impact reliability: In power conversion systems, devices may be subjected to voltage spikes and transient impacts. The high voltage withstand capability and fast recovery capability of silicon carbide VDMOS enable it to withstand these impacts, reducing the risk of device damage caused by voltage overshoot.
[0008] 4. Lower body diode conduction loss: In many applications such as electric motor drive for electric vehicles and renewable energy conversion systems, the conduction loss of the body diode directly affects the overall efficiency of the system. Silicon carbide VDMOS effectively reduces the conduction loss of the body diode by optimizing the device structure, while improving the reverse recovery speed, reducing the energy retention and loss in the diode. SUMMARY
[0009] The utility model wants to solve the technical problem, can effectively reduce the body diode conduction loss of device, improve the reverse recovery speed of device, improve the gate reliability and source electrode large current impact reliability of device.
[0010] In a first aspect, the utility model provides a kind of asymmetric trench gate silicon carbide VDMOS, comprising:
[0011] Silicon carbide substrate;
[0012] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0013] Freewheeling area, the lower side of the freewheeling area is connected to the upper side of the drift layer;P-type trap area, N-type source area, masking layer and recess are equipped in the freewheeling area;The lower side of the N-type source area is connected to the upper side of the P-type trap area;The P-type trap area and N-type source area are located in one side of the recess;The masking layer is located below and other side of the recess;
[0014] Insulating medium layer, the lower part of the insulating medium layer is located in the recess, and the lower side of the insulating medium layer is connected to the masking layer;The outer side of the insulating medium layer is connected respectively the N-type source area, P-type trap area and masking layer;Gutter is equipped in the insulating medium layer;
[0015] Gate metal layer, the gate metal layer is located in the gutter;
[0016] Source metal layer, the source metal layer is connected respectively the freewheeling area, N-type source area and masking layer;
[0017] And drain metal layer, the drain metal layer is connected to the silicon carbide substrate.
[0018] The utility model has the advantages that:
[0019] One, the masking layer of the utility model is wrapped in the area below the trench gate insulating medium layer, can effectively improve the gate reliability of device;
[0020] Two, the masking layer of the utility model is also directly connected with source metal layer, and constitutes ohmic contact with source metal layer, and the pn junction formed by it and N-type freewheeling area can effectively increase the area of body pn junction diode of device, effectively improve the freewheeling capacity of device body diode;
[0021] Three, the freewheeling area of the utility model is connected with source metal layer respectively in left and right two sides, and constitutes Schottky diode of source metal layer and freewheeling area, can effectively reduce the body diode conduction voltage drop of device;
[0022] Fourth, the cathode distribution position of the Schottky diode of the utility model is same with the pn junction cathode, but the reverse recovery of the Schottky diode is faster, and the on voltage drop is lower, so the device has the fast recovery characteristic in general condition, and in extreme condition, the device has the large current condition from the source to the drain, and the pn junction diode auxiliary conduction can effectively improve the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS
[0023] The utility model will be further explained in connection with the embodiments with reference to the drawings.
[0024] Figure 1 It is the principle diagram of the utility model of one kind asymmetric trench gate silicon carbide VDMOS.
[0025] Figure 2 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 1 .
[0026] Figure 3 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 2 .
[0027] Figure 4 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 3 .
[0028] Figure 4 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 5 .
[0029] Figure 4 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 5 .
[0030] Figure 6 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 5 .
[0031] Figure 6 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 7 .
[0032] Figure 6 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 7 .
[0033] Figure 8 It is the process cross section of the utility model of one kind asymmetric trench gate silicon carbide VDMOS Figure 7 .
[0034] Figure 8 The utility model discloses a kind of asymmetric trench gate silicon carbide VDMOS's process section view Figure 9 . DETAILED DESCRIPTION
[0035] For the convenience of understanding the present application, the present application will be described more fully below with reference to the attached drawings. The drawings illustrate embodiments of the present application. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.
[0037] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
[0038] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0039] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0040] As shown in FIG. 1, the embodiment of the present application provides a non-symmetrical trench gate silicon carbide VDMOS, which comprises: Figure 8
[0041] a silicon carbide substrate 1;
[0042] a drift layer 2, a lower side of the drift layer 2 being connected to an upper side of the silicon carbide substrate 1;
[0043] a freewheeling region 3, a lower side of the freewheeling region 3 being connected to an upper side of the drift layer 2; the freewheeling region 3 is provided with a P-type well region 31, an N-type source region 32, a mask layer 33 and a groove 34; a lower side of the N-type source region 32 is connected to an upper side of the P-type well region 31; the P-type well region 31 and the N-type source region 32 are located at one side of the groove 34; the mask layer 33 is located below and at the other side of the groove 34;
[0044] an insulating medium layer 4, a lower part of the insulating medium layer 4 being located in the groove 34, a lower side of the insulating medium layer 4 being connected to the mask layer 33; outer sides of the insulating medium layer 4 are connected to the N-type source region 32, the P-type well region 31 and the mask layer 33 respectively; the insulating medium layer 4 is provided with a trench 41;
[0045] a gate metal layer 5, the gate metal layer 5 being located in the trench 41;
[0046] a source metal layer 6, which is connected to the freewheeling region 3, the N-type source region 31 and the masking layer 33 respectively;
[0047] and a drain metal layer 7, which is connected to the silicon carbide substrate 1.
[0048] In this embodiment, preferably, the width of the P-type well region 31 is greater than the width of the N-type source region 32.
[0049] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2 and the freewheeling region 3 are N-type, and the masking layer 33 is P-type.
[0050] In this embodiment, preferably, the upper side of the N-type source region 32, the freewheeling region 3 and the masking layer 33 are located in the same plane.
[0051] In this embodiment, preferably, the doping concentration of the freewheeling region 3 is greater than the doping concentration of the drift layer 2.
[0052] In this embodiment, preferably, the doping concentration of the masking layer 33 is greater than the doping concentration of the freewheeling region 3.
[0053] As shown in Figure 9 Figure 10 Figure 9 Figure 10 Figure 11 Figure 10 Figure 11 Figure 1 Figures 1 to 11 the preparation method of the VDMOS includes the following steps:
[0054] Step 1, depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7, and epitaxially growing on the silicon carbide substrate 1 to form a drift layer 2;
[0055] Step 2, implanting ions into the drift layer 2 to form a freewheeling region 3, and the ion implantation energy is 100-400 kev;
[0056] Step 3, forming a barrier layer 8 on the drift layer 2, etching the barrier layer 8 to form a through hole, and implanting ions to form a masking layer 33, and the ion implantation energy is 100-330 kev;
[0057] Step 4, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and implanting ions to form a P-type well region 31, and the ion implantation energy is 200-300 kev;
[0058] Step 5, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and implanting ions to form an N-type source region 32, and the ion implantation energy is 100-200 kev;
[0059] Step 6, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a via, and etch the drift layer 2 and the masking layer 33 to form a groove 34, and then oxidize to form the insulating medium layer 4;
[0060] Step 7, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a via, and then deposit metal to form the gate metal layer 5;
[0061] Step 8, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a via, etch the drift layer 2 to the upper side of the freewheeling region 3, and then deposit metal to form the source metal layer 6; remove the barrier layer 8, and the preparation is completed.
[0062] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 1 is 2e18cm -3 , the doping concentration of the N-type drift layer 2 is 1e16cm -3 , the doping concentration of the N-type freewheeling region 3 is 1e17cm -3 , the doping concentration of the P-type masking layer 33 is 1e18cm -3 , the doping concentration of the P-type well region 31 is 5e17 cm -3 , and the material of the insulating medium layer 4 can be one or a combination of several of silicon dioxide, aluminum nitride and hafnium dioxide; the doping concentration of the N-type source region 32 is 2e18cm -3 ; the doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 7 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse voltage resistance and the on-resistance of the device; the doping concentration of the N-type freewheeling region 3 is to reduce the on-resistance of the device while forming a Schottky metal with the source metal layer 6 instead of an ohmic contact, thereby constituting a Schottky body diode inside the device; the doping concentration of the P-type masking layer 33 is to suppress the electric field concentration at the gate corner of the device and suppress the impact of the drain voltage surge on the gate of the device; the P-type masking layer 33 forms an ohmic contact with the source metal layer 6, thereby constituting a pn junction body diode inside the device; and the doping concentration of the N-type source region 32 is to form an ohmic contact with the source metal layer 6 and reduce the contact resistance.
[0063] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 15-25 μm, which is adjusted within the above range according to the requirements of the voltage withstand characteristics of the device, the thickness of the N-type freewheeling region 3 below the P-type mask layer 33 is 200 nm, the thickness of the N-type freewheeling region 3 below the P-type well region 31 is 300 nm, and the thickness of the N-type freewheeling region 3 below the source metal layer 6 is 900 nm; the contact surface width of the N-type freewheeling region 3 located on one side of the N-type source region 32 and the source metal layer 6 is 500 nm; the width of the N-type freewheeling region 3 located beside the P-type well region 31 is 100 nm; the contact surface width of the N-type freewheeling region 3 located on one side of the P-type mask layer 33 and the source metal layer 6 is 200 nm, which ensures that the region is a space charge region when a positive voltage is applied to the drain of the device, and ensures the turn-off characteristics of the device; the N-type freewheeling region 3 below the P-type mask layer 33 can effectively shield the capacitive effect of the gate on the drain, reduce the gate-drain charge of the device, improve the switching speed of the device, and at the same time guide the carriers from one side of the device to other regions of the device, avoid current concentration in the device, and reduce the on-resistance of the device; the thickness of the P-type mask layer 33 below the insulating medium layer 4 is 100 nm, which is to protect the gate of the device and inhibit the breakdown problem caused by the electric field concentration at the corner of the gate; the bottom thickness of the insulating medium layer 4 is 50 nm, the thickness of the N-type source region 32 is 300 nm, and the thickness of the P-type well region 31 is 300 nm.
[0064] The P-type mask layer 33 of the device is directly connected with the source metal layer 6, and forms an ohmic contact with the source metal layer 6, and the pn junction formed by the P-type mask layer 33 and the N-type freewheeling region 3 can effectively increase the area of the body pn junction diode of the device and effectively improve the freewheeling capability of the body diode of the device; the N-type freewheeling region 3 of the device is connected with the source metal layer 6 on the left and right sides respectively, and forms a Schottky diode of the source metal layer 6 and the N-type freewheeling region 3, which can effectively reduce the on-voltage drop of the body diode of the device; the cathode distribution position of the Schottky diode of the device is the same as that of the pn junction, but the reverse recovery of the Schottky diode is faster and the on-voltage drop is lower, so the device has the characteristics of fast recovery in general cases, and in extreme cases, the device has a large current condition from the source to the drain, and the pn junction diode assists conduction, which can improve the source current freewheeling capability of the device, and the structure can effectively improve the reliability of the source large current of the device in the off state.
[0065] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.
Claims
1. An asymmetric trench gate silicon carbide VDMOS, characterized in that: Comprise: a silicon carbide substrate; a drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; a freewheeling region, the upper side of which is connected to the lower side of the drift layer; a P-type well region, an N-type source region, a mask layer and a groove are arranged in the freewheeling region; the lower side of the N-type source region is connected to the upper side of the P-type well region; the P-type well region and the N-type source region are located on one side of the groove; the mask layer is located below and on the other side of the groove; an insulating dielectric layer, the lower part of which is arranged in the groove, and the lower side of which is connected to the mask layer; the outer side of the insulating dielectric layer is connected to the N-type source region, the P-type well region and the mask layer respectively; a groove is arranged in the insulating dielectric layer; a gate metal layer, which is arranged in the groove; a source metal layer, which is connected to the freewheeling region, the N-type source region and the mask layer respectively; and a drain metal layer, which is connected to the silicon carbide substrate.
2. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: The width of the P-type well region is greater than the width of the N-type source region.
3. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: The silicon carbide substrate, the drift layer and the freewheeling region are all N-type, and the mask layer is P-type.
4. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: The upper sides of the N-type source region, the freewheeling region and the mask layer are located in the same plane.
5. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: The doping concentration of the freewheeling region is greater than the doping concentration of the drift layer.
6. The asymmetric trench gate silicon carbide VDMOS of claim 1, wherein: The doping concentration of the mask layer is greater than the doping concentration of the freewheeling region.