Surge-voltage-resistant planar gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

Abstract

The utility model provides an anti-surge-voltage planar gate silicon carbide VDMOS. The anti-surge-voltage planar gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; the drift layer is internally provided with a protection region, a current sharing region and a lug boss; the protection area is located below the flow equalizing area and located under the protruding part, and the flow equalizing area is not located under the protruding part. The first P-type well region is connected to the drift layer and the lug boss; an N-type source region is arranged on the first P-type well region; the Schottky region is connected to the drift layer, and the Schottky region is connected to the first P-type well region; a second P-type well region is arranged in the Schottky region, and the lower part of the second P-type well region passes through the drift layer and is connected to the current sharing region; the insulating dielectric layer is respectively connected with the lug boss, the first P-type well region and the N-type source region; the gate metal layer is connected to the insulating dielectric layer; the source metal layer is respectively connected with the N-type source region, the first P-type well region, the second P-type well region and the Schottky region; and the drain metal layer is connected to the silicon carbide substrate, so that the reliability is improved, the conduction loss is reduced, and the surge voltage resistance is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of plane gate silicon carbide VDMOS of anti-surge voltage. BACKGROUND

[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements of device are different in different fields, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss.

[0003] In aerospace and other fields, high reliability becomes the key to restrict application. In aerospace, electric vehicle and other fields, large surge voltage is easy to appear, and in high reliability application scenarios, improving the anti-surge capability of device on the basis of ensuring low on-resistance of device is the key to special application. INVENTION CONTENTS

[0004] The technical problem to be solved by the utility model is to provide a kind of plane gate silicon carbide VDMOS of anti-surge voltage, which is optimized by designing the protection zone, current-sharing zone and parasitic JBS body diode of device, to improve the reliability of device, reduce the conduction loss of device, and improve the anti-surge voltage capability.

[0005] In the first aspect, the utility model provides a kind of plane gate silicon carbide VDMOS of anti-surge voltage, comprising:

[0006] Silicon carbide substrate;

[0007] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;The drift layer is provided with a protection zone, a current-sharing zone and a protruding part;The protection zone is located below the current-sharing zone, and is located directly below the protruding part, and the current-sharing zone is not located directly below the protruding part;

[0008] First P-type well region, the lower side of the first P-type well region is connected to the upper side of the drift layer, and the inner side of the first P-type well region is connected to the outer side of the protruding part;N-type source region is provided on the first P-type well region;

[0009] Schottky region, the lower side of the Schottky region is connected to the upper side of the drift layer, and the inner side of the Schottky region is connected to the outer side of the first P-type well region;Second P-type well region is provided in the Schottky region, and the lower part of the second P-type well region is connected to the upper side of the current-sharing zone through the drift layer;

[0010] An insulating medium layer, the lower side of the insulating medium layer is connected to the upper side of the protruding part, the first P-type well region and the N-type source region respectively;

[0011] A gate metal layer, the gate metal layer is connected to the insulating medium layer;

[0012] A source metal layer, the lower side of the source metal layer is connected to the upper side of the N-type source region, the upper side of the first P-type well region, the upper side of the second P-type well region and the upper side of the Schottky region respectively;

[0013] And a drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate.

[0014] The utility model discloses a kind of anti-surge voltage's plane gate silicon carbide VDMOS, including silicon carbide substrate, the upper side of the silicon carbide substrate is connected to the lower side of the insulating medium layer.

[0015] One, the utility model discloses a protection area, when big surge voltage is borne in the area of protection area, drift layer and protection area form voltage withstanding space charge region, to avoid the impact of drain surge voltage to device gate structure;

[0016] Two, the utility model discloses a current sharing area, the current sharing area is laterally distributed on the left and right sides above protection area, without affecting the surge voltage resistance capability of protection area, while the current of JFET area when device is turned on is redistributed to the left and right sides of P-type protection area, to reduce the on-resistance of device;

[0017] Three, on the basis of constructing JBS body diode inside device, P-type well region is constructed, the bottom of the P-type well region is directly contacted with current sharing area, low resistance path of device parasitic pn junction body diode to device drain is constructed, to reduce the on-loss of device under large current condition. BRIEF DESCRIPTION OF DRAWINGS

[0018] The utility model will be further described below with reference to the drawings in conjunction with embodiments.

[0019] Figure 1 It is the schematic diagram of the utility model one kind anti-surge voltage's plane gate silicon carbide VDMOS.

[0020] Figure 2 It is the process section view of the utility model one kind anti-surge voltage's plane gate silicon carbide VDMOS Figure 1 .

[0021] Figure 3 It is the process section view of the utility model one kind anti-surge voltage's plane gate silicon carbide VDMOS Figure 2 .

[0022] Figure 4 It is the process section view of the utility model one kind anti-surge voltage's plane gate silicon carbide VDMOS Figure 3 .

[0023] Figure 4 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 5 .

[0024] Figure 4 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 5 .

[0025] Figure 6 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 5 .

[0026] Figure 6 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 7 .

[0027] Figure 6 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 7 .

[0028] Figure 8 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 7 .

[0029] Figure 8 For the process section of the anti-surge voltage plane gate silicon carbide VDMOS of the utility model Figure 9 . DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification of the present application herein is only for the purpose of describing specific embodiments and is not intended to limit the present application.

[0032] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0033] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein can be interpreted accordingly.

[0034] The singular form "a", "an", and "the" include plural references unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0035] As shown in FIG. 1, the embodiment of the present application provides a planar gate silicon carbide VDMOS with anti-surge voltage, comprising: Figure 8

[0036] a silicon carbide substrate 1;

[0037] ​A drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a protection region 21, a current spreading region 22 and a protruding part 23 are arranged in the drift layer 2; the protection region 21 is located below the current spreading region 22 and directly below the protruding part 23, and the current spreading region 22 is not located directly below the protruding part 23;

[0038] A first P-type well region 3 is connected to the upper side of the drift layer 2 and connected to the outer side of the protruding part 23; an N-type source region 31 is arranged on the first P-type well region 3;

[0039] A Schottky region 4 is connected to the upper side of the drift layer 2 and connected to the outer side of the first P-type well region 3; a second P-type well region 41 is arranged in the Schottky region 4 and connected to the upper side of the current spreading region 22 through the drift layer 2;

[0040] An insulating medium layer 5 is connected to the upper side of the protruding part 23, the first P-type well region 3 and the N-type source region 31 respectively;

[0041] A gate metal layer 6 is connected to the insulating medium layer 5;

[0042] A source metal layer 7 is connected to the upper side of the N-type source region 31, the upper side of the first P-type well region 3, the upper side of the second P-type well region 41 and the upper side of the Schottky region 4 respectively;

[0043] And a drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0044] Preferably, the sum of the width of the current spreading region 22 and the width of the protection region 21 is equal to the width of the drift layer 2, and the width of the protection region 21 is equal to the width of the protruding part 23.

[0045] Preferably, the upper side of the protection region 21 and the lower side of the current spreading region 22 are located in the same plane.

[0046] Preferably, the thickness of the protection region 21 is 300 nm, and the thickness of the current spreading region 22 is 300 nm.

[0047] Preferably, the silicon carbide substrate 1, the drift layer 2, the current spreading region 22 and the Schottky region 4 are N-type, and the protection region 21 is P-type.

[0048] Preferably, the doping concentration of the protection region 21 is greater than the doping concentration of the drift layer 2; the doping concentration of the protection region 21 is greater than the doping concentration of the current balancing region 22.

[0049] As shown in the figure, the preparation method of the silicon carbide VDMOS includes the following steps: Figure 9 Figure 10 Figure 9 Figure 10 Figure 11 Figure 10 Figure 11 Figure 1 Figures 1 to 11

[0050] Step 1, depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially growing on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0051] Step 2, forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and ion implantation to form a protection region 21;

[0052] Step 3, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form an N-type current balancing region 22;

[0053] Step 4, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a second P-type well region 41;

[0054] Step 5, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a Schottky region 4;

[0055] Step 6, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a first P-type well region 3 and a protruding portion 23;

[0056] Step 7, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form an N-type source region 31;

[0057] Step 8, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and depositing to form an insulating medium layer 5;

[0058] Step 9, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and depositing metal to form a gate metal layer 6;

[0059] Step 10, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing metal to form a source metal layer 7, and removing the barrier layer 9 to complete the preparation.

[0060] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e16cm -3 , and the doping concentration of the P-type protection region 21 is 5-12e17cm​-3 The doping concentration of the N-type current-sharing region 22 is 1-5e17cm -3 The doping concentration of the first P-type well region 3 is 1-5e17cm -3 The doping concentration of the N-type source region 31 is 2-8e18cm -3 The material of the insulating medium layer 5 can be silicon dioxide; the doping concentration of the first P-type well region 3 is less than the doping concentration of the second P-type well region 41;

[0061] The doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 8 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse voltage resistance and the on-resistance of the device; the P-type protection region 21 is to build a P-type buffer region directly below the gate of the device, thereby suppressing the impact of the drain high voltage on the gate structure; the doping concentration of the first P-type well region 3 mainly considers two aspects, one is to protect the gate and source structure of the device, and the doping concentration needs to be high, and the other is to ensure that the gate has a small charge, so the device needs to have a low concentration, therefore, a compromise is made between the two to select the doping concentration; the doping concentration of the N-type current-sharing region 22 is mainly to reduce the on-resistance of the device while not affecting the protection effect of the P-type protection region 21 of the device on the device structure; the N-type source region 31 is to reduce the ohmic contact resistance of the source of the device without damaging the device lattice due to high ion implantation concentration and affecting the stability of the device;

[0062] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 30-100 μm, which is adjusted within the above range according to different requirements for the voltage resistance characteristics of the device, the thickness of the N-type source region 31 is 200 nm, the thickness of the first P-type well region 3 is 500 nm, the thickness of the N-type Schottky region 4 is 500 nm, the thickness of the N-type current-sharing region 22 is 300 nm, the thickness of the P-type protection region 21 is 300 nm, the top of the P-type protection region 21 is flush with the bottom of the N-type current-sharing region 22, the thickness of the insulating medium layer 5 is 50 nm, and the thickness of the source metal layer 7 is 200 nm; in this embodiment, the P-type protection region 21 is designed, a voltage-resistance space charge region is formed in the N-type drift layer 2 and the P-type protection region 21 region when the device drain withstands a large surge voltage, thereby avoiding the impact of the drain surge voltage on the gate structure of the device, the N-type current-sharing region 22 is designed in the device structure, which is distributed laterally on both sides of the P-type protection region 21 and vertically above the P-type protection region 21, so as not to affect the surge voltage resistance of the P-type protection region 21, and the current of the JFET region is redistributed to both sides of the P-type protection region 21 when the device is turned on, thereby reducing the on-resistance of the device;

[0063] On the basis of constructing the JBS body diode inside the device, a second P-type well region 41 is constructed on the left and right sides of the device, the bottom of the second P-type well region 41 directly contacts with the N-type current sharing region 22, a low-resistance path of the device parasitic pn junction body diode to the device drain is constructed, and the conduction loss of the device under the large current condition can be reduced.

[0064] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A planar gate silicon carbide VDMOS resistant to surge voltage, characterized by: The application relates to a silicon carbide substrate, a drift layer connected to the upper side of the silicon carbide substrate, a protection zone, a current equalization zone and a protruding part in the drift layer, the protection zone being below the current equalization zone and directly below the protruding part, the current equalization zone not being directly below the protruding part, a first P-type well region connected to the upper side of the drift layer and the outer side of the protruding part, an N-type source region on the first P-type well region, a Schottky zone connected to the upper side of the drift layer and the outer side of the first P-type well region, a second P-type well region in the Schottky zone and connected to the upper side of the current equalization zone through the drift layer, an insulating medium layer connected to the upper side of the protruding part, the first P-type well region and the N-type source region, a gate metal layer connected to the insulating medium layer, a source metal layer connected to the upper side of the N-type source region, the upper side of the first P-type well region, the upper side of the second P-type well region and the upper side of the Schottky zone, and a drain metal layer connected to the lower side of the silicon carbide substrate. The width of the current equalization zone and the width of the protection zone are equal to the width of the drift layer, and the width of the protection zone is equal to the width of the protruding part. The upper side of the protection zone and the lower side of the current equalization zone are in the same plane. The thickness of the protection zone is 300 nm, and the thickness of the current equalization zone is 300 nm. The silicon carbide substrate, the drift layer, the current equalization zone and the Schottky zone are N-type, and the protection zone is P-type. The doping concentration of the protection zone is greater than the doping concentration of the drift layer, and the doping concentration of the protection zone is greater than the doping concentration of the current equalization zone. ​ ​ ​ ​ ​ 2. A planar gate silicon carbide VDMOS protected against surge voltages as defined in claim 1, characterized in that: ​ 3. A planar gate SiC VDMOS against surge voltage according to claim 1, characterized in that: ​ 4. A planar gate SiC VDMOS against surge voltage according to claim 1, characterized in that: ​ 5. A planar gate SiC VDMOS against surge voltage as claimed in claim 1, wherein: ​ 6. A planar gate SiC VDMOS against surge voltage according to claim 1, characterized in that: ​

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