Left and right shielding trench gate silicon carbide VDMOS
By improving the shielding gate structure of silicon carbide VDMOS, using an insulating dielectric layer to wrap the metal layer and introducing an auxiliary depletion source metal layer, the problems of insufficient on-resistance and switching speed were solved, achieving improved device performance and simplified process.
Patent Information
- Application Number
- CN202520488210.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-03-20
AI Technical Summary
Existing silicon carbide VDMOS devices in the 650-900V range have shortcomings in terms of on-resistance and switching speed, and urgently need improvement.
A left-right shielded trench gate silicon carbide VDMOS was designed. By improving the shielding gate structure, an insulating dielectric layer is used to wrap the first gate metal layer and the second gate metal layer, and a first source metal layer is introduced into the device to help deplete the epitaxial layer impurities, forming a gate-controlled structure-P-type source region-N-type low-resistivity region structure, which simplifies the fabrication process.
This reduces the on-resistance of the device, increases the switching speed, enhances the drain-source breakdown voltage, and simplifies the fabrication process.
Smart Images
Figure CN223885551U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a left and right shielding trench gate silicon carbide VDMOS. BACKGROUND
[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric automobile, aerospace, power conversion and other fields.For silicon carbide power VDMOS, the performance requirements of the device are different in different fields, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short circuit reliability and the like), and lower body diode on-resistance.
[0003] For the silicon carbide VDMOS device in the range of 650-900V, a technical scheme is urgently needed to reduce the on-resistance and improve the switching speed of the silicon carbide VDMOS device in the range of 650-900V. INVENTION CONTENTS
[0004] The technical problem to be solved by the utility model is to provide a left and right shielding trench gate silicon carbide VDMOS, which reduces the on-resistance of the device and simplifies the process difficulty through the design improvement of the shielding gate structure.
[0005] In the first aspect, the utility model provides a left and right shielding trench gate silicon carbide VDMOS, which comprises:
[0006] Silicon carbide substrate;
[0007] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and the upper side of the drift layer is provided with a first groove and a second groove;
[0008] Low resistance zone, the lower side of the low resistance zone is connected to the upper side of the drift layer;
[0009] P-type source area, the lower part of the P-type source area is arranged in the second groove, and the outer side of the P-type source area is connected to the inner side of the low resistance zone;
[0010] P-type well area, the lower side of the P-type well area is connected to the upper side of the drift layer, and the outer side of the P-type well area is connected to the inner side of the P-type source area;
[0011] N-type source area, the lower side of the N-type source area is connected to the upper side of the P-type well area, and the outer side of the N-type source area is connected to the inner side of the P-type source area;
[0012] An insulating medium layer is arranged in the first groove, and the inner side of the insulating medium layer is connected to the inner side of the P-type well region and the inner side of the N-type source region; the insulating medium layer is provided with a first groove, a second groove and a third groove;
[0013] A first gate metal layer is arranged in the first groove;
[0014] A second gate metal layer is arranged in the second groove;
[0015] A first source metal layer is arranged in the third groove;
[0016] A second source metal layer is connected to the low-resistance region, the P-type source region and the N-type source region;
[0017] And a drain metal layer is connected to the lower side of the silicon carbide substrate.
[0018] The utility model discloses the advantages are:
[0019] One, the utility model discloses a first gate metal layer, first source metal layer and second gate metal layer are all wrapped by insulating medium layer, and the depth of first source metal layer is 1.5-3 times of the depth of first gate metal layer, thereby ensuring that the first source metal layer distributed in the middle of first gate metal layer and second gate metal layer can assist the depletion of the impurity of epitaxial layer, thereby can reduce the equivalent concentration of the epitaxial region on the left and right sides close to first source metal layer, avoid the electric field big breakdown problem caused by the high doping concentration of epitaxial region, realize the improvement of epitaxial region doping concentration, reduce the on-resistance of device;
[0020] Two, the utility model discloses a first gate metal layer and second gate metal layer form the gate control structure-P type source region-N type low resistance region structure, and the space charge region of P type source region is expanded, and when the drain withstands high voltage, realizes the protection of the low-doped P type well region and N type low resistance region of device, improves the drain-source withstand voltage capability of device;
[0021] Three, since the gate control structure-P type source region-N type low resistance region structure is adopted, can effectively reduce the P type well region doping concentration, thereby the gate of device when controlling device switch, due to the reduction of inversion layer concentration, can reduce the drive charge, improve the switching speed of device;
[0022] Four, the utility model discloses a first source metal layer and second source metal layer are distributed in the middle and top of device, can directly contact with source electrode, avoids the traditional up and down shielding gate structure, leads to the problem of complex shielding gate source potential lead-out structure, reduces the preparation process complexity. BRIEF DESCRIPTION OF DRAWINGS
[0023] The utility model is further explained below in combination with the embodiments with reference to the drawings.
[0024] Figure 1 It is a schematic diagram of the left-right shielding trench gate silicon carbide VDMOS of the utility model.
[0025] Figure 2 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 1 .
[0026] Figure 3 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 2 .
[0027] Figure 4 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 3 .
[0028] Figure 5 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 4 .
[0029] Figure 6 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 5 .
[0030] Figure 7 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 6 .
[0031] Figure 8 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 7 .
[0032] Figure 9 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 8 .
[0033] Figure 10 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 9 .
[0034] Figure 11 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 10 .
[0035] Figure 12 It is a process cross section of the left-right shielding trench gate silicon carbide VDMOS of the utility model Figure 10 .
[0036] Figure 13 This is a cross-sectional view of the process of a left-right shielded trench gate silicon carbide VDMOS according to the present invention. Figure 10 two.
[0037] Figure 14 This is a cross-sectional view of the process of a left-right shielded trench gate silicon carbide VDMOS according to the present invention. Figure 10 three. Detailed Implementation
[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0041] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is inverted or rotated by 90 degrees, the descriptions of "below" or "under" or "beneath" or "above" or "upper" or "lower" can be interpreted as "above" or "upper" or "above" or "upper" or "above" or "upper" respectively. The term "above" and "below" can include both the orientations as illustrated in the figures and other opposite orientations. The devices can also be oriented in other ways (for example, 90 degrees rotated or other orientations), and the spatially relative terms used herein interpreted accordingly.
[0042] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0043] As shown in the drawings, Figure 1 The embodiment of the present application provides a left-right shielding trench gate silicon carbide VDMOS, which comprises:
[0044] a silicon carbide substrate 101;
[0045] a drift layer 102, a lower side of the drift layer 102 being connected to an upper side of the silicon carbide substrate 101, and a first recess 1021 and a second recess 1022 being arranged on the drift layer 102;
[0046] a low-resistance region 103, an upper side of the low-resistance region 103 being connected to a lower side of the drift layer 102;
[0047] a P-type source region 104, a lower part of the P-type source region 104 being arranged in the second recess 1022, and an outer side of the P-type source region 104 being connected to an inner side of the low-resistance region 103;
[0048] a P-type well region 105, a lower side of the P-type well region 105 being connected to an upper side of the drift layer 102, and an outer side of the P-type well region 105 being connected to an inner side of the P-type source region 104;
[0049] An N-type source region 106 is connected to the upper side of the P-type well region 105 and the inner side of the P-type source region 104;
[0050] An insulating medium layer 107 is arranged in the first recess 1021 and connected to the inner side of the P-type well region 105 and the inner side of the N-type source region 106; the insulating medium layer 107 is provided with a first trench 1071, a second trench 1072 and a third trench 1073;
[0051] A first gate metal layer 108 is arranged in the first trench 1071;
[0052] A second gate metal layer 109 is arranged in the second trench 1072;
[0053] A first source metal layer 110 is arranged in the third trench 1073;
[0054] A second source metal layer 111 is connected to the low-resistance region 103, the P-type source region 104 and the N-type source region 106;
[0055] A drain metal layer 112 is connected to the lower side of the silicon carbide substrate 101.
[0056] Preferably, the lower side of the insulating medium layer 107 is lower than the lower side of the P-type source region 105.
[0057] Preferably, the lower side of the first gate metal layer 108, the lower side of the second gate metal layer 109 and the lower side of the P-type well region 105 are in the same plane.
[0058] Preferably, the depth of the third trench 1073 is greater than the depth of the first trench 1071.
[0059] Preferably, the thickness of the insulating medium layer 107 on the left side of the first gate metal layer 108 is less than the thickness of the insulating medium layer 107 on the right side of the first gate metal layer 108.
[0060] Preferably, the thickness of the insulating medium layer 107 on the left side of the second gate metal layer 109 is greater than the thickness of the insulating medium layer 107 on the right side of the second gate metal layer 109.
[0061] In this embodiment, preferably, the doping concentration of the P-type source region 104 is greater than the doping concentration of the low resistance region 103, and the doping concentration of the low resistance region 103 is greater than the doping concentration of the drift layer 102.
[0062] In this embodiment, preferably, the doping concentration of the P-type source region 104 is greater than the doping concentration of the P-type well region 105, and the doping concentration of the P-type source region 104 is greater than the doping concentration of the N-type source region 106.
[0063] As shown in FIG. 1, the preparation method of the silicon carbide VDMOS includes the following steps: Figures 1 to 14
[0064] Step 1, depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; epitaxially growing on the upper side of the silicon carbide substrate 101 to form a drift layer 102;
[0065] Step 2, forming a barrier layer 113 above the drift layer 102, etching the barrier layer 113 to form a through hole, and ion implantation to form a P-type source region 104;
[0066] Step 3, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and ion implantation to form a low resistance region 103;
[0067] Step 4, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and ion implantation to form a P-type well region 105;
[0068] Step 5, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and ion implantation to form an N-type source region 106;
[0069] Step 6, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, etching the drift layer 102 to form a first recess 1021, and depositing to form an insulating medium layer 107;
[0070] Step 7, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, etching the insulating medium layer 107 to form a first trench 1071 and a second trench 1072, and depositing metal to form a first gate metal layer 108 and a second gate metal layer 109;
[0071] Step 8, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, etching the insulating medium layer 107 to form a third trench 1073, and depositing metal to form a first source metal layer 110;
[0072] Step 9, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a via, and etching the low resistance region 103, the P-type source region 104 and the N-type source region 106, depositing metal to form a second source metal layer 111, removing the barrier layer 113, and completing the preparation.
[0073] In another embodiment of the utility model, the silicon carbide substrate 101, the drift layer 102 and the low resistance region 103 are all N-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm -3 ; the doping concentration of the drift layer 102 is 5-9e17cm -3 ; the doping concentration of the low resistance region 103 is 6-10e17cm -3 ; the doping concentration of the P-type well region 105 is 1-5e16cm -3 ; the doping concentration of the P-type source region 104 is 1-5e19cm -3 ; and the material of the insulating medium layer 107 can be silicon dioxide, and the doping concentration of the N-type source region 106 is 2-8e18cm -3 ; wherein the doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low resistance ohmic contact with the drain metal layer 112 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse voltage resistance and the on-resistance of the device, and since the left and right shielding trench gate structure is designed, the N-type drift layer 102 can increase the doping concentration on the basis of ensuring the voltage resistance and reduce the on-resistance of the device; the doping concentration of the P-type well region 105 is to realize the voltage resistance of the pn junction structure of the device when the drain of the device bears high voltage, and reducing the doping concentration can reduce the gate switching charge and reduce the drive loss; the concentration of the P-type source region 104 is to form a space charge region that diffuses to the N-type drift layer 102 with the N-type drift layer 102 to realize the protection of the P-type well 105 and the gate of the device when the drain bears high voltage, and at the same time, the P-type source region 104 also realizes the ohmic contact with the second source metal layer 111, thereby completing the supplement of the current capacity of the device and improving the current capacity of the device when the parasitic Schottky body diode of the device is insufficient; and the doping concentration of the N-type low resistance region 103 is to form a Schottky contact with the second source metal layer 111, reduce the on-voltage drop of the body diode of the device and ensure the reverse voltage resistance.
[0074] The thickness of the N-type silicon carbide substrate 101 of the device is 500 nm, which is to form a low-resistance ohmic contact with the drain metal layer 112 to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 30-60 μm, which is adjusted within the above range according to different requirements for the voltage withstand characteristics of the device, and the voltage withstand range of the device is 650-900 V; the thickness of the second source metal layer 111 is 200 nm, and the width is 3 μm; the thickness of the first source metal layer 110 is 1.5-3 times the thickness of the first gate metal layer 108, and the thickness of the first source metal layer 110 is 900-1800 nm, and the width is 800 nm; the thickness of the P-type source region 104 is 600 nm, and the width is 2 μm; the thickness of the N-type source region 106 is 100 nm, and the width is 500 nm; the thickness of the P-type well region 105 is 300 nm, and the width is 500 nm; the thickness of the N-type low-resistance region 103 is 400 nm, and the width is 500 nm; the thickness of the first gate metal layer 108 and the second gate metal layer is 600 nm, and the thickness of the insulating medium layer 107 located directly below the first gate metal layer 108 is 150 nm; the width of the insulating medium layer 107 located on one side of the first gate metal layer 108 and the second gate metal layer 109 and close to the P-type well region 105 is 50 nm, and the width of the insulating medium layer 107 away from the P-type well region 105 is 100 nm, and the thickness of the insulating medium layer 107 directly below the first source metal layer 110 is 100 nm, and the width of the first gate metal layer 108 and the second gate metal layer 109 is 300-500 nm.
[0075] Among them, the top of the N-type low-resistance region 103, the P-type source region 104, and the N-type source region 106 is flush with the second source metal layer 111, and the lower side of the N-type low-resistance region 103, the lower side of the P-type well region 105, the lower side of the first gate metal layer 108, and the lower side of the second gate metal layer 109 are flush.
[0076] In this embodiment, the first gate metal layer 108, the first source metal layer 110, and the second gate metal layer 109 are designed to be wrapped by the insulating medium layer 107, wherein the depth of the first source metal layer 110 is 1.5-3 times the depth of the first gate metal layer 108, so as to ensure that the first source metal layer 110 distributed between the first gate metal layer 108 and the second gate metal layer 109 can assist in depleting the impurities of the epitaxial layer, thereby reducing the equivalent concentration of the epitaxial region near the left and right sides of the first source metal layer 110, avoiding the problem of large electric field breakdown caused by high doping concentration of the epitaxial region, and realizing the improvement of the doping concentration of the epitaxial region and the reduction of the on-resistance of the device;
[0077] The first gate metal layer 108 and the second gate metal layer 109 in the embodiment form a gate control structure-P type source region-N type low resistance region structure, and the protection of the low-doped P type well region 105 and the N type low resistance region 103 is realized by the space charge region expansion of the P type source region 104 when the drain bears a large voltage, and the drain-source voltage capacity of the device is improved; since the gate control structure-P type source region-N type low resistance region structure is adopted, the doping concentration of the P type well region 105 can be effectively reduced, so that the driving charge can be reduced and the switching speed of the device can be improved when the device gate controls the switching of the device due to the reduced concentration of the inversion layer; the first source metal layer 110 and the second source metal layer 111 are distributed in the middle and the top of the device, and can be directly contacted with the source electrode, so that the problem of the complex shielding gate source potential lead-out structure caused by the traditional upper and lower shielding gate structure is avoided, and the preparation process complexity is reduced.
[0078] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.
Claims
1. A left and right shielded trench gated silicon carbide VDMOS, characterized in that: The application relates to a silicon carbide substrate, a drift layer connected to the upper side of the silicon carbide substrate, a first recess and a second recess arranged on the upper side of the drift layer, a low-resistance region connected to the upper side of the drift layer, a P-type source region arranged in the second recess, a P-type well region connected to the upper side of the drift layer and the inner side of the P-type source region, an N-type source region connected to the upper side of the P-type well region and the inner side of the P-type source region, an insulating medium layer arranged in the first recess and connected to the inner side of the P-type well region and the inner side of the N-type source region, a first trench, a second trench and a third trench arranged on the insulating medium layer, a first gate metal layer arranged in the first trench, a second gate metal layer arranged in the second trench, a first source metal layer arranged in the third trench, a second source metal layer connected to the low-resistance region, the P-type source region and the N-type source region, and a drain metal layer connected to the lower side of the silicon carbide substrate. The lower side of the insulating medium layer is lower than the lower side of the P-type source region. The lower side of the first gate metal layer, the lower side of the second gate metal layer and the lower side of the P-type well region are in the same plane. The depth of the third trench is greater than the depth of the first trench. The thickness of the insulating medium layer on the left side of the first gate metal layer is less than the thickness of the insulating medium layer on the right side of the first gate metal layer. The thickness of the insulating medium layer on the left side of the second gate metal layer is greater than the thickness of the insulating medium layer on the right side of the second gate metal layer. The doping concentration of the P-type source region is greater than the doping concentration of the low-resistance region, and the doping concentration of the low-resistance region is greater than the doping concentration of the drift layer. The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type source region is greater than the doping concentration of the N-type source region. 2. The left and right shielded trench gate silicon carbide VDMOS of claim 1, wherein: 3. The left and right shielded trench gate silicon carbide VDMOS of claim 1, wherein: 4. The left and right shielded trench gate silicon carbide VDMOS of claim 1, wherein: 5. The left and right shielded trench gate silicon carbide VDMOS of claim 1, wherein: 6. The left and right shielded trench gate silicon carbide VDMOS of claim 1, wherein: 7. The left and right shielded trench gate silicon carbide VDMOS as described in claim 1, characterized in that: 8. The left and right shielded trench gate silicon carbide VDMOS as described in claim 1, characterized in that: