Hybrid discrete device for photovoltaic energy storage

Abstract

The utility model relates to the technical field of photovoltaic energy storage, in particular to a hybrid discrete device for photovoltaic energy storage, which comprises a plurality of hybrid discrete devices, each hybrid discrete device comprises at least one insulated gate bipolar transistor (IGBT) and at least one metal oxide semiconductor (MOS) tube connected with the IGBT, the hybrid discrete devices are connected to form an inverter circuit, and the inverter circuit is connected with the hybrid discrete devices. The MOS tube is controllably conducted based on the first illumination intensity signal and the third current signal, and the IGBT tube is controllably conducted based on the second illumination intensity signal and the third illumination intensity signal. According to the utility model, a mixed single-tube structure is adopted, different characteristics of the IGBT tube and the MOS tube are utilized, more flexible power conversion is realized, a circuit structure of an inversion loop is freely combined based on actual current, different powers are compatible, and a condition that the current in a photovoltaic energy storage system continuously changes can be well adapted.

Description

TECHNICAL FIELD

[0001] The utility model relates to photovoltaic energy storage technical field, concretely relates to a photovoltaic energy storage is with hybrid discrete device's device. BACKGROUND

[0002] The module of the current industry has hybrid insulated gate bipolar transistor (IGBT) and silicon carbide semiconductor field effect transistor (SiC mosfet), and the advantage point is that the integration degree is higher, but the disadvantage is that the design of the whole machine end is relatively single, and the relative cost is higher, since the module is integrated, the internal circuit structure and the connection mode are fixed, and the limitation is large in different power segments, if the large power and the small power are unified and compatible packaging, the module volume will be large, and unnecessary waste will be caused in the small power segment. UTILITY MODEL CONTENTS

[0003] The utility model discloses a photovoltaic energy storage is with hybrid discrete device's device, and solves the above technical problem.

[0004] The technical problem solved by the utility model can be realized by adopting the following technical scheme:

[0005] A photovoltaic energy storage is with hybrid discrete device's device, comprising a plurality of hybrid discrete devices, each hybrid discrete device comprising at least one IGBT tube and at least one MOS tube connected to the IGBT tube, the hybrid discrete devices are connected to form an inverter circuit, the MOS tube is controllably turned on based on a first light intensity signal and a third current signal, and the IGBT tube is controllably turned on based on a second light intensity signal and the third light intensity signal.

[0006] Preferably, the IGBT tubes in the hybrid discrete device are connected in series in the same direction, the MOS tubes in the hybrid discrete device are connected in series in the same direction, the anode end of the antiparallel diode of the IGBT tube at the first end of the hybrid discrete device is connected to the anode end of the body diode of the MOS tube, and the cathode end of the antiparallel diode of the IGBT tube at the second end of the hybrid discrete device is connected to the cathode end of the body diode of the MOS tube.

[0007] The current output value corresponding to the first light intensity signal is less than the current output value corresponding to the second light intensity signal, and the current output value corresponding to the second light intensity signal is less than the current output value corresponding to the third light intensity signal.

[0008] Preferably, the inverter circuit comprises,

[0009] The first level connection branch is provided with a first hybrid discrete part, a first end of the first hybrid discrete part is connected with a connection node, and a second end of the first hybrid discrete part is connected with a first level signal.

[0010] The second level connection branch is provided with a third hybrid discrete part and a second hybrid discrete part, a first end of the third hybrid discrete part is connected with a second level signal, a second end of the second hybrid discrete part is connected with a second end of the third hybrid discrete part, and a first end of the second hybrid discrete part is connected with the connection node.

[0011] The third level connection branch comprises a fourth hybrid discrete part, a first end of the fourth hybrid discrete part is connected with a third level signal, and a second end of the fourth hybrid discrete part is connected with the connection node.

[0012] Preferably, the first hybrid discrete part comprises at least one first hybrid discrete device connected in the same direction in series, the second hybrid discrete part comprises at least one second hybrid discrete device connected in the same direction in series, the third hybrid discrete part comprises at least one third hybrid discrete device connected in the same direction in series, and the fourth hybrid discrete part comprises at least one fourth hybrid discrete device connected in the same direction in series.

[0013] The hybrid discrete devices comprise the first hybrid discrete device, the second hybrid discrete device, the third hybrid discrete device, and the fourth hybrid discrete device.

[0014] Preferably,

[0015] The first hybrid discrete part and the third hybrid discrete part are controllable to conduct in the direction from the first level signal to the second level signal based on a first loop conduction signal;

[0016] The second hybrid discrete part and the fourth hybrid discrete part are controllable to conduct in the direction from the second level signal to the third level signal based on a second loop conduction signal.

[0017] The first hybrid discrete part and the fourth hybrid discrete part are controllable to conduct in the direction from the first level signal to the third level signal based on a third loop conduction signal.

[0018] Preferably, a groove for connecting a mounting card is arranged on a package shell of the hybrid discrete device, the hybrid discrete devices are uniformly distributed on a heat sink, a first end of the mounting card is connected with the groove, and a second end of the mounting card is connected with an upper surface of the heat sink.

[0019] Preferably, the back of the packaging shell is provided with a heat dissipation substrate, the heat dissipation substrate is embedded in the packaging shell, and a heat dissipation surface of the heat dissipation substrate is exposed from the back of the packaging shell and connected with the heat sink.

[0020] Preferably, the heat dissipation substrate is a double-sided copper-clad ceramic substrate, and the thickness of the exposed copper layer of the heat dissipation substrate is less than or equal to the thickness of the built-in copper layer of the heat dissipation substrate.

[0021] Preferably, the single-side edge of the packaging shell is provided with a pin terminal, the pin terminal includes a power pin and a signal pin, the power pin and the signal pin of each hybrid discrete device are located on the same side, the size of the power pin is greater than the size of the signal pin, and the pin terminal is connected with the heat dissipation substrate.

[0022] Preferably, the pin terminal is a multi-bent special-shaped structure, the pin terminal includes a connecting part extending from the side edge of the packaging shell, a pin tip vertically upward, and a plurality of bending parts between the connecting part and the pin tip.

[0023] The beneficial effects of the present application are as follows: by adopting the above technical scheme, the present application adopts a hybrid single-tube structure, utilizes different characteristics of IGBT tubes and MOS tubes, realizes more flexible power conversion, and is compatible with different powers based on a circuit structure of an actual current free combination inverter circuit, and can better adapt to the situation that the current in a photovoltaic energy storage system is constantly changing. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 FIG. 1 is a front view of a hybrid discrete device according to an embodiment of the present application;

[0025] Figure 2 FIG. 2 is a side view of the hybrid discrete device according to the embodiment of the present application;

[0026] Figure 3 FIG. 3 is a back view of the hybrid discrete device according to the embodiment of the present application;

[0027] Figure 4 FIG. 4 is a top view of a device of a hybrid discrete device for photovoltaic energy storage according to an embodiment of the present application;

[0028] Figure 5 FIG. 5 is a structural view of the device of the hybrid discrete device for photovoltaic energy storage according to the embodiment of the present application;

[0029] Figure 6 FIG. 6 is a circuit schematic view of the device of the hybrid discrete device for photovoltaic energy storage according to the embodiment of the present application;

[0030] Figure 7The first loop conducting signal effective small current loop schematic diagram in the embodiment of the utility model;

[0031] Figure 8 The first loop conducting signal effective medium current loop schematic diagram in the embodiment of the utility model;

[0032] Figure 9 The first loop conducting signal effective large current loop schematic diagram in the embodiment of the utility model;

[0033] Figure 10 The second loop conducting signal effective small current loop schematic diagram in the embodiment of the utility model;

[0034] Figure 11 The third loop conducting signal effective small current loop schematic diagram in the embodiment of the utility model. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model, and obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments.

[0036] It should be noted that the embodiments in the utility model and the features in the embodiments can be combined with each other without conflict.

[0037] The utility model will be further described below with reference to the drawings and specific embodiments, but not as the limitation of the utility model.

[0038] A kind of photovoltaic energy storage with hybrid discrete device device, as shown in Figures 1 to 5 It includes several hybrid discrete devices, each hybrid discrete device includes at least one IGBT tube and at least one MOS tube connected with IGBT tube, hybrid discrete device connection constitutes an inverter circuit, MOS tube is controllably turned on based on first light intensity signal and third light intensity signal, IGBT tube is controllably turned on based on second light intensity signal and third light intensity signal.

[0039] Specifically, the utility model adopts hybrid single tube structure, whole machine end can freely combine inverter circuit structure, and small power section can use single or double, and high power end can increase the number of series and parallel to solve.

[0040] In a preferred embodiment, the IGBT tube in the hybrid discrete device is connected in series in the same direction, the MOS tube in the hybrid discrete device is connected in series in the same direction, the anode end of the antiparallel diode of the IGBT tube at the first end of the hybrid discrete device is connected with the anode end of the body diode of the MOS tube, and the cathode end of the antiparallel diode of the IGBT tube at the second end of the hybrid discrete device is connected with the cathode end of the body diode of the MOS tube.

[0041] The current output value corresponding to the first light intensity signal is less than the current output value corresponding to the second light intensity signal, and the current output value corresponding to the second light intensity signal is less than the current output value corresponding to the third light intensity signal.

[0042] Specifically, the internal chip of the hybrid discrete device must contain at least one IGBT and at least one MOS tube, the IGBT tube has a corresponding antiparallel diode, and the Mosfet has a corresponding body diode; further specifically, the internal chip of the hybrid discrete device contains 1-2 IGBTs, 1-2 diodes and 1-2 silicon carbide Mosfets.

[0043] According to different power terminal requirements, multiple chips can be connected into an inverter circuit in the mode of aluminum binding wire, aluminum strip, copper binding wire, copper bar, etc.

[0044] The signal circuits of the IGBT tube and the MOS tube are independent of each other and are distributed on both sides, and the device is turned on and off by controlling the high and low potentials of the external circuit. The power circuits are connected to each other, and the IGBT tube and the MOS tube can use the antiparallel diode during freewheeling, and the connected power circuit can better reduce the loop inductance.

[0045] In a preferred embodiment, the inverter circuit comprises,

[0046] The first level connection branch is provided with a first hybrid discrete part, the first end of the first hybrid discrete part is connected with a connection node N, and the second end of the first hybrid discrete part is connected with a first level signal.

[0047] The second level connection branch is provided with a second hybrid discrete part and a third hybrid discrete part, the first end of the third hybrid discrete part is connected with a second level signal, the second end of the second hybrid discrete part is connected with the second end of the third hybrid discrete part, and the first end of the second hybrid discrete part is connected with the connection node N.

[0048] The third level connection branch comprises a fourth hybrid discrete part, the first end of the fourth hybrid discrete part is connected with a third level signal, and the second end of the fourth hybrid discrete part is connected with the connection node N.

[0049] Specifically, the mixed discrete device is connected to constitute an inverter circuit, the inverter circuit is used for AC-DC conversion, the MOS tube is controllably turned on based on the first light intensity signal and the third light intensity signal, and the IGBT tube is controllably turned on based on the second light intensity signal and the third light intensity signal. According to the characteristics of unstable switching of sunlight intensity in the photovoltaic energy storage system, the effective switching of the IGBT tube and the MOS tube is realized based on the current corresponding to the sunlight intensity, so that the illumination conditions of different intensities are adapted.

[0050] The IGBT tubes in the mixed discrete device are connected in the same direction in series, the MOS tubes are connected in the same direction in series, and the IGBT tube anti-parallel diode and the MOS tube body diode at both ends of the device are connected in a specific manner. The number of IGBT tubes and MOS tubes can be increased or reduced based on actual needs, which helps to share voltage and reduce the voltage stress of a single device, and improves the withstand voltage capacity.

[0051] Specifically, the inverter circuit includes a first level connection branch, a second level connection branch and a third level connection branch. Each branch has a corresponding mixed discrete part, which is composed of series mixed discrete devices and connected to each other through a connection node N. Each mixed discrete part controls the conduction direction based on different circuit conduction signals to realize accurate control of level conversion and realize three-level inverter.

[0052] The utility model makes full use of the characteristics of IGBT tube and MOS tube in mixed discrete device. IGBT has high voltage and large current control ability, and MOS tube has high input impedance and fast switching speed. The utility model uses MOS tube under small current, uses IGBT tube under medium current, and uses both under full current, which can make mixed discrete device play its own advantages under different working conditions and improve overall performance.

[0053] In a preferred embodiment, the first mixed discrete part includes at least one first mixed discrete device 11 connected in the same direction in series, the second mixed discrete part includes at least one second mixed discrete device 12 connected in the same direction in series, the third mixed discrete part includes at least one third mixed discrete device 13 connected in the same direction in series, and the fourth mixed discrete part includes at least one first mixed discrete device 11 connected in the same direction in series.

[0054] The mixed discrete device includes a first mixed discrete device 11, a second mixed discrete device 12, a third mixed discrete device 13 and a fourth mixed discrete device 14.

[0055] Specifically, the inverter circuit includes a first mixed discrete device 11, a second mixed discrete device 12, a third mixed discrete device 13 and a fourth mixed discrete device 14.

[0056] The first hybrid discrete device 11 is a plurality of hybrid discrete devices, the second hybrid discrete device 12 is a plurality of hybrid discrete devices, the third hybrid discrete device 13 is a plurality of hybrid discrete devices, and the fourth hybrid discrete device 14 is a plurality of hybrid discrete devices;

[0057] Each hybrid discrete device further comprises a plurality of IGBT tubes and MOS tubes; the utility model takes the first hybrid discrete device 11 as one hybrid discrete device, the second hybrid discrete device 12 as one hybrid discrete device, the third hybrid discrete device 13 as one hybrid discrete device, and the fourth hybrid discrete device 14 as one hybrid discrete device, and each hybrid discrete device comprises one IGBT tube and MOS tube.

[0058] The power generation circuit diagram is as shown in the figure, Figure 6 In other embodiments, if the number of hybrid discrete devices or the number of IGBT tubes and MOS tubes in the hybrid discrete device is to be increased, the increase can be performed in the same direction in series, for example, D1 can represent a plurality of IGBT tubes in series in the same direction, M1 can represent a plurality of MOS tubes in series in the same direction, and so on.

[0059] The first hybrid discrete device 11 comprises a first IGBT tube Q1, a first MOS tube M1 and a first anti-parallel diode D1, the anode end of the first anti-parallel diode D1 of the first IGBT tube Q1 is connected with the anode end of the body diode of the first MOS tube M1 as a first end connection connection node N of the first hybrid discrete device 11, and the cathode end of the first anti-parallel diode D1 of the first IGBT tube Q1 is connected with the cathode end of the body diode of the first MOS tube M1 as a second end connection first level signal of the first hybrid discrete device 11;

[0060] The second hybrid discrete device 12 comprises a second IGBT tube Q2, a second MOS tube M2 and a second anti-parallel diode D2, the anode end of the second anti-parallel diode D2 of the second IGBT tube Q2 is connected with the anode end of the body diode of the second MOS tube M2 as a first end connection connection node N of the second hybrid discrete device 12, and the cathode end of the second anti-parallel diode D2 of the second IGBT tube Q2 is connected with the cathode end of the body diode of the second MOS tube M2 as a second end of the second hybrid discrete device 12;

[0061] The third hybrid discrete device 13 comprises a third IGBT tube Q3, a third MOS tube M3 and a third anti-parallel diode D3, the anode end of the third anti-parallel diode D3 of the third IGBT tube Q3 is connected with the anode end of the body diode of the third MOS tube M3 as the first end of the third hybrid discrete device 13, the second level signal is connected, the cathode end of the third anti-parallel diode D3 of the third IGBT tube Q3 is connected with the cathode end of the body diode of the third MOS tube M3 as the second end of the third hybrid discrete device 13, and the second end of the second hybrid discrete device 12 is connected;

[0062] The fourth hybrid discrete device 14 comprises a fourth IGBT tube Q4, a fourth MOS tube M4 and a fourth anti-parallel diode D4, the anode end of the fourth anti-parallel diode D4 of the fourth IGBT tube Q4 is connected with the anode end of the body diode of the fourth MOS tube M4 as the first end of the fourth hybrid discrete device 14, the third level signal is connected, the cathode end of the fourth anti-parallel diode D4 of the fourth IGBT tube Q4 is connected with the cathode end of the body diode of the fourth MOS tube M4 as the second end of the fourth hybrid discrete device 14, and the connecting node N is connected.

[0063] Therefore, the utility model at least needs four hybrid discrete devices to form a circuit.

[0064] In photovoltaic applications, the current size is controlled by the light intensity, and cannot have a fixed working mode at all times. When the light intensity is strong, the current output is large, and when the light intensity is weak, the current output is small.

[0065] In this application example, when the current output is small, the MOS tube switch, and the IGBT tube is kept closed, that is, only the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 work.

[0066] Because the internal resistance of the SiC mosfet is small at small current, the MOS tube is more efficient at small current. The parasitic body diode of the MOS tube generally has poor characteristics, and in this application example, the anti-parallel diodes of the IGBT, that is, the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3 and the fourth anti-parallel diode D4, are used for commutation to improve the working efficiency.

[0067] With the increase of sunlight intensity, the current increases, at this time, the IGBT tube switch, MOS tube is closed, that is, only the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, the fourth IGBT tube Q4 are switched on to work, the SiC mosfet resistance increases rapidly with the increase of current, and the IGBT changes little with the current, therefore, when the current increases, the efficiency of using IGBT tube is higher, and the reverse parallel diodes of IGBT are used: the first reverse parallel diode D1, the second reverse parallel diode D2, the third reverse parallel diode D3 and the fourth reverse parallel diode D4 are used for commutation.

[0068] With the increase of sunlight intensity, the current increases, at this time, the IGBT tube switch, MOS tube is closed, that is, only the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3, the fourth IGBT tube Q4 are switched on to work, the SiC mosfet resistance increases rapidly with the increase of current, and the IGBT changes little with the current, therefore, when the current increases, the efficiency of using IGBT tube is higher, and the reverse parallel diodes of IGBT are used: the first reverse parallel diode D1, the second reverse parallel diode D2, the third reverse parallel diode D3 and the fourth reverse parallel diode D4 are used for commutation.

[0069] Further, the first light intensity signal, the second light intensity signal and the third light intensity signal in the utility model all correspond to current values under different light intensities, in the embodiment,

[0070] The current less than 30% of the preset current value is a small current, corresponding to the first light intensity signal, at this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are switched on to work, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 are closed, and the first reverse parallel diode D1, the second reverse parallel diode D2, the third reverse parallel diode D3 and the fourth reverse parallel diode D4 are used for commutation.

[0071] The current between 30% and 70% of the preset current value is a medium current, corresponding to the second light intensity signal, at this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are closed, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 are switched on to work, and the first reverse parallel diode D1, the second reverse parallel diode D2, the third reverse parallel diode D3 and the fourth reverse parallel diode D4 are used for commutation.

[0072] The current greater than 70% of the preset current value is a large current, corresponding to the third light intensity signal, at this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 are all switched on to work, and the working efficiency reaches the maximum value.

[0073] In this application example, four hybrid discrete components are connected in series to form the working circuit. For higher output power, multiple components can be connected in parallel. The components are mounted to the heat sink using a snap-fit ​​method, and the contact surfaces are coated with thermally conductive material to enhance heat dissipation.

[0074] In a preferred embodiment,

[0075] The first hybrid discrete part and the third hybrid discrete part are controllably turned on in the direction from the first level signal to the second level signal based on the first loop conduction signal;

[0076] The second hybrid discrete part and the fourth hybrid discrete part can be controlled to conduct in the direction from the second level signal to the third level signal based on the second loop conduction signal;

[0077] The first hybrid discrete part and the fourth hybrid discrete part can be controlled to conduct in the direction from the first level signal to the third level signal based on the third loop conduction signal.

[0078] More specifically, such as Figure 7 As shown,

[0079] In this embodiment, the inverter circuit is used to perform AC-DC conversion. The inverter circuit of this invention is connected to a first level signal, a second level signal, and a third level signal, wherein the first level signal is a high potential signal, the second level signal is a 0 potential signal, and the third level signal is a low potential signal. The inverter circuit is turned on by sequentially switching the first circuit turn-on signal, the second circuit turn-on signal, and the third circuit turn-on signal.

[0080] Taking the first circuit with the first circuit conduction signal turned on as an example:

[0081] Under the low current state corresponding to the first light intensity signal, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are switched on, the first IGBT Q1, the second IGBT Q2, the third IGBT Q3, and the fourth IGBT Q4 are turned off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3, and the fourth anti-parallel diode D4 are commutated.

[0082] When the first circuit conduction signal is valid, the first MOSFET M1 and the third MOSFET M3 are turned on, while the second MOSFET M2 and the fourth MOSFET M4 are turned off. The current flows through the first MOSFET M1, through the second anti-parallel diode D2 and the body diode of the second MOSFET M2, and then through the third MOSFET M3 to form a circuit.

[0083] like Figure 8 As shown,

[0084] In the medium current state corresponding to the second light intensity signal, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are closed, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 are switched on and off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3 and the fourth anti-parallel diode D4 are commutated.

[0085] When the first loop conduction signal is valid, the first IGBT tube Q1 and the third IGBT tube Q3 are turned on, the second IGBT tube Q2 and the fourth IGBT tube Q4 are turned off, the current passes through the first IGBT tube Q1, the body diode of the second anti-parallel diode D2 and the second MOS tube M2, and forms a loop through the third IGBT tube Q3.

[0086] As shown in Figure 9 ,

[0087] In the large current state corresponding to the third light intensity signal, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 all work.

[0088] When the first loop conduction signal is valid, the first MOS tube M1, the third MOS tube M3, the first IGBT tube Q1 and the third IGBT tube Q3 are turned on, the current passes through the first MOS tube M1 and the first IGBT tube Q1, and forms a loop through the body diode of the second anti-parallel diode D2 and the second MOS tube M2, and flows out from the third MOS tube M3 and the third IGBT tube Q3.

[0089] As shown in Figure 10 ,

[0090] Continuing to take the small current state corresponding to the first light intensity signal as an example, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are switched on and off, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 are closed, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3 and the fourth anti-parallel diode D4 are commutated;

[0091] When the second loop conduction signal is valid, the second MOS tube M2 and the fourth MOS tube M4 are turned on, the first MOS tube M1 and the third MOS tube M3 are turned off, the current forms a loop through the third anti-parallel diode D3 and the body diode of the third MOS tube M3, and flows out after passing through the second MOS tube M2 and the fourth MOS tube M4;

[0092] The current deformation under the second loop conducting signal can refer to the above-mentioned embodiments, which will not be repeated here.

[0093] As Figure 11 shown,

[0094] Continuing to take the small current state corresponding to the first light intensity signal as an example, at this time, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are switched on, the first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 and the fourth IGBT tube Q4 are turned off, and the first anti-parallel diode D1, the second anti-parallel diode D2, the third anti-parallel diode D3 and the fourth anti-parallel diode D4 are commutated.

[0095] When the third loop conducting signal is valid, the first MOS tube M1 and the fourth MOS tube M4 are turned on, the second MOS tube M2 and the third MOS tube M3 are turned off, and the current forms a loop through the first MOS tube M1 and the fourth MOS tube M4.

[0096] In a more preferred embodiment, as Figures 1 to 5 shown, the packaging shell 1 of the hybrid discrete device is provided with a groove 2 for connecting a mounting card 6, the hybrid discrete device is uniformly distributed on a heat sink, the first end of the mounting card 6 is connected to the groove 2, and the second end of the mounting card 6 is connected to the upper surface of the heat sink.

[0097] Specifically, the packaging shell 1 of the utility model is integrally formed by epoxy injection molding, which wraps all the remaining structural components, and the shell contains functions such as insulation, protection of chips, installation of stress, etc.

[0098] At the same time, the integrally formed shell has good insulation performance, which can effectively prevent the internal chips and circuits from electrical short circuit with the external environment, improve the safety of the device, and is especially suitable for the high-voltage and high-current environment of the photovoltaic energy storage system.

[0099] The shell has two grooves 2 for fixing the mounting card 6, and the mounting card 6 is compatible in size with the existing ordinary discrete device mounting card 6. The groove 2 has the advantage that the photovoltaic energy storage whole machine has a higher creepage distance requirement, and the installation groove 2 can increase the creepage distance, thereby eliminating the need for an external safety insulation protection shell.

[0100] Specifically, in the case where the photovoltaic energy storage whole machine has a higher requirement for the creepage distance, the installation groove 2 can increase the creepage distance. The increase of the creepage distance can effectively prevent the surface discharge phenomenon of the insulating medium caused by the excessively high electric field strength, thereby improving the safety of the equipment. In addition, this design eliminates the step of adding an external safety insulation protection shell, simplifies the overall structure, reduces the cost and complexity of the equipment.

[0101] In a preferred embodiment, the back of the package shell 1 is provided with a heat dissipation substrate 4, the heat dissipation substrate 4 is embedded in the package shell 1, the heat dissipation surface of the heat dissipation substrate 4 is exposed from the back of the package shell 1, and the heat dissipation substrate 4 is connected with the heat sink 5.

[0102] Specifically, the insulating heat dissipation substrate 4 generally adopts a ceramic substrate, and a high-thermal-conductivity material ceramic Si3N4 can be used for pursuing good performance, the ceramic substrate is double-sided copper-clad, and the thickness of the copper layer of the exposed surface generally needs to be less than or equal to the thickness of the copper layer of the embedded surface, so as to ensure that the exposed surface does not become concave due to process or structural stress, and thus the heat dissipation problem caused by poor contact with the heat sink 5 is avoided.

[0103] The insulating heat dissipation substrate 4 can be installed with the heat sink 5 after being coated with a thermal conductive silicone grease by using a general heat dissipation mode, and in a large-power scenario, a plurality of solder joints can be used with the heat dissipation substrate 4, and the number of solder joints is not limited, and in this application example, a four-solder-joint mode is used.

[0104] In a preferred embodiment, the heat dissipation substrate 4 is a double-sided copper-clad ceramic substrate, and the thickness of the copper layer of the exposed surface of the heat dissipation substrate 4 is less than or equal to the thickness of the copper layer of the embedded surface of the heat dissipation substrate 4.

[0105] Specifically, the back of the package shell 1 is provided with the heat dissipation substrate 4, the heat dissipation substrate 4 is embedded in the package shell 1, the heat dissipation surface of the heat dissipation substrate 4 is exposed from the back and connected with the heat sink 5. The heat dissipation substrate 4 adopts a double-sided copper-clad ceramic substrate, which has good thermal conductivity. Moreover, the thickness of the copper layer of the exposed surface is less than or equal to the thickness of the copper layer of the embedded surface, so that the exposed surface is prevented from becoming concave due to process or stress problems, and good contact with the heat sink 5 is ensured, thereby ensuring the stability of the heat dissipation effect.

[0106] In a preferred embodiment, the single-side edge of the package shell 1 is provided with a pin terminal 3, the pin terminal 3 includes power pins 32 and signal pins 31, the power pins 32 and the signal pins 31 of each hybrid discrete device are located on the same side, the size of the power pin 32 is greater than the size of the signal pin 31, and the pin terminal 3 is connected with the heat dissipation substrate 4.

[0107] Specifically, the pin terminal 3 in the utility model adopts a multiple bending design, which is different from the single bending of the existing discrete device, and can be quickly installed with a PCB board by welding, and the installation height can be controlled by shortening the length of the pin tip.

[0108] The spacing between the pin terminals 3 is consistent with that of the existing discrete device, and the advantage is that the existing discrete device can be quickly and compatibly designed.

[0109] The single power pin 32 has a size width of 2mm-3mm, and the single signal pin 31 has a size width of 1mm-2mm.

[0110] The pin terminal 3 is connected with the bottom insulating heat dissipation substrate 4 by welding.

[0111] The pin terminal 3 is arranged on one side of the packaging shell 1.

[0112] In a preferred embodiment, the power pin terminal 3 is a multi-bent special-shaped structure, and the pin terminal 3 comprises a connecting part extending from the side of the packaging shell 1, a vertical upward pin tip and a plurality of bent parts between the connecting part and the pin tip.

[0113] Specifically, the single side of the packaging shell 1 is provided with the power pin 32 and the signal pin 31, and all the pins of the mixed discrete devices are on the same side, which facilitates the layout and connection of the circuit.

[0114] The size of the power pin 32 is greater than that of the signal pin 31, which can meet the large current requirement of power transmission and avoid signal interference.

[0115] The power pin 32 and the signal pin 31 are multi-bent special-shaped structures, comprising a connecting part, a pin tip and a bent part, which can facilitate installation and welding.

[0116] The above only describes the preferred embodiments of the present application, and does not limit the implementation and protection scope of the present application. For those skilled in the art, it should be realized that any equivalent replacement and obvious changes made according to the content of the present application should be included in the protection scope of the present application.

Claims

1. A device for hybrid discrete devices for photovoltaic energy storage, characterized in that, The device includes several hybrid discrete devices, each of which includes at least one IGBT and at least one MOSFET connected to the IGBT. The hybrid discrete devices are connected to form an inverter circuit. The MOSFET is controllably turned on based on a first light intensity signal and a third light intensity signal, and the IGBT is controllably turned on based on a second light intensity signal and the third light intensity signal.

2. The apparatus for hybrid discrete devices for photovoltaic energy storage according to claim 1, characterized in that, The IGBT transistors in the hybrid discrete device are connected in series in the same direction, and the MOS transistors in the hybrid discrete device are connected in series in the same direction. The anode of the anti-parallel diode of the IGBT transistor located at the first end of the hybrid discrete device is connected to the anode of the body diode of the MOS transistor. The cathode of the anti-parallel diode of the IGBT transistor located at the second end of the hybrid discrete device is connected to the cathode of the body diode of the MOS transistor. The current output value corresponding to the first light intensity signal is less than the current output value corresponding to the second light intensity signal, and the current output value corresponding to the second light intensity signal is less than the current output value corresponding to the third light intensity signal.

3. The apparatus for hybrid discrete devices for photovoltaic energy storage according to claim 1, characterized in that, The inverter circuit includes, A first-level connection branch is provided, wherein the first-level connection branch is provided with a first hybrid discrete part, the first end of the first hybrid discrete part is connected to a connection node (N), and the second end of the first hybrid discrete part is connected to a first-level signal; The second level connection branch is provided with a third hybrid discrete part and a second hybrid discrete part. The first end of the third hybrid discrete part is connected to the second level signal, and the second end of the second hybrid discrete part is connected to the second end of the third hybrid discrete part. The first end of the second hybrid discrete part is connected to the connection node (N). The third-level connection branch includes a fourth hybrid discrete part, the first end of which is connected to the third-level signal, and the second end of which is connected to the connection node (N).

4. The apparatus for hybrid discrete devices for photovoltaic energy storage according to claim 3, characterized in that, The first hybrid discrete part includes at least one first hybrid discrete device (11) connected in the same direction; the second hybrid discrete part includes at least one second hybrid discrete device (12) connected in the same direction; the third hybrid discrete part includes at least one third hybrid discrete device (13) connected in the same direction; and the fourth hybrid discrete part includes at least one fourth hybrid discrete device (14) connected in the same direction. The hybrid discrete device includes the first hybrid discrete device (11), the second hybrid discrete device (12), the third hybrid discrete device (13), and the fourth hybrid discrete device (14).

5. The apparatus for hybrid discrete devices for photovoltaic energy storage according to claim 3, characterized in that, The first hybrid discrete part and the third hybrid discrete part are controllably turned on in the direction from the first level signal to the second level signal based on the first loop conduction signal; The second hybrid discrete part and the fourth hybrid discrete part are controllably turned on in the direction from the second level signal to the third level signal based on the second loop turn-on signal; The first hybrid discrete part and the fourth hybrid discrete part are controllably turned on in the direction from the first level signal to the third level signal based on the third loop conduction signal.

6. The apparatus for hybrid discrete devices for photovoltaic energy storage according to claim 1, characterized in that, The package housing (1) of the hybrid discrete device is provided with a groove (2) for connecting the mounting card (6). The hybrid discrete device is evenly distributed on a heat sink (5). The first end of the mounting card (6) is connected to the groove (2), and the second end of the mounting card (6) is connected to the upper surface of the heat sink (5).

7. The apparatus for a hybrid discrete device for photovoltaic energy storage according to claim 6, characterized in that, The back of the encapsulation housing (1) is provided with a heat dissipation substrate (4), which is embedded in the encapsulation housing (1). The heat dissipation surface of the heat dissipation substrate (4) is exposed from the back of the encapsulation housing (1) and connected to the heat sink (5).

8. The apparatus for a hybrid discrete device for photovoltaic energy storage according to claim 7, characterized in that, The heat dissipation substrate (4) is a double-sided copper-clad ceramic substrate, and the thickness of the exposed copper layer of the heat dissipation substrate (4) is less than or equal to the thickness of the internal copper layer of the heat dissipation substrate (4).

9. The apparatus for a hybrid discrete device for photovoltaic energy storage according to claim 7, characterized in that, The packaging housing (1) has a pin terminal (3) on one side. The pin terminal (3) includes a power pin (32) and a signal pin (31). The power pin (32) and the signal pin (31) of each of the hybrid discrete devices are located on the same side. The size of the power pin (32) is larger than the size of the signal pin (31). The pin terminal (3) is connected to the heat dissipation substrate (4).

10. The apparatus for a hybrid discrete device for photovoltaic energy storage according to claim 9, characterized in that, The pin terminals (3) are all irregularly shaped structures with multiple bends. The pin terminals (3) include a connecting part extending from the side of the package housing (1), a vertically upward pin tip, and several bends located between the connecting part and the pin tip.

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