Display panel

Abstract

A display panel includes: a substrate layer including a display area and a non-display area adjacent to the display area; a lower electrode on the base layer and overlapping the display area; a driving voltage line on the base layer and overlapping the non-display area; a pixel defining layer on the base layer, covering a portion of the lower electrode, and defining a light emitting opening; a light emitting pattern within the light emitting opening and on the lower electrode; a partition wall on the pixel defining layer and the driving voltage line and defining an upper opening corresponding to the light emitting opening; and an upper electrode on the light emitting pattern and in contact with an inner surface of the partition wall defining the upper opening, in which the driving voltage line is in contact with the partition wall.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2022-0135113, filed on October 19, 2022, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to display panels. Background Technology

[0004] Display devices that provide images to users, such as televisions, monitors, smartphones, and tablet PCs, include display panels that display images. Over the years, various display panels, including liquid crystal display panels, organic light-emitting display panels, electrowetting display panels, and electrophoretic display panels, have been developed.

[0005] The information disclosed in this background section is intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art. Utility Model Content

[0006] An aspect of the embodiments of this disclosure relates to a display panel including a configuration with improved adhesion reliability.

[0007] According to some embodiments of the present disclosure, a display panel is provided, comprising: a substrate layer including a display area and a non-display area adjacent to the display area; a lower electrode on the substrate layer and overlapping the display area; a driving voltage line on the substrate layer and overlapping the non-display area; a pixel defining layer on the substrate layer, covering a portion of the lower electrode and defining a light-emitting opening; a light-emitting pattern within the light-emitting opening and on the lower electrode; a partition wall on the pixel defining layer and the driving voltage line and defining an upper opening corresponding to the light-emitting opening; and an upper electrode on the light-emitting pattern and contacting the inner surface of the partition wall defining the upper opening, wherein the driving voltage line is in contact with the partition wall.

[0008] In some embodiments, the partition wall extends from the boundary between the display area and the non-display area in a direction away from the display area.

[0009] In some embodiments, the upper electrode and the drive voltage line are electrically connected.

[0010] In some embodiments, the partition wall includes: a first conductive layer having a first conductivity; and a second conductive layer having a second conductivity lower than the first conductivity and situated on the first conductive layer.

[0011] In some embodiments, the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

[0012] In some embodiments, the inner surface of the first conductive layer defines a first region of the upper opening, the inner surface of the second conductive layer defines a second region of the upper opening, and in a plan view, the inner surface of the second conductive layer defining the second region is closer to a center of the lower electrode than the inner surface of the first conductive layer defining the first region.

[0013] In some embodiments, the display panel further includes a lower encapsulation inorganic layer on the upper electrode and the partition wall, an encapsulation organic layer on the lower encapsulation inorganic layer, and an upper encapsulation inorganic layer on the encapsulation organic layer, wherein the lower encapsulation inorganic layer is in contact with the inner surface of the first conductive layer and the lower surface of the second conductive layer.

[0014] In some embodiments, the display panel further includes a cap pattern between the upper electrode and the lower encapsulation inorganic layer.

[0015] In some embodiments, the drive voltage line includes a first voltage conductive layer including a first material, a second voltage conductive layer on the first voltage conductive layer and including a second material different from the first material, and a third voltage conductive layer on the second voltage conductive layer and including the first material.

[0016] In some embodiments, the first material has a lower electrical conductivity than the second material.

[0017] In some embodiments, the second voltage conductive layer has a thickness greater than a thickness of the first voltage conductive layer and a thickness of the third voltage conductive layer.

[0018] In some embodiments, the first conductive layer and the second voltage conductive layer include a same material, and the second conductive layer, the first voltage conductive layer, and the third voltage conductive layer include a same material.

[0019] In some embodiments, the drive voltage line includes a first electrode layer and a second electrode layer on the first electrode layer, the second electrode layer being in contact with the partition wall.

[0020] According to some embodiments of the present disclosure, a display panel is provided, including: a substrate layer including a display region and a non-display region adjacent to the display region; a lower electrode on the substrate layer and overlapping the display region; a drive voltage line on the substrate layer and overlapping the non-display region; a pixel definition layer on the substrate layer, covering a portion of the lower electrode and defining a light emitting opening; a light emitting pattern within the light emitting opening and on the lower electrode; a partition wall defining an upper opening corresponding to the light emitting opening; and an upper electrode on the light emitting pattern and in contact with an inner surface of the partition wall defining the upper opening, wherein the partition wall extends from a boundary between the display region and the non-display region in a direction away from the display region and electrically connects the upper electrode and the drive voltage line.

[0021] In some embodiments, the drive voltage line is in contact with the partition wall.

[0022] In some embodiments, the partition wall includes: a first conductive layer having a first conductivity; and a second conductive layer having a second conductivity lower than the first conductivity and on the first conductive layer.

[0023] In some embodiments, an inner surface of the first conductive layer defines a first region of the upper opening, an inner surface of the second conductive layer defines a second region of the upper opening, and in a plan view, the inner surface of the second conductive layer defining the second region is closer to a center of the lower electrode than the inner surface of the first conductive layer defining the first region.

[0024] In some embodiments, the drive voltage line includes: a first voltage conductive layer including a first material; a second voltage conductive layer on the first voltage conductive layer and including a second material different from the first material; and a third voltage conductive layer on the second voltage conductive layer and including the first material, wherein a conductivity of the first material is lower than a conductivity of the second material.

[0025] In some embodiments, the first conductive layer and the second voltage conductive layer include a same material, and the second conductive layer, the first voltage conductive layer, and the third voltage conductive layer include a same material.

[0026] In some embodiments, the drive voltage line includes a first electrode layer and a second electrode layer on the first electrode layer, the second electrode layer being in contact with the partition wall. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent from the detailed description of the embodiments of the present disclosure given below with reference to the accompanying drawings.

[0028] Figure 1A is a perspective view of a display device according to some embodiments of the present disclosure.

[0029] Figure 1B is an exploded perspective view of a display device according to some embodiments of the present disclosure.

[0030] Figure 2 is a cross-sectional view of a display module according to some embodiments of the present disclosure.

[0031] Figure 3 is a plan view of a display panel according to some embodiments of the present disclosure.

[0032] Figure 4 is a circuit diagram of a pixel according to some embodiments of the present disclosure.

[0033] Figure 5 is an enlarged plan view of a portion of a display area of a display panel according to some embodiments of the present disclosure.

[0034] Figure 6 is a cross-sectional view taken alongFigure 3 The cross-sectional view of the display panel taken by line I-I'.

[0035] Figure 7 It is along Figure 3 The cross-sectional view of the display panel taken by line II-II'.

[0036] Figure 8 Is with Figure 7 An enlarged diagram of the area corresponding to area AA'.

[0037] Figure 9 Is with Figure 7 An enlarged diagram of the area corresponding to area AA'. Detailed Implementation

[0038] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout refer to the same elements. However, this disclosure may be embodied in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey to those skilled in the art the aspects and features of this disclosure. Accordingly, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, redundant descriptions are not repeated.

[0039] Unless otherwise specified, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, commonly used terms defined in dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant art, and unless expressly defined herein, these terms shall not be interpreted in an overly idealized or overly formal sense.

[0040] Figure 1A This is a perspective view of a display device DD according to some embodiments of the present disclosure, and Figure 1B This is an exploded perspective view of a display device DD according to some embodiments of the present disclosure.

[0041] In some embodiments, the display device DD may be a large electronic device such as a television, monitor, or external billboard. Alternatively, the display device DD may be a small to medium-sized electronic device such as a personal computer (PC) (e.g., a laptop computer or tablet PC), personal digital terminal, vehicle navigation unit, game console, smartphone, or camera. However, this is illustrative, and other display devices may be used, provided they do not depart from the concept of this disclosure. Figure 1Aand Figure 1B An example is shown in which the display device DD is a smartphone.

[0042] refer to Figure 1A and Figure 1B The display device DD can display an image IM on a display surface FS parallel to the first direction DR1 and the second direction DR2, and on a third direction DR3. The image IM can include still images and moving images. Figure 1A In the image IM, a clock window and icons are shown as an example. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device DD.

[0043] In the current embodiment, the front surface (e.g., upper surface) and rear surface (e.g., lower surface) of each component are defined relative to the direction on which the image IM is displayed (e.g., the third direction DR3 relative to the projection direction of the image IM). The front and rear surfaces may face each other on the third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. The directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be changed to other directions. In this specification, the phrases "when viewed in a plane" and "in a plan view" may refer to the state "when viewed on the third direction DR3".

[0044] refer to Figure 1B The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be connected to each other to form the appearance of the display device DD.

[0045] The window WP may include an optically transparent insulating material. For example, the window WP may include glass and / or plastic. The front surface of the window WP may define the display surface FS of the display device DD. The display surface FS may include a transparent area TA and a border area BZA. The transparent area TA may be an optically transparent area. For example, the transparent area TA may be an area with a visible light transmittance of approximately 90% or greater.

[0046] The border area BZA can be a region with a relatively lower light transmittance than the transparent area TA. The border area BZA can define the shape of the transparent area TA. The border area BZA can be adjacent to and surround the transparent area TA. However, this is illustrative, and the border area BZA of the window WP can be omitted. The window WP can include at least one functional layer selected from a fingerprint prevention layer, a hard coating layer, and a reflection prevention layer, and is not limited to some embodiments.

[0047] The display module DM can be positioned below the window WP. The display module DM can be, for example, the image IM that generates the image (see, for example, [link to image IM]). Figure 1AThe image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized from the outside by the user through the transparent area TA.

[0048] The display surface IS of the display module DM can include a display area DA and a non-display area NDA. The display area DA can be an area activated according to an electrical signal. The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA is an area covered by the bezel area BZA and can not be visually recognized from the outside by the user.

[0049] The housing HAU can be coupled to the window WP. The housing HAU can be coupled to the window WP to provide an internal space (e.g., a set or predetermined internal space). The display module DM can be accommodated in the internal space.

[0050] The housing HAU can include a material having relatively high rigidity. For example, the housing HAU can include a plurality of frames and / or plates made of glass, plastic, metal, or a combination thereof. The housing HAU can stably protect the components of the display device DD accommodated in the internal space from external impacts.

[0051] Figure 2 is a cross-sectional view of a display module DM according to some embodiments of the disclosure.

[0052] Referring to Figure 2 , the display module DM can include a display panel DP and an input sensor INS. The display device DD according to some embodiments of the disclosure (e.g., see Figure 1A ) can further include a protection member disposed on a lower surface of the display panel DP or a reflection prevention member and / or a window member disposed on an upper surface of the input sensor INS.

[0053] The display panel DP can be a light-emitting display panel. However, this is illustrative, and the disclosure is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel can include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel can include quantum dots, quantum rods, and / or micro light-emitting diodes (LEDs), etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0054] The display panel DP can include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE disposed on the base layer BL. The input sensor INS can be directly disposed on the thin film encapsulation layer TFE. In this specification, the expression "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B.

[0055] The base layer BL can include at least one plastic film. The base layer BL is a flexible substrate, and can include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1B The display area DA and the non-display area NDA depicted can be equally defined on the base layer BL.

[0056] The circuit element layer DP-CL can include circuit elements and at least one insulating layer. The insulating layer can include at least one inorganic layer and at least one organic layer. The circuit elements can include signal lines and a driving circuit of a pixel, etc.

[0057] The display element layer DP-OLED can include a partition wall and a light emitting element. The light emitting element can include a lower electrode, a light emitting pattern, and an upper electrode.

[0058] The thin film encapsulation layer TFE can include a plurality of thin films. Some thin films can be arranged to improve optical efficiency, and some thin films can be arranged to protect an organic light emitting diode.

[0059] The input sensor INS acquires coordinate information of an external input. The input sensor INS can have a multi-layer structure. The input sensor INS can include a single-layered conductive layer or a multi-layered conductive layer. In addition, the input sensor INS can include a single-layered insulating layer or a multi-layered insulating layer. The input sensor INS can detect an external input in a capacitive manner. However, this is illustrative, and the present disclosure is not limited thereto. For example, in some embodiments, the input sensor INS can also detect an external input in an electromagnetic induction manner or a pressure sensing manner. In some embodiments of the present disclosure, the input sensor INS can be omitted.

[0060] Figure 3 is a plan view of a display panel DP according to some embodiments of the present disclosure.

[0061] Referring to Figure 3 , a display area DA and a non-display area NDA surrounding the display area DA can be defined in the display panel DP. The display area DA and the non-display area NDA can be distinguished depending on whether a pixel PX is disposed. The pixel PX can be disposed in the display area DA. A scan driving unit SDV, a data driving unit, and a light emitting driving unit EDV can be arranged in the non-display area NDA. The data driving unit can be a part of a circuit included in a driving chip DIC.

[0062] The display panel DP can include the pixels PX, the initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, the black scan lines GBL1 to GBLm, the emission control lines ECL1 to ECLm, the data lines DL1 to DLn, the first control line CSL1 and the second control line CSL2, the driving voltage line PL, and the plurality of pads PD. In this case, “m” and “n” are natural numbers greater than or equal to 2.

[0063] The pixels PX can be connected to the initialization scan lines GIL1 to GILM, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, the black scan lines GBL1 to GBLm, the emission control lines ECL1 to ECLm, and the data lines DL1 to DLn.

[0064] The initialization scan lines GIL1 to GILM, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, and the black scan lines GBL1 to GBLm can extend in the first direction DR1 and can be electrically connected to the scan driving unit SDV. The data lines DL1 to DLn can extend in the second direction DR2 and can be electrically connected to the driving chip DIC. The emission control lines ECL1 to ECLm can extend in the first direction DR1 and can be electrically connected to the emission driving unit EDV.

[0065] The driving voltage line PL can include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 can be disposed in different layers. The driving voltage line PL can provide a driving voltage to the pixels PX.

[0066] The first control line CSL1 can be connected to the scan driving unit SDV. The second control line CSL2 can be connected to the emission driving unit EDV.

[0067] The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 can be electrically connected to the pad PD. The flexible circuit film FCB can be electrically connected to the pad PD through the anisotropic conductive adhesive layer.

[0068] Figure 4 is a circuit diagram of a pixel PXij according to some embodiments of the present disclosure.

[0069] Figure 4 A plurality of pixels PX is exemplarily illustrated (see, for example, Figure 3) a circuit diagram of one of the pixels PXij. Since the plurality of pixels PX have the same circuit structure, detailed description of the other pixels PX will be omitted because there is a description of the circuit structure of the pixel PXij.

[0070] Referring to Figure 3 and Figure 4 , the pixel PXij is connected to an i-th data line DLi among the data lines DL1 to DLn, a j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, a j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, a j-th write scan line GWLj among the write scan lines GWL1 to GWLm, a j-th black scan line GBLj among the black scan lines GBL1 to GBLm, a j-th emission control line ECLj among the emission control lines ECL1 to ECLm, a first drive voltage line VL1 and a second drive voltage line VL2, and a first initialization voltage line VL3 and a second initialization voltage line VL4. Here, i is an integer greater than or equal to 1 and less than or equal to n, and j is an integer greater than or equal to 1 and less than or equal to m.

[0071] The pixel PXij includes an emission element ED and a pixel circuit PDC. The emission element ED can be a light emitting diode. As an example of the present disclosure, the emission element ED can be an organic light emitting diode including an organic emission layer, but the present disclosure is not particularly limited thereto. The pixel circuit PDC can control an amount of current flowing in the emission element ED in response to an i-th data signal Di. The emission element ED can emit light having a luminance (e.g., a set or predetermined luminance) corresponding to the amount of current supplied from the pixel circuit PDC.

[0072] The pixel circuit PDC can include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and first to third capacitors Cst, Cbst, and Nbst. According to the present disclosure, the configuration of the pixel circuit PDC is not limited to the embodiment shown in Figure 4 . The pixel circuit PDC shown in Figure 4 is merely an example, and the configuration of the pixel circuit PDC can be modified and implemented in an appropriate manner.

[0073] At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be a transistor having a low temperature polysilicon (LTPS) semiconductor layer. At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 can be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be LTPS transistors.

[0074] In some embodiments, the first transistor T1 that directly affects the luminance of the light-emitting element ED includes a highly reliable polysilicon semiconductor layer, and thus, a high-resolution display device can be implemented. Because the oxide semiconductor has a high carrier mobility and a low leakage current, the voltage drop is not large even when the driving time is long. That is, because the color change of an image due to the voltage drop during low-frequency driving is not large, low-frequency driving can be performed. In this way, because the oxide semiconductor has a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be implemented as an oxide semiconductor transistor, and thus, the leakage current that can flow to the gate electrode of the first transistor T1 can be prevented or substantially reduced and the power consumption can be reduced at the same time.

[0075] Some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be P-type transistors, and the other of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, and the third transistor T3 and the fourth transistor T4 can be N-type transistors.

[0076] The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 4 some embodiments shown in FIG. 1. Figure 4 The pixel circuit PDC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PDC can be modified and implemented in an appropriate manner. For example, all of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be P-type transistors or N-type transistors. In some examples, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be N-type transistors.

[0077] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth light-emitting control line ECLj can transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth light-emitting control signal EMj, respectively, to the pixel PXij. The ith data line DLi can transmit the ith data signal Di to the pixel PXij. The ith data signal Di can have a voltage level corresponding to an image signal input to the display device DD (see, for example, Figure 1A ).

[0078] The first driving voltage line VL1 and the second driving voltage line VL2 can transmit a first driving voltage ELVDD and a second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first initialization voltage line VL3 and the second initialization voltage line VL4 can transmit a first initialization voltage VINT and a second initialization voltage VAINT to the pixel PXij, respectively.

[0079] The first transistor T1 is connected between the first driving voltage line VL1 that receives the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode connected to a pixel electrode (e.g., an anode) of the light emitting element ED via the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted through the i-th data line DLi according to a switching operation of the second transistor T2, and can supply a driving current to the light emitting element ED.

[0080] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on according to the j-th write scan signal GWj transmitted through the j-th write scan line GWLj, and can transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst can be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst can be connected to the first node N1.

[0081] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 can be turned on according to the j-th compensation scan signal GCj transmitted through the j-th compensation scan line GCLj, can connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other, and thus, can diode-connect the first transistor T1. One end of the third capacitor Nbst can be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst can be connected to the first node N1.

[0082] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is applied, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 can be turned on according to the jth initialization scan signal GIj transmitted through the jth initialization scan line GILj. The turned-on fourth transistor T4 can transmit the first initialization voltage VINT to the first node N1, and can initialize the potential (e.g., voltage) of the third electrode of the first transistor T1 (i.e., the potential or voltage of the first node N1).

[0083] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the jth emission control line ECLj.

[0084] The fifth transistor T5 and the sixth transistor T6 can be simultaneously (e.g., concurrently) turned on according to the jth emission signal EMj transmitted through the jth emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 can be compensated through the diode-connected first transistor T1, and then can be transmitted to the light emitting element ED through the sixth transistor T6.

[0085] The seventh transistor T7 includes a first electrode connected to the second initialization voltage line VL4 to which the second initialization voltage VAINT is applied, a second electrode connected to the second electrode (e.g., the second node N2) of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the jth black scan line GBLj. The second initialization voltage VAINT can have a voltage level lower than or equal to a voltage level of the first initialization voltage VINT.

[0086] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. The opposite electrode (e.g., cathode) of the light emitting element ED can be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. The second driving voltage ELVSS can have a voltage level lower than a voltage level of the first driving voltage ELVDD.

[0087] Figure 5 is a plan view of a portion of a display area DA of a display panel DP according to some embodiments of the disclosure. Figure 6 is a cross-sectional view of the display panel DP taken along a line I-I’. Figure 3 Figure 5 illustrates a flat surface of the display module DM (see, for example, Figure 1B ) when viewed from a display surface IS (see, for example, Figure 1B ) and illustrates an arrangement of the light emitting areas PXA-R, PXA-G, and PXA-B.

[0088] Referring to Figure 5 and Figure 6 , the display area DA can include first to third light emitting areas PXA-R, PXA-G, and PXA-B and a non-light emitting area NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, and PXA-B. The display panel DP can include first, second, and third light emitting elements. In Figure 6 , a structure of the light emitting element ED is representatively illustrated, and structures of the first to third light emitting elements can be substantially the same as the structure of the light emitting element ED.

[0089] The first light emitting element can include a first lower electrode LE1, a first light emitting pattern, and a first upper electrode. The second light emitting element can include a second lower electrode LE2, a second light emitting pattern, and a second upper electrode. The third light emitting element can include a third lower electrode LE3, a third light emitting pattern, and a third upper electrode. In some embodiments, the first light emitting pattern can provide red light (R), the second light emitting pattern can provide green light (G), and the third light emitting pattern can provide blue light (B).

[0090] Referring to Figure 5 , the first to third light emitting areas PXA-R, PXA-G, and PXA-B can respectively correspond to areas from which light provided from the first to third light emitting elements is emitted. In Figure 5 , for ease of description, only the first to third lower electrodes LE1, LE2, and LE3 among components of the first to third light emitting elements are illustrated as examples. The first to third light emitting areas PXA-R, PXA-G, and PXA-B can be classified according to colors of light emitted toward the outside of the display module DM (see, for example, Figure 1B ).

[0091] The first to third light emitting areas PXA-R, PXA-G, and PXA-B can respectively provide first to third color light having different colors. For example, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. However, examples of the first to third color light are not necessarily limited to the above-described examples. ​

[0092] The first light emitting area PXA-R can be defined as an area exposed through a light emitting opening OP1-E on the upper surface of the first lower electrode LE1. The second light emitting area PXA-G can be defined as an area exposed through a light emitting opening OP2-E on the upper surface of the second lower electrode LE2. The third light emitting area PXA-B can be defined as an area exposed through a light emitting opening OP3-E on the upper surface of the third lower electrode LE3. The light emitting openings OP1-E, OP2-E, and OP3-E can be defined in a pixel defining layer ISL (see, for example, FIG. 1B) that covers a portion of the lower electrodes LE1, LE2, and LE3, the detailed description of which will be made below. Figure 6 ).

[0093] The non-light emitting area NPXA can set boundaries between the first to third light emitting areas PXA-R, PXA-G, and PXA-B, and can prevent or substantially reduce color mixing between the first to third light emitting areas PXA-R, PXA-G, and PXA-B.

[0094] As shown in Figure 5 , each of the first to third light emitting areas PXA-R, PXA-G, and PXA-B can be provided in plural, and can be repeatedly arranged in a set or predetermined pattern within the display area DA. For example, the first light emitting areas PXA-R and the third light emitting areas PXA-B can be alternately arranged in the first direction DR1 to constitute a "first group". The second light emitting areas PXA-G can be arranged in the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" can be provided in plural, and the "first group" and the "second group" can be alternately arranged in the second direction DR2.

[0095] One second light emitting area PXA-G can be spaced apart from one first light emitting area PXA-R or one third light emitting area PXA-B in a fourth direction DR4. The fourth direction DR4 can be defined as a direction crossing (e.g., diagonally crossing) the first direction DR1 and the second direction DR2.

[0096] Although Figure 5 an example of a specific arrangement of the first to third light emitting areas PXA-R, PXA-G, and PXA-B is shown, the present disclosure is not limited thereto, and the first to third light emitting areas PXA-R, PXA-G, and PXA-B can be arranged in various appropriate forms. For example, the first to third light emitting areas PXA-R, PXA-G, and PXA-B can have a honeycomb arrangement as shown in Figure 5 , or can have a stripe arrangement or a diamond arrangement, etc.

[0097] The first to third light emitting areas PXA-R, PXA-G, and PXA-B can have various shapes in a planar surface (for example, in a plan view). The first to third light emitting areas PXA-R, PXA-G, and PXA-B can each have, for example, a polygonal shape, a circular shape, or an elliptical shape. Figure 5 An example in which the first light emitting area PXA-R and the third light emitting area PXA-B have a quadrangular shape (or a lozenge shape) in a planar surface, and the second light emitting area PXA-G has an octagonal shape is shown.

[0098] The first to third light emitting areas PXA-R, PXA-G, and PXA-B can have the same shape in a planar surface (for example, can have the same shape in a plan view), or can have shapes that are at least partially different. Figure 5 An example in which the first light emitting area PXA-R and the third light emitting area PXA-B have the same shape in a planar surface, and the second light emitting area PXA-G has a shape different from that of the first light emitting area PXA-R and the third light emitting area PXA-B is shown.

[0099] At least some of the first to third light emitting areas PXA-R, PXA-G, and PXA-B can have different areas in a planar surface. In some embodiments, the area of the first light emitting area PXA-R that emits red light can be greater than the area of the second light emitting area PXA-G that emits green light, and can be less than the area of the third light emitting area PXA-B that emits blue light. However, the size relationship between the areas of the first to third light emitting areas PXA-R, PXA-G, and PXA-B according to the color of the light emitted is not limited thereto, and can vary as appropriate depending on the design of the display module DM (for example, see Figure 1B ). Furthermore, the present disclosure is not limited thereto, and the first to third light emitting areas PXA-R, PXA-G, and PXA-B can also have the same area in a planar surface (for example, can also have the same area in a plan view).

[0100] The shapes, areas, and arrangements, etc. of the first to third light emitting areas PXA-R, PXA-G, and PXA-B of the display module DM (for example, see Figure 1B ) of the present disclosure can be designed in an appropriate manner differently according to the color of the light emitted or the size and configuration of the display module DM (for example, see Figure 1B ), and are not limited to some embodiments shown in Figure 5 .

[0101] The connection contact holes CNT-R, CNT-G, and CNT-B can include a first connection contact hole CNT-R, a second connection contact hole CNT-G, and a third connection contact hole CNT-B. The first through third lower electrodes LE1, LE2, and LE3 can be connected to pixel circuits PDC (see, e.g., FIG. 2) inside the circuit element layer DP-CL (see, e.g., FIG. 2) through the first through third connection contact holes CNT-R, CNT-G, and CNT-B. For example, the first lower electrode LE1 can be connected to a pixel circuit corresponding to the first lower electrode LE1 through the first connection contact hole CNT-R, the second lower electrode LE2 can be connected to a pixel circuit corresponding to the second lower electrode LE2 through the second connection contact hole CNT-G, and the third lower electrode LE3 can be connected to a pixel circuit corresponding to the third lower electrode LE3 through the third connection contact hole CNT-B. Figure 2 ) inside the circuit element layer DP-CL (see, e.g., FIG. 2). For example, the first lower electrode LE1 can be connected to a pixel circuit corresponding to the first lower electrode LE1 through the first connection contact hole CNT-R, the second lower electrode LE2 can be connected to a pixel circuit corresponding to the second lower electrode LE2 through the second connection contact hole CNT-G, and the third lower electrode LE3 can be connected to a pixel circuit corresponding to the third lower electrode LE3 through the third connection contact hole CNT-B. Figure 4 ) inside the circuit element layer DP-CL (see, e.g., FIG. 2). For example, the first lower electrode LE1 can be connected to a pixel circuit corresponding to the first lower electrode LE1 through the first connection contact hole CNT-R, the second lower electrode LE2 can be connected to a pixel circuit corresponding to the second lower electrode LE2 through the second connection contact hole CNT-G, and the third lower electrode LE3 can be connected to a pixel circuit corresponding to the third lower electrode LE3 through the third connection contact hole CNT-B.

[0102] The first through third connection contact holes CNT-R, CNT-G, and CNT-B can be spaced apart from the first through third light emitting areas PXA-R, PXA-G, and PXA-B defined in the first through third lower electrodes LE1, LE2, and LE3, respectively. However, this is illustrative, and the first through third connection contact holes CNT-R, CNT-G, and CNT-B can overlap the first through third light emitting areas PXA-R, PXA-G, and PXA-B defined in the first through third lower electrodes LE1, LE2, and LE3, respectively.

[0103] Referring to Figure 6 , the display panel DP can include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. Figure 6 The descriptions of the base layer BL, the circuit element layer DP-CL, the display element layer DP-OLED, and the thin film encapsulation layer TFE of FIG. 1 can be the same as or substantially the same as those provided with reference to Figure 2 . Thus, for the sake of brevity, the descriptions of elements having the same reference numerals can not be repeated here.

[0104] The display panel DP can include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and a plurality of signal lines, etc. The insulating layers, the semiconductor layers, and the conductive layers are formed by a coating process or a deposition process, etc. Thereafter, the insulating layers, the semiconductor layers, and the conductive layers can be selectively patterned by a photolithography process or an etching process. In this way, the semiconductor patterns, the conductive patterns, and the signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED can be formed.

[0105] The circuit element layer DP-CL can be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission area SCL, first to fifth insulating layers 10, 20, 30, 40 and 50, an electrode EE, and multiple connecting electrodes CNE1 and CNE2.

[0106] A buffer layer (BFL) can be disposed on the substrate layer (BL). The buffer layer (BFL) can improve the bonding force between the substrate layer (BL) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be stacked alternately.

[0107] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, this disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide, etc. Figure 6 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern can be further arranged in multiple light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern can be arranged in a specific manner across multiple light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern can have different electrical characteristics depending on whether the semiconductor pattern is doped. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with N-type or P-type dopant. A P-type transistor may include a first region doped with P-type dopant.

[0108] The conductivity of the first region can be greater than that of the second region, and the first region can essentially be used as an electrode or signal line. The second region can essentially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor, another portion of the semiconductor pattern can be the source or drain of a transistor, and yet another portion of the semiconductor pattern can be a conductive region.

[0109] like Figure 6 As shown, the source S1, active region A1, and drain D1 of transistor TR1 can be formed by semiconductor patterns. Furthermore, Figure 6 A portion of the signal transmission region SCL, formed by a semiconductor pattern, is shown. In the planar view, the signal transmission region SCL can be connected to the drain D1 of transistor TR1.

[0110] The first to fifth insulating layers 10, 20, 30, 40 and 50 can be arranged on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40 and 50 can be inorganic layers or organic layers.

[0111] A first insulating layer 10 can be disposed on the buffer layer BFL. A gate G1 can be disposed on the first insulating layer 10. A second insulating layer 20 can be disposed on the first insulating layer 10 to cover the gate G1. An electrode EE can be disposed on the second insulating layer 20. A third insulating layer 30 can be disposed on the second insulating layer 20 to cover the electrode EE.

[0112] A first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal transmission area SCL through a contact hole CNT-1 passing through the first to third insulating layers 10 to 30. A fourth insulating layer 40 can be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. In some examples, the fourth insulating layer 40 can be an organic layer.

[0113] A second connection electrode CNE2 can be disposed on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. A fifth insulating layer 50 can be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. In some examples, the fifth insulating layer 50 can be an organic layer.

[0114] A display element layer DP-OLED can be disposed on the circuit element layer DP-CL. The display element layer DP-OLED can include light emitting elements ED, a sacrificial pattern SP, a pixel definition layer ISL, a partition wall CPW, and a dummy pattern DMP.

[0115] The light emitting element ED can include a lower electrode LE, a light emitting pattern EP, and an upper electrode UE. The first to third light emitting elements can each include substantially the same configuration of the light emitting element ED. That is, the description regarding the lower electrode LE, the light emitting pattern EP, and the upper electrode UE can be equally applied to all of the lower electrodes, the light emitting patterns, and the upper electrodes of the first to third light emitting elements. Figure 6

[0116] The lower electrode LE can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The lower electrode LE can be a transmissive electrode, a semi-transparent electrode, or a reflective electrode. The lower electrode LE can be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined by passing through the fifth insulating layer 50. Accordingly, the lower electrode LE can be electrically connected to the signal transmission area SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus to the corresponding circuit element.

[0117] ​The sacrifice pattern SP can be disposed on an upper surface of the lower electrode LE. A portion of the upper surface of the lower electrode LE, through which the lower opening OP-L is exposed, can be defined in the sacrifice pattern SP. In some examples, the sacrifice pattern SP can include an amorphous transparent conductive oxide. According to the present disclosure, in a process of etching the sacrifice pattern SP to form the lower opening OP-L, the lower electrode LE can be prevented from being damaged due to etching, or damage to the lower electrode LE can be substantially reduced.

[0118] The pixel-defining layer ISL can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel-defining layer ISL can cover a portion of the lower electrode LE and the sacrifice pattern SP. The light-emitting opening OP-E can be defined in the pixel-defining layer ISL. The light-emitting opening OP-E can correspond to the lower opening OP-L of the sacrifice pattern SP.

[0119] In a plan view, the light-emitting opening OP-E can overlap the lower opening OP-L, and an area of the light-emitting opening OP-E can be smaller than an area of the lower opening OP-L. For example, in a plan view, an entirety of the light-emitting opening OP-E can overlap the lower opening OP-L, and the two openings can have a common center. That is, in a plan view, an inner surface of the pixel-defining layer ISL that defines the light-emitting opening OP-E can be closer to a center of the lower electrode LE than an inner surface of the sacrifice pattern SP that defines the lower opening OP-L. A portion of the pixel-defining layer ISL that is closer to the center of the lower electrode LE than the inner surface of the sacrifice pattern SP that defines the lower opening OP-L in a plan view can be defined as a tip portion of the pixel-defining layer ISL.

[0120] In some examples, the pixel-defining layer ISL can include an inorganic insulating material. For example, the pixel-defining layer ISL can include silicon nitride (SiN x ), etc. The pixel-defining layer ISL can be disposed between the lower electrode LE and the partition wall CPW, and can block (e.g., prevent or substantially prevent) an electrical connection between the lower electrode LE and the partition wall CPW. That is, the pixel-defining layer ISL can facilitate electrically isolating the lower electrode LE and the partition wall CPW.

[0121] The partition wall CPW can be disposed on the pixel-defining layer ISL. The upper opening OP-U can be defined in the partition wall CPW. The upper opening OP-U can correspond to the light-emitting opening OP-E.

[0122] The barrier wall CPW can include a first conductive layer CDL1 and a second conductive layer CDL2. The first conductive layer CDL1 can be disposed on the pixel definition layer ISL, and the second conductive layer CDL2 can be disposed on the first conductive layer CDL1. The first conductive layer CDL1 can have a first conductivity, and the second conductive layer CDL2 can have a second conductivity lower than the first conductivity. A thickness of the first conductive layer CDL1 can be greater than a thickness of the second conductive layer CDL2. An etching rate of the first conductive layer CDL1 can be greater than an etching rate of the second conductive layer CDL2. That is, the first conductive layer CDL1 can include a material having a higher etching selectivity than an etching selectivity of a material of the second conductive layer CDL2.

[0123] The first conductive layer CDL1 and the second conductive layer CDL2 can include a conductive material. The first conductive layer CDL1 and the second conductive layer CDL2 can include a metallic material. Further, the second conductive layer CDL2 can include a material having a lower reflectivity than a reflectivity of a material of the first conductive layer CDL1. Accordingly, a display quality of the display panel DP can be improved by reducing the reflectivity on the upper surface of the second conductive layer CDL2 forming the upper surface of the barrier wall CPW. For example, the first conductive layer CDL1 can include aluminum (Al), and the second conductive layer CDL2 can include titanium (Ti). However, the materials of the first conductive layer CDL1 and the second conductive layer CDL2 are not limited thereto, and any appropriate material can be utilized.

[0124] The barrier wall CPW can receive a second driving voltage ELVSS (e.g., see Figure 4 ). Accordingly, the second driving voltage ELVSS can be provided to the upper electrode UE in contact with the barrier wall CPW.

[0125] In Figure 6 , as an example, the barrier wall CPW can have a tapered shape (i.e., an angle θ formed between a lower surface of the barrier wall CPW and a side surface of the barrier wall CPV can be less than 90 degrees); however, the disclosure is not limited thereto. For example, the barrier wall CPW can have an inverted tapered shape. In this case, the angle θ formed between the lower surface of the barrier wall CPW and the side surface of the barrier wall CPW can exceed 90 degrees.

[0126] In a plan view, the upper opening OP-U defined in the second conductive layer CDL2 can overlap the lower opening OP-U defined in the first conductive layer CDL1, and an area of the upper opening OP-U defined in the second conductive layer CDL2 can be less than an area of the upper opening OP-U defined in the first conductive layer CDL1.

[0127] In the cross-sectional view, the upper opening OP-U can include a first region OP-U1 defined by an inner surface of the first conductive layer CDL1 and a second region OP-U2 defined by an inner surface of the second conductive layer CDL2. In the cross-sectional view (as shown in FIG. 1C), a width and an area of the first region OP-U1 can be greater than a width and an area of the second region OP-U2. In the plan view, the inner surface of the second conductive layer CDL2 defining the second region OP-U2 can be closer to a center of the lower electrode LE than the inner surface of the first conductive layer CDL1 defining the first region OP-U1. A portion of the second conductive layer CDL2 of the partition wall CPW that is closer to the center of the lower electrode LE in the plan view than the inner surface of the first conductive layer CDL1 defining the first region OP-U1 can be defined as a tip portion. Figure 6 In the cross-sectional view (as shown in FIG. 1C), a width and an area of the first region OP-U1 can be greater than a width and an area of the second region OP-U2. In the plan view, the inner surface of the second conductive layer CDL2 defining the second region OP-U2 can be closer to a center of the lower electrode LE than the inner surface of the first conductive layer CDL1 defining the first region OP-U1. A portion of the second conductive layer CDL2 of the partition wall CPW that is closer to the center of the lower electrode LE in the plan view than the inner surface of the first conductive layer CDL1 defining the first region OP-U1 can be defined as a tip portion.

[0128] In the plan view, an area of the upper opening OP-U defined in the first conductive layer CDL1 can be greater than an area of the light emitting opening OP-E defined in the pixel defining layer ISL, and the first conductive layer CD-1 can expose a portion of an upper surface of the pixel defining layer ISL through the upper opening OP-U.

[0129] The light emitting pattern EP can be disposed on the lower electrode LE. The light emitting pattern EP can include a light emitting layer including a light emitting material.

[0130] The light emitting pattern EP can further include a hole injection layer (HIL) and a hole transport layer (HTL) arranged between the lower electrode LE and the light emitting layer, and can further include an electron transport layer (ETL) and an electron injection layer (EIL) arranged on the light emitting layer.

[0131] The light emitting pattern EP can be patterned by the tip portion defined in the partition wall CPW. The light emitting pattern EP can be disposed within the lower opening OP-L, the light emitting opening OP-E, and the upper opening OP-U. The light emitting pattern EP can cover a portion of the upper surface of the pixel defining layer ISL exposed from the upper opening OP-U.

[0132] According to the disclosure, the light emitting pattern EP can be patterned and deposited in units of pixels by means of the tip portion defined in the partition wall CPW. That is, the light emitting pattern EP can be commonly formed (e.g., concurrently formed) using an opening mask, but can be easily separated in units of pixels by the partition wall CPW.

[0133] When a separate mask (e.g., a fine metal mask (FMM)) is used to pattern the light emitting pattern EP, a support spacer protruding from the partition wall to support the separate mask can be provided. Also, because the separate mask is spaced apart from the substrate surface on which the patterning is performed by the height of the partition wall and the support spacer, improvement of resolution can be limited. Also, when the mask is in contact with the support spacer, foreign matter can be left on the support spacer after the patterning process for the light emitting pattern EP, and the support spacer can be provided to be damaged due to the molding of the mask. Accordingly, a defective display panel can be formed.

[0134] In the present disclosure, because the light emitting pattern EP is patterned without a separate mask in contact with the internal configuration of the display panel DP, the defect rate is reduced, and thus, a display panel DP having improved reliability can be provided. In particular, when a large area display panel DP is manufactured, a display panel DP in which the process cost is reduced due to the omission of the production of a large area mask can be provided, and because the large area display panel DP is not affected by defects occurring in the large area mask, the reliability can be improved.

[0135] Figure 6 An example of a state in which the light emitting pattern EP does not come into contact with the inner surface of the first conductive layer CDL1 defining the upper opening OP-U is exemplarily shown; however, the present disclosure is not limited thereto. For example, the light emitting pattern EP can come into contact with the inner surface of the first conductive layer CDL1 defining the upper opening OP-U.

[0136] The upper electrode UE can be disposed on the light emitting pattern EP. The upper electrode UE can be patterned by means of the tip portion defined in the partition wall CPW. The upper electrode UE can come into contact with the inner surface of the first region OP-U1 of the first conductive layer CDL1 defining the upper opening OP-U. Accordingly, the upper electrode UE can be electrically connected to the partition wall CPW, and can receive the second driving voltage ELVSS through the partition wall CPW (e.g., see Figure 4 ).

[0137] According to the present disclosure, because the upper electrode UE is not provided in the form of a common layer overlapping the entire light emitting pattern EP, a leakage current along the common layer can not occur (or any such leakage current can be significantly reduced). Also, because the upper electrode UE is electrically connected to the partition wall CPW having a relatively large thickness, the driving resistance can be reduced (e.g., the resistance to the driving signal can be reduced), and thus, a light emitting element ED having improved light emitting efficiency and having an increased lifespan can be provided.

[0138] The cover pattern CP can be disposed on the upper electrode UE inside the upper opening OP-U. The cover pattern CP can be patterned by a tip portion defined in the partition wall CPW. According to some embodiments of the disclosure, the cover pattern CP can be omitted.

[0139] Figure 6 The state in which the cover pattern CP does not contact the inner surface of the first conductive layer CDL1 defining the upper opening OP-U is exemplarily illustrated; however, the disclosure is not limited thereto. For example, the cover pattern CP can be formed to contact the inner surface of the first conductive layer CDL1 defining the upper opening OP-U.

[0140] The dummy pattern DMP can be disposed on the partition wall CPW. The dummy pattern DMP can completely cover the upper surface of the partition wall CPW. The dummy pattern DMP can cover at least a portion of the inner surface of the second conductive layer CDL2 defining the upper opening OP-U. In some examples, a portion of the dummy pattern DMP can overlap the inner surface of the second conductive layer CDL2 defining the second area OP-U2.

[0141] The dummy pattern DMP can include an organic layer L1, a conductive layer L2, and a cover layer L3.

[0142] The organic layer L1 can be formed by the same process as that of the emission pattern EP, can have the same or substantially the same structure as that of the emission pattern EP, and can include the same or substantially the same material as that of the emission pattern EP. The organic layer L1 can be spaced apart from the emission pattern EP. The organic layer L1 can correspond to a residue separated from the emission pattern EP by the partition wall CPW when the emission pattern EP is commonly formed (e.g., concurrently formed).

[0143] The conductive layer L2 can be disposed on the organic layer L1. The conductive layer L2 can be formed by the same process as that of the upper electrode UE, can have the same or substantially the same structure as that of the upper electrode UE, and can include the same or substantially the same material as that of the upper electrode UE. The conductive layer L2 can be spaced apart from the upper electrode UE. The conductive layer L2 can correspond to a residue separated from the upper electrode UE by the partition wall CPW when the upper electrode UE is commonly formed (e.g., concurrently formed).

[0144] The cover layer L3 can be disposed on the conductive layer L2. The cover layer L3 can be formed by the same process as that of the cover pattern CP, can have the same or substantially the same structure as that of the cover pattern CP, and can include the same or substantially the same material as that of the cover pattern CP. The cover layer L3 can be spaced apart from the cover pattern CP. The cover layer L3 can correspond to a residue separated from the cover pattern CP by the partition wall CPW when the cover pattern CP is commonly formed (e.g., concurrently formed).

[0145] A thin film encapsulation layer TFE can be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE can include a lower encapsulation inorganic layer LIL, an encapsulation organic layer OL, and an upper encapsulation inorganic layer UIL.

[0146] The lower encapsulation inorganic layer LIL can be formed on the partition wall CPW and the upper electrode UE, and can be formed within the upper opening OP-U. The encapsulation organic layer OL can be formed on the lower encapsulation inorganic layer LIL, and the upper encapsulation inorganic layer UIL can be formed on the encapsulation organic layer OL. In some examples, the lower encapsulation inorganic layer LIL can cover the dummy pattern DMP and the upper electrode UE (or the cap pattern CP). Further, the lower encapsulation inorganic layer LIL can be in contact with an inner surface of the first conductive layer CDL1 that defines the upper opening OP-U. The lower encapsulation inorganic layer LIL can be in contact with a lower surface of the second conductive layer CDL2 that is exposed from the first conductive layer CDL1. The lower encapsulation inorganic layer LIL can cover an entire upper surface of the dummy pattern DMP. The lower encapsulation inorganic layer LIL can have an integral shape.

[0147] The lower encapsulation inorganic layer LIL and the upper encapsulation inorganic layer UIL can protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic layer OL can protect the display element layer DP-OLED from foreign substances such as dust particles.

[0148] Figure 7 is a cross-sectional view of the display panel DP taken along a line II-II' of Figure 3 will be described with reference to Figure 6 and the description for the same reference numerals can not be repeated. Figure 7 is shown. The display panel DP includes a display area DA and a non-display area NDA. Figure 7

[0149] Reference will be made to Figure 6 and Figure 7 ​The second driving voltage line VL2 can be disposed on the third insulating layer 30 overlapping the non-display area NDA. The second driving voltage line VL2 can include a plurality of layers. For example, the second driving voltage line VL2 can include a first electrode layer SD1 and a second electrode layer SD2. The first electrode layer SD1 can be disposed on the third insulating layer 30, and the second electrode layer SD2 can be disposed on the first electrode layer SD1 and the fourth insulating layer 40. The second electrode layer SD2 can be connected to the first electrode layer SD1. Since the second electrode layer SD2 extends to overlap the scan driving unit SDV, a narrow bezel can be implemented (e.g., formed). Accordingly, even when a width (e.g., as defined along the first direction DR1) of the first electrode layer SD1 is reduced, the second electrode layer SD2 can be provided by extending toward the scan driving unit SDV (e.g., in the first direction DR1), and thus, a total resistance of the second driving voltage line VL2 can be reduced. However, this is illustrative, and the second driving voltage line VL2 can include only one of the first electrode layer SD1 and the second electrode layer SD2.

[0150] The partition wall CPW can extend from a boundary between the display area DA and the non-display area NDA in a direction away from the display area DA. That is, the partition wall CPW can extend from the boundary between the display area DA and the non-display area NDA in a direction opposite to the first direction DR1. The partition wall CPW extending to the non-display area NDA can be disposed on the pixel definition layer ISL, the fifth insulating layer 50, and the second driving voltage line VL2. The partition wall CPW can be in contact with the second driving voltage line VL2. For example, the partition wall CPW can be in contact with the second electrode layer SD2 of the second driving voltage line VL2. Accordingly, the upper electrode UE in contact with the partition wall CPW can be electrically connected to the second driving voltage line VL2 in contact with the partition wall CPW. Accordingly, since the driving voltage is transmitted to the upper electrode UE through the partition wall CPW having a relatively large thickness, a voltage drop of the driving voltage can be reduced.

[0151] A portion of the second driving voltage line VL2 can be exposed without being covered by the fifth insulating layer 50 and the pixel-defining layer ISL. For example, in a plan view, the portion of the second driving voltage line VL2 can not overlap the fifth insulating layer 50 and the pixel-defining layer ISL. Accordingly, the exposed portion of the second driving voltage line VL2 can be in contact with the partition wall CPW. For example, after the fifth insulating layer 50 and the pixel-defining layer ISL are formed, a portion of the second driving voltage line VL2 can be exposed by an additional patterning process. In some examples, when the fifth insulating layer 50 is patterned, for example, when the connection contact hole CNT-3 is formed, the openings through which a portion of the second driving voltage line VL2 is exposed can be formed together (e.g., concurrently), and when the light-emitting opening OP-E is formed in the pixel-defining layer ISL, the openings through which a portion of the second driving voltage line VL2 is exposed can be formed together (e.g., concurrently).

[0152] The scan driving unit SDV can include a plurality of thin film transistors formed by the same process as a process of a pixel circuit PDC (e.g., see Figure 3 ) of the pixel PX (e.g., see Figure 4 ).

[0153] The dam DMM can be disposed in the non-display area NDA. The dam DMM can include a plurality of insulating layers. For example, the dam DMM can include a first layer formed in the same process as a process of the fourth insulating layer 40, a second layer formed in the same process as a process of the fifth insulating layer 50, and a third layer formed in the same process as a process of the pixel-defining layer ISL. However, the present disclosure is not limited thereto, and the dam DMM can include four or more layers, unlike the illustration of Figure 7 The encapsulation organic layer OL can extend to an area in which the dam DMM is formed. That is, when the encapsulation organic layer OL is formed, the dam DMM can be used to control the flow of monomers.

[0154] The display panel DP can include a plurality of auxiliary connection electrodes PCNE. The auxiliary connection electrode PCNE can be formed in the same process as a process of the lower electrode LE. In some embodiments, the auxiliary connection electrode PCNE can be omitted.

[0155] Figure 8 is an enlarged view of an area corresponding to the area AA' of Figure 7 . Figure 8 is a view illustrating the partition wall CPW and the second driving voltage line VL2.

[0156] Referring to Figure 8The first electrode layer SD1 and the second electrode layer SD2 of the second driving voltage line VL2 can include first voltage conductive layers VCL1-1 and VCL1-2, second voltage conductive layers VCL2-1 and VCL2-2 disposed on the first voltage conductive layers VCL1-1 and VCL1-2, respectively, and third voltage conductive layers VCL3-1 and VCL3-2 disposed on the second voltage conductive layers VCL2-1 and VCL2-2, respectively. That is, the first electrode layer SD1 can include a 1-1st voltage conductive layer VCL1-1, a 2-1st voltage conductive layer VCL2-1, and a 3-1st voltage conductive layer VCL3-1, and the second electrode layer SD2 can include a 1-2nd voltage conductive layer VCL1-2, a 2-2nd voltage conductive layer VCL2-2, and a 3-2nd voltage conductive layer VCL3-2.

[0157] The thicknesses of the second voltage conductive layers VCL2-1 and VCL2-2 can be greater than the thicknesses of the first voltage conductive layers VCL1-1 and VCL1-2 and the third voltage conductive layers VCL3-1 and VCL3-2. The first voltage conductive layers VCL1-1 and VCL1-2 and the third voltage conductive layers VCL3-1 and VCL3-2 can include a first material, and the second voltage conductive layers VCL2-1 and VCL2-2 can include a second material different from the first material. The electrical conductivity of the first material can be lower than the electrical conductivity of the second material. The first conductive layer CDL1 and the second voltage conductive layers VCL2-1 and VCL2-2 can include the same or substantially the same material, and the second conductive layer CDL2, the first voltage conductive layers VCL1-1 and VCL1-2, and the third voltage conductive layers VCL3-1 and VCL3-2 can include the same or substantially the same material. For example, the first conductive layer CDL1 and the second voltage conductive layers VCL2-1 and VCL2-2 can include aluminum (Al), and the second conductive layer CDL2, the first voltage conductive layers VCL1-1 and VCL1-2, and the third voltage conductive layers VCL3-1 and VCL3-2 can include titanium (Ti). However, the materials of the first conductive layer CDL1 and the second conductive layer CDL2 and the materials of the first to third voltage conductive layers VCL1-1, VCL1-2, VCL2-1, VCL2-2, VCL3-1, and VCL3-2 are not limited to the above-described materials and can be appropriately modified.

[0158] Figure 9 is a magnified schematic view of a region corresponding to the region AA' of Figure 7 is a magnified schematic view of a region corresponding to the region AA' of Figure 9 is a view showing the partition wall CPW and the second driving voltage line VL2a.

[0159] Referring to Figure 9 , the second driving voltage line VL2a can include a first electrode layer SD1 (see, for example,Figure 7 ) and one of the second electrode layers SD2 (see, for example, Figure 7 ) and one of the second electrode layers SD2 (see, for example,

[0160] The thickness of the second voltage conductive layer VCL2 can be greater than the thickness of the first voltage conductive layer VCL1 and the thickness of the third voltage conductive layer VCL3. The first voltage conductive layer VCL1 and the third voltage conductive layer VCL3 can include a first material, and the second voltage conductive layer VCL2 can include a second material different from the first material. The conductivity of the first material can be lower than the conductivity of the second material. The first conductive layer CDL1 and the second voltage conductive layer VCL2 can include the same or substantially the same material, and the second conductive layer CDL2, the first voltage conductive layer VCL1, and the third voltage conductive layer VCL3 can include the same or substantially the same material. For example, the first conductive layer CDL1 and the second voltage conductive layer VCL2 can include aluminum (Al), and the second conductive layer CDL2, the first voltage conductive layer VCL1, and the third voltage conductive layer VCL3 can include titanium (Ti). However, the materials of the first conductive layer CDL1 and the second conductive layer CDL2 and the materials of the first to third voltage conductive layers VCL1, VCL2, and VCL3 are not limited to the above-described materials and can be appropriately modified.

[0161] Referring to Figures 7 to 9 , the second driving voltage line VL2 or VL2a can include the first to third voltage conductive layers VCL1-1, VCL1-2, VCL2-1, VCL2-2, VCL3-1, and VCL3-2 or VCL1, VCL2, and VCL3, and the partition wall CPW can include the first conductive layer CDL1 and the second conductive layer CDL2. The third voltage conductive layer VCL3-2 or VCL3 of the second driving voltage line VL2 or VL2a can be in contact with the second conductive layer CDL2 of the partition wall CPW, and adhesion reliability can be improved (e.g., increased) by the characteristics of the materials described above.

[0162] According to the above description, the upper electrode and the driving voltage line are electrically connected through the partition wall. Thus, since the driving voltage is transmitted to the upper electrode through the partition wall having a relatively large thickness, the voltage drop of the driving voltage can be reduced.

[0163] Further, the conductive layers of the driving voltage line and the conductive layers of the partition wall can include different materials and can be in contact with each other. For example, because the conductive layer including titanium of the driving voltage line and the conductive layer including aluminum of the partition wall are in contact with each other, adhesion reliability can be improved (e.g., increased) by the characteristics of the materials.

[0164] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the inventive concept.

[0165] Spatially relative terms such as“beneath,”“below,”“lower,”“under,”“above,” and“on” are used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as depicted in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as“below” or“beneath” or“under” other elements or features would then be oriented“above” the other elements or features. Thus, the example term“below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being“between” two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0166] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and“including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0167] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or both A and B. When used as an adjective, such as “one or more of’ and “at least one of’, the expressions modify the entire list of elements and not just the individual elements in the list. For example, the expressions “one or more of A, B, and C”, “at least one of A, B, and C”, and “at least one selected from the group consisting of A, B, and C” mean A alone, B alone, C alone, both A and B, both A and C, both B and C, or all of A, B, and C.

[0168] Furthermore, as used in this specification and the appended claims, the terms “can” and “could” mean “one or more embodiments of the present inventive concept”. Also, the term “exemplary” is intended to mean an example or an illustration.

[0169] It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to” or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to” or “in contact with” another element or layer, there are no intervening elements or layers present.

[0170] As used herein, the terms “substantially”, “approximately”, and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0171] As used herein, the terms “use” and “used” can be considered synonymous to the terms “utilize” and “utilized”, respectively.

[0172] While the above has been described with reference to certain embodiments of the present disclosure, it is understood that various modifications and changes can be made by those skilled in the art or ordinary skilled in the art in suitable ways without departing from the spirit and technical scope of the present disclosure as defined by the claims and their equivalents. Accordingly, the technical scope of the present disclosure is not limited to the detailed description of the specification, but is defined by the claims.

Claims

1. A display panel, comprising: a base layer including a display area and a non-display area adjacent to the display area; a lower electrode on the base layer and overlapping the display area; a driving voltage line on the base layer and overlapping the non-display area; a pixel definition layer on the base layer, covering a portion of the lower electrode and defining a light emission opening; a light emission pattern within the light emission opening and on the lower electrode; a partition wall on the pixel definition layer and the driving voltage line and defining an upper opening corresponding to the light emission opening; and an upper electrode on the light emission pattern and in contact with an inner surface of the partition wall defining the upper opening, wherein the driving voltage line is in contact with the partition wall. The partition wall extends in a direction away from the display area from a boundary between the display area and the non-display area.

2. The display panel of claim 1, wherein, The upper electrode and the driving voltage line are electrically connected.

3. The display panel of claim 1, wherein, The partition wall includes:

4. The display panel of any one of claims 1 to 3, wherein, a first conductive layer having a first conductivity; and a second conductive layer having a second conductivity lower than the first conductivity and on the first conductive layer. A thickness of the first conductive layer is greater than a thickness of the second conductive layer.

5. The display panel of claim 4, wherein, An inner surface of the first conductive layer defines a first area of the upper opening, and an inner surface of the second conductive layer defines a second area of the upper opening, and 6. The display panel of claim 4, wherein, wherein, in a plan view, the inner surface of the second conductive layer defining the second area is closer to a center of the lower electrode than the inner surface of the first conductive layer defining the first area. 7.The display panel of claim 4, further comprising: a lower encapsulation inorganic layer on the upper electrode and the partition wall; an encapsulation organic layer on the lower encapsulation inorganic layer; and an upper encapsulation inorganic layer on the encapsulation organic layer, wherein the lower encapsulation inorganic layer is in contact with an inner surface of the first conductive layer and a lower surface of the second conductive layer. The driving voltage line includes: a first voltage conductive layer; 8. The display panel of claim 4, wherein, a second voltage conductive layer on the first voltage conductive layer; and a third voltage conductive layer on the second voltage conductive layer, and wherein a thickness of the second voltage conductive layer is greater than a thickness of the first voltage conductive layer and a thickness of the third voltage conductive layer. The driving voltage line includes a first electrode layer and a second electrode layer on the first electrode layer, the second electrode layer being in contact with the partition wall. 10.A display panel, comprising:

9. The display panel of claim 4, wherein, a base layer including a display area and a non-display area adjacent to the display area; a lower electrode on the base layer and overlapping the display area; a driving voltage line on the base layer and overlapping the non-display area; a pixel definition layer on the base layer, covering a portion of the lower electrode and defining a light emission opening; a light emission pattern within the light emission opening and on the lower electrode; a partition wall defining an upper opening corresponding to the light emission opening; and an upper electrode on the light emission pattern and in contact with an inner surface of the partition wall defining the upper opening, wherein the driving voltage line is in contact with the partition wall. ​ ​ The partition wall extends from a boundary between the display region and the non-display region in a direction away from the display region and electrically connects the upper electrode and the driving voltage line. The partition wall extends from a boundary between the display region and the non-display region in a direction away from the display region and electrically connects the upper electrode and the driving voltage line.

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